`timescale 1ns / 1ps
module smg(
led,
clk,
rst_n,
duan,
wei
);
output led;//led
input clk;//100MHz时钟
input rst_n;//复位信号
output reg[7:0] duan;//数码管段选
output reg[3:0] wei;//数码管位选
* h( ]2 f' v% [% Z6 [+ P% @; ?- {/******************数码管位选定义**************************/
parameter AN1=4'b0111,AN2=4'b1011,AN3=4'b1101,AN4=4'b1110;
7 F; {% k, @2 K( P3 E
/*****************数码管段选定义********************************/
parameter zero=8'b0000_0011,one =8'b1001_1111,
two = 8'b0010_0101,three =8'b0000_1101,four = 8'b1001_1001,
five = 8'b0100_1001,six =8'b0100_0001,seven = 8'b0001_1111,
eight = 8'b0000_0001,nine = 8'b0000_1001;
0 j6 }* _: M; j1 J m$ A/*************数码管带小数点的段选定义****************************/
parameter zero_dp=8'b0000_0010,one_dp =8'b1001_1110,
two_dp = 8'b0010_0100,three_dp =8'b0000_1100,four_dp = 8'b1001_1000,
five_dp = 8'b0100_1000,six_dp =8'b0100_0000,seven_dp = 8'b0001_1110,
eight_dp = 8'b0000_0000,nine_dp =8'b0000_1000;
s/ K; J( J, Q6 }! q! \5 E* c/***********1HZ分频模块 提供时钟秒基准***************************************/
reg[25:0] cnt;//x/100 000000=0.5 x=50 000000 26位
reg clk_1;
always @(posedge clk )
begin
if(cnt==50000000)
begin
cnt<=26'b0;
clk_1<=~clk_1;
end
else
cnt<=cnt+26'b1;
end
- o5 z- |- @3 G. I$ k; j/***********1000HZ分频模块 为数码管刷新用*********************************/
reg[15:0] cnt2;//50 000
reg clk_1k;
always @(posedge clk )
begin
if(cnt2==50000)
begin
cnt2<=16'b0;
clk_1k<=~clk_1k;
end
else
cnt2<=cnt2+16'b1;
end
& D& }) O* ^9 e+ N1 w
/*********LED每隔1秒状态翻转一次*****************************************/
reg ledr;
always @(posedge clk_1 or negedge rst_n)
begin
if(!rst_n)
ledr<=1'b1;
else
ledr<=~ledr;
end
1 G$ ~' k" S! s N: J5 cassign led=ledr;
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/********下面是秒与分的计时*****************************************/
reg [5:0] miao;
reg[5:0] fen;
always@(posedge clk_1 or negedge rst_n)
begin
if(!rst_n)//复位
begin
miao<=10;
fen<=12;
end
else
begin
miao<=miao+6'b1;//每隔一秒,秒自加1
if(miao==59)//如果秒等于59
begin
miao<=6'b0;//
fen<=fen+6'b1;
if(fen==59)
fen<=6'b0;
end
end
end
/**********下面开始显示秒,分钟************************************/
reg [1:0] count;
always @(posedge clk_1k or negedge rst_n)
begin
if(!rst_n)//复位
begin
duan<=zero;
wei<=4'b0000;
end
else
begin
count<=count+2'b1;//相当于每隔4ms数码管整体刷新一次,第一秒,刷新秒的个 //位,第二秒,刷新秒的十位,第三秒刷新分的个位,第四秒刷新分的十位
if(count==2'b00)
begin
wei<=AN1;//首先显示秒的个位
case(miao%10)
0:duan<=zero;
1:duan<=one;
2:duan<=two;
3:duan<=three;
4:duan<=four;
5:duan<=five;
6:duan<=six;
7:duan<=seven;
8:duan<=eight;
9:duan<=nine;
endcase
end
elseif(count==2'b01)
begin
wei<=AN2;//显示秒的十位
case(miao/10)
0:duan<=zero;
1:duan<=one;
2:duan<=two;
3:duan<=three;
4:duan<=four;
5:duan<=five;
6:duan<=six;
7:duan<=seven;
8:duan<=eight;
9:duan<=nine;
endcase
end
elseif(count==2'b10)
begin
wei<=AN3;//显示十的个位
case(fen%10)
0:duan<=zero_dp;
1:duan<=one_dp;
2:duan<=two_dp;
3:duan<=three_dp;
4:duan<=four_dp;
5:duan<=five_dp;
6:duan<=six_dp;
7:duan<=seven_dp;
8:duan<=eight_dp;
9:duan<=nine_dp;
endcase
end
elseif(count==2'b11)
begin
count<=2'b00;
wei<=AN4;//显示十的十位
case(fen/10)
0:duan<=zero;
1:duan<=one;
2:duan<=two;
3:duan<=three;
4:duan<=four;
5:duan<=five;
6:duan<=six;
7:duan<=seven;
8:duan<=eight;
9:duan<=nine;
endcase
end
end
end
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endmodule
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端口配置如下:
% a6 y; p' c u: i# PlanAhead Generated physical constraints
6 s6 p% O3 e' yNET "duan[7]" LOC = T17;
NET "duan[6]" LOC = T18;
NET "duan[5]" LOC = U17;
NET "duan[4]" LOC = U18;
NET "duan[3]" LOC = M14;
NET "duan[2]" LOC = N14;
NET "duan[1]" LOC = L14;
NET "duan[0]" LOC = M13;
NET "wei[3]" LOC = N16;
NET "wei[2]" LOC = N15;
NET "wei[1]" LOC = P18;
NET "wei[0]" LOC = P17;
NET "clk" LOC = V10;
NET "rst_n" LOC=T10;
NET "led" LOC =T11;
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