转——ZRtech Altera CycloneIV FPGA开发板——按键控制数码管

Zedd · 发表于 2019-4-26 07:30

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转——ZRtech Altera CycloneIV FPGA开发板——按键控制数码管

1、同样新建工程

2、本实验要实现的功能是：当程序下载进去时，某一位的数码管上显示的数字是0，当对应按键每按下一次，相应数码管上的数字会逐渐增1，当数字增到F时，会重新回到0，继续开始从0增加。当按下其他按键时，之前在那个数码管上显示的数字会对应的显示到现在按下的按键所对应的数码管上面。具体程序如下：
//key———seg
module key(clk,Key4,Key3,Key2,Key1,DS_EN4,DS_EN3,DS_EN2,DS_EN1,DS_A,DS_B,DS_C,DS_D,DS_E,DS_F,DS_G,DS_DP);

input clk;
input Key4,Key3,Key2,Key1;
output wire DS_EN4,DS_EN3,DS_EN2,DS_EN1;
output wire DS_A,DS_B,DS_C,DS_D,DS_E,DS_F,DS_G,DS_DP;

wire [3:0]Key_r;
wire [3:0]wei;
wire [7:0]duan;
wire clk_1k,clk_1s;
reg [7:0]duan_r;
reg [3:0]wei_r;
reg [3:0]num;

assign Key_r={Key4,Key1,Key2,Key3};
assign {DS_EN1,DS_EN2,DS_EN3,DS_EN4}=wei; //低电平选中对应数码管
assign {DS_DP,DS_G,DS_F,DS_E,DS_D,DS_C,DS_B,DS_A}=duan; //数码管共阴极

initial
begin
wei_r<=4'b1111; //数码管全部不亮
duan_r<=8'b00000000;
num<=4'b0000;
end

always @(posedge clk_1s)
begin
  if(Key_r==4'b1110)
begin
wei_r<=4'b1110;
if(num<15)
   num<=num+1;
else if(num==15)
   num<=0;
end
  else if(Key_r==4'b1101)
begin
wei_r<=4'b1101;
if(num<15)
   num<=num+1;
else if(num==15)
   num<=0;
end
  else if(Key_r==4'b1011)
begin
wei_r<=4'b1011;
if(num<15)
   num<=num+1;
else if(num==15)
   num<=0;
end
  else if(Key_r==4'b0111)
begin
wei_r<=4'b0111;
if(num<15)
   num<=num+1;
else if(num==15)
   num<=0;
/*if(num==4'b1111)
   num<=4'b0000;
else
   num<=num+4'b0001;*/
end
end
/*always @(Key_r)
begin
  if(Key_r==4'b1110)
begin
wei_r<=4'b1110;
end
  else if(Key_r==4'b1101)
begin
wei_r<=4'b1101;
end
  else if(Key_r==4'b1011)
begin
wei_r<=4'b1011;
end
  else if(Key_r==4'b0111)
begin
wei_r<=4'b0111;
/*if(num==4'b1111)
   num<=4'b0000;
else
   num<=num+4'b0001;*/
//end

//end

assign wei=wei_r;
//assign Key=Key_r;
fp_k fp_1k(clk,clk_1k);
fp_s fp_1s(clk_1k,clk_1s);

/*always @(posedge clk_1s)
begin
  num<=0;
  if(num==15)
num<=0;
  else
num<=num+1;
end*/
always @(posedge clk_1k)
begin
  if(wei_r==4'b1110)
  case(num)
0: duan_r=7'b00111111;
1: duan_r=7'b00000110;
2: duan_r=7'b01011011;
3: duan_r=7'b01001111;
4: duan_r=7'b01100110;
5: duan_r=7'b01101101;
6: duan_r=7'b01111101;
7: duan_r=7'b00000111;
8: duan_r=7'b01111111;
9: duan_r=7'b01101111;
10: duan_r=7'b01110111;
11: duan_r=7'b01111100;
12: duan_r=7'b00111001;
13: duan_r=7'b01011110;
14: duan_r=7'b01111001;
15: duan_r=7'b01110001;
default: duan_r=7'b00000000;
  endcase
  else if(wei_r==4'b1101)
  case(num)
0: duan_r=7'b00111111;
1: duan_r=7'b00000110;
2: duan_r=7'b01011011;
3: duan_r=7'b01001111;
4: duan_r=7'b01100110;
5: duan_r=7'b01101101;
6: duan_r=7'b01111101;
7: duan_r=7'b00000111;
8: duan_r=7'b01111111;
9: duan_r=7'b01101111;
10: duan_r=7'b01110111;
11: duan_r=7'b01111100;
12: duan_r=7'b00111001;
13: duan_r=7'b01011110;
14: duan_r=7'b01111001;
15: duan_r=7'b01110001;
default: duan_r=7'b00000000;
  endcase
  else if(wei_r==4'b1011)
  case(num)
0: duan_r=7'b00111111;
1: duan_r=7'b00000110;
2: duan_r=7'b01011011;
3: duan_r=7'b01001111;
4: duan_r=7'b01100110;
5: duan_r=7'b01101101;
6: duan_r=7'b01111101;
7: duan_r=7'b00000111;
8: duan_r=7'b01111111;
9: duan_r=7'b01101111;
10: duan_r=7'b01110111;
11: duan_r=7'b01111100;
12: duan_r=7'b00111001;
13: duan_r=7'b01011110;
14: duan_r=7'b01111001;
15: duan_r=7'b01110001;
default: duan_r=7'b00000000;
  endcase
  else if(wei_r==4'b0111)
  case(num)
0: duan_r=7'b00111111;
1: duan_r=7'b00000110;
2: duan_r=7'b01011011;
3: duan_r=7'b01001111;
4: duan_r=7'b01100110;
5: duan_r=7'b01101101;
6: duan_r=7'b01111101;
7: duan_r=7'b00000111;
8: duan_r=7'b01111111;
9: duan_r=7'b01101111;
10: duan_r=7'b01110111;
11: duan_r=7'b01111100;
12: duan_r=7'b00111001;
13: duan_r=7'b01011110;
14: duan_r=7'b01111001;
15: duan_r=7'b01110001;
default: duan_r=7'b00000000;
  endcase
end
assign duan=duan_r;

endmodule
//分频1k-----1s
module fp_s(clk_1k,clk_1s);
input clk_1k;
output reg clk_1s;
reg [10:0]cout;
//reg clk_en;
initial
begin
  cout<=10'd0;
  clk_1s<=1'd0;
end
always @(posedge clk_1k)
begin
  if(cout==10'd500)
begin
cout<=10'd0;
clk_1s<=~clk_1s;
end
  else
begin
cout<=cout+1;
end
  //clk_1s<=clk_en;
end

endmodule
//分频48M-----1k
module fp_k(clk,clk_1k);
input clk;
output reg clk_1k;
reg [31:0]cout;
//reg clk_en;
initial
begin
  cout<=32'd0;
  clk_1k<=1'd0;
end
always @(posedge clk)
begin
  if(cout==32'd24000)
begin
cout<=32'd0;
clk_1k<=~clk_1k;
end
  else
begin
cout<=cout+1;
end
  //clk_1s<=clk_en;
end

endmodule

3、实验结果：

这是刚下载完成时的显示结果，对应右边第四个数码管亮

当按键S1按下时，数码管上面的数字会增加，这是按键按键下次时的结果

这是按下S3时，对应左数第二个数码管显示的结果

总结：这个程序里面没有用到按键消抖程序，打算用状态机消抖，暂时还没学到那一块，还有就是想让数字增加时，按键的时间必须稍微长一点，当长时间按下按键时，数码管上面的数字也会间隔1s增加，这个并不是我写程序最初的想法，我的想法是按下一次数字增一次，目前还没想到解决办法，希望大神指点一二。

gaoxings · 发表于 2019-4-26 18:44

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转——ZRtech Altera CycloneIV FPGA开发板——按键控制数码管

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