FPGA编程这些常见的错误终于会解决了(三)

cpupygu · 发表于 2019-4-18 16:09

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Quartus 常见警告和错误

1. Warning: VHDLProcess Statement warning at random.vhd(18): signal reset is in
statement, but is not in sensitivity list
---- 没把 singal 放到 process （）中

2. Warning: Found pins ing as undefined clocks and/or memory enables Info: Assuming node CLK is an undefined clock
-=----- 可能是说设计中产生的触发器没有使能端

3. Error: VHDLInteRFace Declaration error in clk_gen.vhd(29): interface object
"clk_scan" of mode out cannot be read. Change object mode to buffer or inout.
------ 信号类型设置不对， out 当作 buffer 来定义

4. Error: Nodeinstance "clk_gen1" instantiates undefined entity "clk_gen"
------- 引用的例化元件未定义实体－－ entity "clk_gen"

5. Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or
gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer

6. Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable
"dataout" may not be assigned a new in every possible path through the Process
Statement. Signal or variable "dataout" holds its previous in every path with no
new assignment, which may create a combinational loop in the current design.

7. Warning: VHDLProcess Statement warning at divider_10.vhd(17): signal "cnt" is
read inside the Process Statement but isn't in the Process Statement's sensivitity list
----- 缺少敏感信号

8. Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register

9. Warning: Reducedregister "counter_bcd7:counter_counter_clk|q_sig[3]" with
stuck clock port to stuck GND

10. Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked
by clock "class[1]" with clock skew larger than data delay. See Compilation
Report for details.

11. Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked
by clock "sign" with clock skew larger than data delay. See Compilation Report
for details.

12. Error: VHDLerror at counter_clk.vhd(90): actual port "class" of mode "in"
cannot be associated with formal port "class" of mode "out"
------ 两者不能连接起来

13. Warning: Ignored node in vector source file. Can't find corresponding node
name "class_sig[2]" in design.
------ 没有编写 testbench 文件，或者没有编辑输入变量的值 testbench 里是元件申明和映射

14. Error: VHDLBinding Indication error at freqdetect_top.vhd(19): port "class"
in design entity does not have std_logic_vector type that is specified for the
same generic in the associated component
--- 在相关的元件里没有当前文件所定义的类型

15. Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate"
because signal does not hold its outside clock edge

16. Warning: Found clock high time violation at 1000.0 ns on register "|fcounter|lpm_counter:temp_rtl_0|dffs[4]"

17. Warning: Compiler packed, optimized or synthesized away node "temp[19]".
Ignored vector source file node.
---"temp[19]" 被优化掉了

18. Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND

19. Warning: Design contains 2 input pin(s) that do not drive logic Warning: No output dependent on input pin "clk"
Warning: No output dependent on input pin "sign"
------ 输出信号与输入信号无关，

20. Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1"

21. Error: VHDLerror at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator "or"

22. Error: VHDLAssociation List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alARM", but formal parameter is not
declared
------- 连接表错误，形参"alarm" 赋值给实参，形参没定义，可能是形参与实参的位置颠倒了，规定形参在实参之前。

23. Error: Ignored construct behavier at period_counter.vhd(15) because of
previous errors
－－－－－－－－因为前一个错误而导致的错误

24. Error: VHDL error at period_counter.vhd(38): type of identifier "alarm" does
not agree with its usage as std_logic type
－－－－－－－－ "alarm" 的定义类型与使用的类型不一致

25Error: VHDL error at shift_reg.vhd(24): can't synthesize logic for statement
with conditions that test for the edges of multiple clocks
------- 同一进程中含有两个或多个 if(edge) 条件，（一个进程中之能有一个时钟沿）

26. Error: Can't resolve multiple constant drivers for net "datain_reg[22]" at
shift_reg.vhd(19)

27. can't infer register for signal "num[0]" because signal does not hold its
outside clock edge

28. Error: Can't elaborate top-level user hierarchy

29. Error: Can't resolve multiple constant drivers for net "cs_in" at led_key.vhd(32) ---------- 有两个以上赋值语句，不能确定“ cs_in ” 的值

30. Warning: Ignored node in vector source file. Can't find corresponding node
name "over" in design.
--------------- 在源文件中找不到对应的节点“ over ”。

31. Error: Can't access JTAG chain
无法找到下载链

32. Info: Assuming node "clk" is an undefined clock

fanichicl · 发表于 2019-4-18 17:32

顶顶

adogpp · 发表于 2019-4-18 18:03

学习了

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FPGA编程这些常见的错误终于会解决了(三)

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