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Quartus 常见警告和错误 1. Warning: VHDLProcess Statement warning at random.vhd(18): signal reset is in0 i2 T1 s: X) J( u
statement, but is not in sensitivity list- o. J1 |$ L! a; X: G
---- 没把 singal 放到 process ()中 ' @% v& \& ^7 N1 ^: g
2. Warning: Found pins ing as undefined clocks and/or memory enables Info: Assuming node CLK is an undefined clock! c& v9 o9 U# V) J# O) Q
-=----- 可能是说设计中产生的触发器没有使能端
/ i b: [. i+ @+ S3. Error: VHDLInteRFace Declaration error in clk_gen.vhd(29): interface object
2 U' l3 ~8 j6 d- t"clk_scan" of mode out cannot be read. Change object mode to buffer or inout.
& o0 ^; W" Q R( D' [------ 信号类型设置不对, out 当 作 buffer 来定义 ; ]0 z" q6 U& N1 V
4. Error: Nodeinstance "clk_gen1" instantiates undefined entity "clk_gen"- s, s& q3 ]$ `" ]
------- 引用的例化元件未定义实体-- entity "clk_gen" % c, }6 z7 n3 v
5. Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or
( Z+ P; e6 B# |0 W ^" R v h( P# Wgated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer
: \4 N1 t. I" |7 C! v6. Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable% ]; k9 a( Y& k5 I
"dataout" may not be assigned a new in every possible path through the Process+ J- M0 j* R0 o4 e- S
Statement. Signal or variable "dataout" holds its previous in every path with no8 k& o) e8 E, T% z
new assignment, which may create a combinational loop in the current design.
& Q$ J8 t5 J$ \% g7. Warning: VHDLProcess Statement warning at divider_10.vhd(17): signal "cnt" is
7 W5 H5 r. C( P' _3 b$ X# @2 ~) B5 lread inside the Process Statement but isn't in the Process Statement's sensivitity list
6 V4 P: u" q2 {) V9 I----- 缺少敏感信号
$ G6 x; ^- x$ h& @: {7 \8. Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register ( l+ q5 ~, ?& g1 u2 t V# t
9. Warning: Reducedregister "counter_bcd7:counter_counter_clk|q_sig[3]" with
" f8 O+ a7 ~8 m' A1 [1 k- F1 G+ n7 F1 xstuck clock port to stuck GND
4 Z/ q4 n+ T9 `0 x5 k10. Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked
# M! D' B+ q9 l8 j( Z+ A4 W, ?by clock "class[1]" with clock skew larger than data delay. See Compilation: c$ Z& e7 p1 N" O& {( N# C. f6 m6 ~% K% ^
Report for details. * `! P; a8 X; E% h a) ?
11. Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked) O/ L' u1 f# X7 T# n2 J
by clock "sign" with clock skew larger than data delay. See Compilation Report
$ ^/ u ~6 O9 D2 `. \for details.
1 ]# J# C8 u9 ~ s* t0 R G12. Error: VHDLerror at counter_clk.vhd(90): actual port "class" of mode "in"
2 W, x O3 d# W* Ecannot be associated with formal port "class" of mode "out"9 {9 |0 L/ `4 {/ p7 w9 J8 d
------ 两者不能连接起来
+ C# |& ]0 l2 G% a g13. Warning: Ignored node in vector source file. Can't find corresponding node
" N3 W2 h5 }+ t. Tname "class_sig[2]" in design./ Q0 c: z6 K' h8 S. X
------ 没有编写 testbench 文件,或者没有编辑输入变量的值 testbench 里是元件申明和映射
0 v0 L2 O8 Y. y; \# l14. Error: VHDLBinding Indication error at freqdetect_top.vhd(19): port "class"
7 Q- I) P ^$ Nin design entity does not have std_logic_vector type that is specified for the
, |- z$ R5 _$ J+ \same generic in the associated component
v) h, ? [/ m/ S) y k3 ^--- 在相关的元件里没有当前文件所定义的类型 + C6 q4 I# _/ M( d7 z* J4 r5 S
15. Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate"
" A1 J' [) D! p6 E; T( B( Abecause signal does not hold its outside clock edge
; D1 O* O1 ` V9 v16. Warning: Found clock high time violation at 1000.0 ns on register "|fcounter|lpm_counter:temp_rtl_0|dffs[4]" 7 c. G+ `' ^- @1 Q4 A3 X' \$ {
17. Warning: Compiler packed, optimized or synthesized away node "temp[19]".
" ~) k! H0 p" F7 uIgnored vector source file node.' @4 R, [$ H: g' }4 b
---"temp[19]" 被优化掉了 ; q& m0 k/ S$ C
18. Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND
6 Q9 v/ i4 Q2 U& h2 W* _19. Warning: Design contains 2 input pin(s) that do not drive logic Warning: No output dependent on input pin "clk"
8 ^5 e3 o8 @: K4 ]6 iWarning: No output dependent on input pin "sign", y7 d( \& n8 e# b& J u
------ 输出信号与输入信号无关, e/ ^$ O) P" ~* n& @4 |
20. Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1"
$ F" e1 K! V( L0 t21. Error: VHDLerror at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator "or" 6 @* K/ Q" A: j4 S" o
22. Error: VHDLAssociation List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alARM", but formal parameter is not
. c- x, b8 L. W# ]* `% Zdeclared
# U4 S1 s. l1 U/ z- l: |! r7 D- J------- 连接表错误, 形参"alarm" 赋值给实参, 形参没定义, 可能是形参与实参的位置颠倒了,规定形参在实参之前。
+ U U) f n0 D8 c. u4 x4 }; x23. Error: Ignored construct behavier at period_counter.vhd(15) because of3 _0 v; Q" ^/ k1 y, [: q7 z
previous errors
1 w2 S$ o2 W& Z1 k--------因为前一个错误而导致的错误 2 x5 O. u# o& H8 v0 F$ d) q
24. Error: VHDL error at period_counter.vhd(38): type of identifier "alarm" does
$ A8 f3 M* j+ c* n- pnot agree with its usage as std_logic type
. s5 j6 [! F+ {+ u6 {-------- "alarm" 的定义类型与使用的类型不一致 + y. p! c2 o8 C/ S! e
25Error: VHDL error at shift_reg.vhd(24): can't synthesize logic for statement
" q+ x% s1 F/ i3 Y0 j2 pwith conditions that test for the edges of multiple clocks+ d: _% k0 C; `- b
------- 同一进程中含有两个或多个 if(edge) 条件,(一个进程中之能有一个时钟沿) 26. Error: Can't resolve multiple constant drivers for net "datain_reg[22]" at7 |1 R: a+ Q6 S) U/ [
shift_reg.vhd(19)
9 V6 Q. }& N# D# {& D0 f27. can't infer register for signal "num[0]" because signal does not hold its" ]" I5 V8 g& h5 L% b
outside clock edge 1 I" u, J8 L- `/ Y. a) U
28. Error: Can't elaborate top-level user hierarchy 0 l* i5 k* A5 ]4 q9 k
29. Error: Can't resolve multiple constant drivers for net "cs_in" at led_key.vhd(32) ---------- 有两个以上赋值语句,不能确定“ cs_in ” 的 值 - F' O% E, L8 e- N
30. Warning: Ignored node in vector source file. Can't find corresponding node
" L& J' ^* y, ?/ h2 P5 ?# A' Jname "over" in design.
) ^; C% y; }! ~9 G" |/ t--------------- 在源文件中找不到对应的节点“ over ”。
/ C ]' {8 ~. j* X8 E31. Error: Can't access JTAG chain& s6 y0 V- s6 P9 L4 ~
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( n# v G! e: T32. Info: Assuming node "clk" is an undefined clock : s9 f2 z3 X# R4 h$ D
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