在屏幕上显示大写字母DMH的VGA控制器

Zedd · 发表于 2019-4-11 11:17

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在屏幕上显示大写字母DMH的VGA控制器

基于ise14.7平台，用Nexys3开发板弄了一个显示程序。程序包含六部分

首先是顶层模块：

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 16:04:30 07/22/2015

// Design Name:

// Module Name: vga_initials

// Project Name:

// Target Devices:

// Tool versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module vga_initials(

input wire vidon,

input wire[9:0] hc,

input wire[9:0] vc,

input wire[0:31] M,

input wire[7:0] sw,

output wire[3:0] rom_addr4,

output reg[2:0] red,

output reg[2:0] green,

output reg[1:0] blue

);



      parameter hbp=10'b0010010000;//行显示后沿=144（128+16）

      parameter vbp=10'b0000011111;//场显示后沿=31（2+29）

      parameter W=32;

      parameter H=16;



      wire[10:0]C1,R1,rom_addr,rom_pix;

      reg spriteon,R,G,B;

      assign C1={2'b00,sw[3:0],5'b0001};

      assign R1={2'b00,sw[7:4],5'b0001};

      assign rom_addr=vc-vbp-R1;

assign rom_pix =hc-hbp-C1;

      assign rom_addr4=rom_addr[3:0];

      //Enable sprite video out when within the sprite region

      always@(*)

         begin

               if((hc>=C1+hbp)&&(hc<=C1+hbp+W)&&(vc>=R1+vbp)&&(vc<=R1+vbp+H))

                  spriteon=1;

               else

                  spriteon=0;

            end



      //输出彩色信号

      always@(*)

         begin

               red=0;

               green=0;

               blue=0;

               if((spriteon==1)&&(vidon==1))

                  begin

                        R=M[rom_pix];

                              G=M[rom_pix];

                              B=M[rom_pix];

                              red={R,R,R};

                              green={G,G,G};

                              blue={B,B};

                     end

            end

endmodule

然后是子模块1：

module clkdiv(

input wire mclk,

input wire clr,

output wire clk25

);

      reg[1:0]q;



      //2-bit counter

      always@(posedge mclk or posedge clr)

         begin

               if(clr==1)

                  q<=0;

               else

                  q<=q+1'b1;

            end



      assign clk25=q[1];//50MHz  时钟100MHz  （100M/2的1次方）=50MHz

endmodule

子模块2：

module vga_640x480(

input wire clk,

input wire clr,

output reg hsync,

output reg vsync,

output reg[9:0] hc,

output reg[9:0] vc,

output reg vidon

);



      parameter hpixels=10'b1100100000;//行像素点=800



      parameter vlines=10'b1000001001;//行数=521



      parameter hbp=10'b0010010000;//行显示后延=144（128+16）



      parameter hfp=10'b1100010000;//行显示前沿=748（128+16+640）



      parameter vbp=10'b0000011111;//场显示后沿=31（2+29）



      parameter vfp=10'b0111111111;//场显示前延=511（2+29+480）



      reg vsenable;//Enable for the vertical counter



      //行同步信号计数器

      always@(posedge clk or posedge clr)

            begin

                        if(clr==1)

                                 hc<=0;

                              else

                                 begin

                                       if(hc==hpixels-1)

                                          begin

                                                //The counter has reached the end of pixel count

                                                      hc<=0;//计数器复位

                                                      vsenable<=1;

                                                      //Enable the vertical counter to increment

                                             end

                                       else

                                          begin

                                                hc<=hc+1'b1;//Increment the horizontal counter

                                                      vsenable<=0;//Leave the vsenable off

                                          end

                                 end

                              end

      //产生hsync脉冲

      //当hc为0~127时，行同步脉冲为低电平

      always@(*)

      begin

         if(hc<96)

               hsync=0;

               else

               hsync=1;

      end



      //场同步信号计数器

      always@(posedge clk or posedge clr)

      begin

         if(clr==1)

               vc<=0;

               else

               if(vsenable==1)

                        begin

                        if(vc==vlines-1)

                                 //Reset when the number of lines is reached

                                    vc<=0;

                              else

                                 vc<=vc+1'b1;//场计数器+1

                        end

      end



      //产生vsync脉冲

      //当hc为0或1时，场同步脉冲为低电平

      always@(*)

      begin

         if(vc<2)

               vsync=0;

               else

               vsync=1;

      end



      //Enable video out when within the porches

      always@(*)

      begin

         if((hc<hfp)&&(hc>hbp)&&(vc<vfp)&&(vc>vbp))

               vidon=1;

               else

               vidon=0;

      end

endmodule

子模块3：

module vga_initials(

input wire vidon,

input wire[9:0] hc,

input wire[9:0] vc,

input wire[0:31] M,

input wire[7:0] sw,

output wire[3:0] rom_addr4,

output reg[2:0] red,

output reg[2:0] green,

output reg[1:0] blue

);



      parameter hbp=10'b0010010000;//行显示后沿=144（128+16）

      parameter vbp=10'b0000011111;//场显示后沿=31（2+29）

      parameter W=32;

      parameter H=16;



      wire[10:0]C1,R1,rom_addr,rom_pix;

      reg spriteon,R,G,B;

      assign C1={2'b00,sw[3:0],5'b0001};

      assign R1={2'b00,sw[7:4],5'b0001};

      assign rom_addr=vc-vbp-R1;

assign rom_pix =hc-hbp-C1;

      assign rom_addr4=rom_addr[3:0];

      //Enable sprite video out when within the sprite region

      always@(*)

         begin

               if((hc>=C1+hbp)&&(hc<=C1+hbp+W)&&(vc>=R1+vbp)&&(vc<=R1+vbp+H))

                  spriteon=1;

               else

                  spriteon=0;

            end



      //输出彩色信号

      always@(*)

         begin

               red=0;

               green=0;

               blue=0;

               if((spriteon==1)&&(vidon==1))

                  begin

                        R=M[rom_pix];

                              G=M[rom_pix];

                              B=M[rom_pix];

                              red={R,R,R};

                              green={G,G,G};

                              blue={B,B};

                     end

            end

endmodule

子模块四：

module prom_DMH(

input wire[3:0]addr,

      output wire[0:31]M

);

      reg[0:31]rom[0:15];//16个32位寄存器

      parameter data={

         32'b01111110000011000001101000000010,//0

            32'b01000001000011000001101000000010,//1

            32'b01000000100010100010101000000010,//2

            32'b01000000010010100010101000000010,//3

            32'b01000000001010100010101000000010,//4

            32'b01000000001010010100101000000010,//5

            32'b01000000001010010100101000000010,//6

            32'b01000000001010010100101111111110,//7

            32'b01000000001010001000101000000010,//8

            32'b01000000001010001000101000000010,//9

            32'b01000000001010001000101000000010,//10

            32'b01000000001010001000101000000010,//11

            32'b01000000010010000000101000000010,//12

            32'b01000000100010000000101000000010,//13

            32'b01000001000010000000101000000010,//14

            32'b01111110000010000000101000000010//15

      };

      integer i;

      initial

         begin

               for(i=0;i<16;i=i+1)

                  rom=data[(511-32*i)-:32];
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      assign M=rom[addr];
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endmodule7 Q* `0 R8 @8 L4 L/ o" @
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- w6 v5 s: M. D' D2 Z& W约束文件：$ {9 j2 H% }: B2 P

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Net "mclk" LOC=V10;
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## Buttons, R. O! \1 K5 {4 ^6 i/ @& t

7 {$ t' I3 @- x# J6 @Net "btn" LOC = B8;
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## Switches
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Net "sw<0>" LOC = T10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29N_GCLK2, Sch name = SW0
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Net "sw<1>" LOC = T9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32P_GCLK29, Sch name = SW1
% H0 D; a! A$ y1 G- D2 \3 ]# U* y, j8 m# p6 m7 l' |( a$ F
Net "sw<2>" LOC = V9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32N_GCLK28, Sch name = SW2
' R0 \1 A1 R  G6 C
& J" H9 n' C3 e) `Net "sw<3>" LOC = M8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40P, Sch name = SW34 R6 Y; V3 F" B0 Q5 r
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Net "sw<4>" LOC = N8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40N, Sch name = SW4
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Net "sw<5>" LOC = U8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41P, Sch name = SW5
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Net "sw<6>" LOC = V8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41N_VREF, Sch name = SW6
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8 \9 _* v9 i( eNet "sw<7>" LOC = T5 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW7; g! Q) H4 W) D. ]- B
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## VGA Connector, g: i) q0 d5 E4 q! z2 v! ~

* p) x9 U7 D, C/ W% r/ r) ?NET "red<0>" LOC = U7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L43P, Sch name = RED0; U8 V* y3 t, C/ r
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NET "red<1>" LOC = V7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L43N, Sch name = RED13 h. t1 {* _- M1 n7 |/ T
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NET "red<2>" LOC = N7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L44P, Sch name = RED2. q  A+ |* m3 ]! G6 B5 @
) {! [, E/ J8 F: C9 ^
NET "green<0>" LOC = P8 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L44N, Sch name = GRN01 N! O% j' P! |0 J5 k3 J6 c5 `" q

% n: J* T$ s/ _7 m5 gNET "green<1>" LOC = T6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L45P, Sch name = GRN17 }, `2 e5 {4 P: K  D

% T6 H8 c2 C0 y$ ^9 X' o, X$ |( ]+ X' RNET "green<2>" LOC = V6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L45N, Sch name = GRN2
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2 |( p# b! k& u- G. X4 H2 wNET "blue<0>" LOC = R7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L46P, Sch name = BLU1
  i3 o* D, k- G  ^& m7 B1 u, @+ |  o
NET "blue<1>" LOC = T7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L46N, Sch name = BLU2
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NET "Hsync" LOC = N6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L47P, Sch name = HSYNC5 X4 F& u$ ~8 U9 j7 z+ I/ H5 C
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NET "Vsync" LOC = P7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L47N, Sch name = VSYNC
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## Switches/ S+ N7 k! d1 J2 _' y

) H6 ]; u6 N# [; C2 k% gNet "sw<0>" LOC = T10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29N_GCLK2, Sch name = SW0
* I( f$ p2 j; z3 e2 \" `# P4 C* f' M
Net "sw<1>" LOC = T9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32P_GCLK29, Sch name = SW1
$ p" N  g: u: v" ~3 Q! E
& N' b0 |- t( N% ZNet "sw<2>" LOC = V9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32N_GCLK28, Sch name = SW2
6 w5 W+ W3 N% x# }* z5 N9 O. q( a
, D! S+ O, Y( q$ ~Net "sw<3>" LOC = M8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40P, Sch name = SW3
. {# C2 q3 f& a. y2 J% @: ~' Y7 H- y; A0 `
Net "sw<4>" LOC = N8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40N, Sch name = SW4* d4 K  Y  }  u% r/ t
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Net "sw<5>" LOC = U8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41P, Sch name = SW5( r  _0 z5 S% b& @

3 w& T' m7 O9 _  M- Y. l: ANet "sw<6>" LOC = V8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41N_VREF, Sch name = SW6
& F$ j/ w* {. E* c8 G: j, `; a1 a2 [+ V1 T) y3 z0 f, t3 Y- X4 H
Net "sw<7>" LOC = T5 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW76 U7 V" N# T* o% V) }' e
% n( q0 `- M3 Z( L* N, }% P% y  D

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以上是程序的全部内容: W5 i' W+ b' W
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编译后没有错误  经检验实际结果与预期结果一致
这是源程序所有文件

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relchhiclty · 发表于 2019-4-11 15:49

最近正在找这方面的资料谢谢楼主分享

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在屏幕上显示大写字母DMH的VGA控制器

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