在屏幕上显示大写字母DMH的VGA控制器

Zedd · 发表于 2019-4-11 11:17

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在屏幕上显示大写字母DMH的VGA控制器

基于ise14.7平台，用Nexys3开发板弄了一个显示程序。程序包含六部分

首先是顶层模块：

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 16:04:30 07/22/2015

// Design Name:

// Module Name: vga_initials

// Project Name:

// Target Devices:

// Tool versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module vga_initials(

input wire vidon,

input wire[9:0] hc,

input wire[9:0] vc,

input wire[0:31] M,

input wire[7:0] sw,

output wire[3:0] rom_addr4,

output reg[2:0] red,

output reg[2:0] green,

output reg[1:0] blue

);



      parameter hbp=10'b0010010000;//行显示后沿=144（128+16）

      parameter vbp=10'b0000011111;//场显示后沿=31（2+29）

      parameter W=32;

      parameter H=16;



      wire[10:0]C1,R1,rom_addr,rom_pix;

      reg spriteon,R,G,B;

      assign C1={2'b00,sw[3:0],5'b0001};

      assign R1={2'b00,sw[7:4],5'b0001};

      assign rom_addr=vc-vbp-R1;

assign rom_pix =hc-hbp-C1;

      assign rom_addr4=rom_addr[3:0];

      //Enable sprite video out when within the sprite region

      always@(*)

         begin

               if((hc>=C1+hbp)&&(hc<=C1+hbp+W)&&(vc>=R1+vbp)&&(vc<=R1+vbp+H))

                  spriteon=1;

               else

                  spriteon=0;

            end



      //输出彩色信号

      always@(*)

         begin

               red=0;

               green=0;

               blue=0;

               if((spriteon==1)&&(vidon==1))

                  begin

                        R=M[rom_pix];

                              G=M[rom_pix];

                              B=M[rom_pix];

                              red={R,R,R};

                              green={G,G,G};

                              blue={B,B};

                     end

            end

endmodule

然后是子模块1：

module clkdiv(

input wire mclk,

input wire clr,

output wire clk25

);

      reg[1:0]q;



      //2-bit counter

      always@(posedge mclk or posedge clr)

         begin

               if(clr==1)

                  q<=0;

               else

                  q<=q+1'b1;

            end



      assign clk25=q[1];//50MHz  时钟100MHz  （100M/2的1次方）=50MHz

endmodule

子模块2：

module vga_640x480(

input wire clk,

input wire clr,

output reg hsync,

output reg vsync,

output reg[9:0] hc,

output reg[9:0] vc,

output reg vidon

);



      parameter hpixels=10'b1100100000;//行像素点=800



      parameter vlines=10'b1000001001;//行数=521



      parameter hbp=10'b0010010000;//行显示后延=144（128+16）



      parameter hfp=10'b1100010000;//行显示前沿=748（128+16+640）



      parameter vbp=10'b0000011111;//场显示后沿=31（2+29）



      parameter vfp=10'b0111111111;//场显示前延=511（2+29+480）



      reg vsenable;//Enable for the vertical counter



      //行同步信号计数器

      always@(posedge clk or posedge clr)

            begin

                        if(clr==1)

                                 hc<=0;

                              else

                                 begin

                                       if(hc==hpixels-1)

                                          begin

                                                //The counter has reached the end of pixel count

                                                      hc<=0;//计数器复位

                                                      vsenable<=1;

                                                      //Enable the vertical counter to increment

                                             end

                                       else

                                          begin

                                                hc<=hc+1'b1;//Increment the horizontal counter

                                                      vsenable<=0;//Leave the vsenable off

                                          end

                                 end

                              end

      //产生hsync脉冲

      //当hc为0~127时，行同步脉冲为低电平

      always@(*)

      begin

         if(hc<96)

               hsync=0;

               else

               hsync=1;

      end



      //场同步信号计数器

      always@(posedge clk or posedge clr)

      begin

         if(clr==1)

               vc<=0;

               else

               if(vsenable==1)

                        begin

                        if(vc==vlines-1)

                                 //Reset when the number of lines is reached

                                    vc<=0;

                              else

                                 vc<=vc+1'b1;//场计数器+1

                        end

      end



      //产生vsync脉冲

      //当hc为0或1时，场同步脉冲为低电平

      always@(*)

      begin

         if(vc<2)

               vsync=0;

               else

               vsync=1;

      end



      //Enable video out when within the porches

      always@(*)

      begin

         if((hc<hfp)&&(hc>hbp)&&(vc<vfp)&&(vc>vbp))

               vidon=1;

               else

               vidon=0;

      end

endmodule

子模块3：

module vga_initials(

input wire vidon,

input wire[9:0] hc,

input wire[9:0] vc,

input wire[0:31] M,

input wire[7:0] sw,

output wire[3:0] rom_addr4,

output reg[2:0] red,

output reg[2:0] green,

output reg[1:0] blue

);



      parameter hbp=10'b0010010000;//行显示后沿=144（128+16）

      parameter vbp=10'b0000011111;//场显示后沿=31（2+29）

      parameter W=32;

      parameter H=16;



      wire[10:0]C1,R1,rom_addr,rom_pix;

      reg spriteon,R,G,B;

      assign C1={2'b00,sw[3:0],5'b0001};

      assign R1={2'b00,sw[7:4],5'b0001};

      assign rom_addr=vc-vbp-R1;

assign rom_pix =hc-hbp-C1;

      assign rom_addr4=rom_addr[3:0];

      //Enable sprite video out when within the sprite region

      always@(*)

         begin

               if((hc>=C1+hbp)&&(hc<=C1+hbp+W)&&(vc>=R1+vbp)&&(vc<=R1+vbp+H))

                  spriteon=1;

               else

                  spriteon=0;

            end



      //输出彩色信号

      always@(*)

         begin

               red=0;

               green=0;

               blue=0;

               if((spriteon==1)&&(vidon==1))

                  begin

                        R=M[rom_pix];

                              G=M[rom_pix];

                              B=M[rom_pix];

                              red={R,R,R};

                              green={G,G,G};

                              blue={B,B};

                     end

            end

endmodule

子模块四：

module prom_DMH(

input wire[3:0]addr,

      output wire[0:31]M

);

      reg[0:31]rom[0:15];//16个32位寄存器

      parameter data={

         32'b01111110000011000001101000000010,//0

            32'b01000001000011000001101000000010,//1

            32'b01000000100010100010101000000010,//2

            32'b01000000010010100010101000000010,//3

            32'b01000000001010100010101000000010,//4

            32'b01000000001010010100101000000010,//5

            32'b01000000001010010100101000000010,//6

            32'b01000000001010010100101111111110,//7

            32'b01000000001010001000101000000010,//8

            32'b01000000001010001000101000000010,//9

            32'b01000000001010001000101000000010,//10

            32'b01000000001010001000101000000010,//11

            32'b01000000010010000000101000000010,//12

            32'b01000000100010000000101000000010,//13

            32'b01000001000010000000101000000010,//14

            32'b01111110000010000000101000000010//15

      };

      integer i;

      initial

         begin

               for(i=0;i<16;i=i+1)

                  rom=data[(511-32*i)-:32];
5 K6 S, Z4 I- ^9 w/ D  z' \$ a8 y# \9 Q% X9 Y3 h+ ]1 T- ^* I7 A
         end+ n9 N0 V9 ?- b' G; l
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      assign M=rom[addr];
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" O6 p! W+ y: _0 C) E+ o& a5 oendmodule
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约束文件：
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# e: @, |. g! B7 A7 R0 uNet "mclk" LOC=V10;
6 `8 ~' C3 w3 W  O/ r( c1 w5 E" {7 {" h$ ]+ @  M. N
## Buttons3 k- S; Q1 b' a5 T# i+ Q( V

! m7 F  h! N1 n5 vNet "btn" LOC = B8;. F% R: T; v" R6 b5 B- O8 b- N

, ?- `3 x0 G: g! Y3 |- k% P; D) Y1 Z% B5 a. A6 j- k# X

5 n  J+ a1 a3 ^## Switches  y6 T" p8 U! ^7 c, M# o3 j6 {
) B) M5 g1 [' M
Net "sw<0>" LOC = T10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29N_GCLK2, Sch name = SW0  n! i! g$ B8 w7 s3 Q
) {) ^6 @5 W* q+ |
Net "sw<1>" LOC = T9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32P_GCLK29, Sch name = SW18 j% T2 e8 E2 E" H3 G  D# j
4 h, L9 X; Q! g5 e
Net "sw<2>" LOC = V9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32N_GCLK28, Sch name = SW2
) P3 n/ B& p- u8 r1 m
6 V$ \: z* V# }- D) WNet "sw<3>" LOC = M8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40P, Sch name = SW3
9 i6 t8 F9 [2 Q8 N0 _+ M9 h: e
8 Y6 ~( G$ g% g3 l5 M  DNet "sw<4>" LOC = N8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40N, Sch name = SW4
# T  U+ m/ ?, G2 f6 [% h: @
  V1 r3 ^: b$ c9 Y1 iNet "sw<5>" LOC = U8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41P, Sch name = SW59 U' A8 Y- F7 s, e; y

* K: h( q! G1 ^/ ?7 i; u! C/ `Net "sw<6>" LOC = V8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41N_VREF, Sch name = SW6
# F# V# _: B8 m, W5 ~# q$ J% G7 p+ \# R5 {2 y) [& ]
Net "sw<7>" LOC = T5 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW79 q. L- S/ _  B' S  G

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! D  x8 `; ~- V0 N4 s, d## VGA Connector. n* @% E0 [) L* X- K- z: g

5 W; V6 R5 ^9 n/ o7 INET "red<0>" LOC = U7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L43P, Sch name = RED0
/ V+ }: k' o" }2 {5 n6 }/ s6 \; N  R( M4 I% j9 S
NET "red<1>" LOC = V7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L43N, Sch name = RED1
' S7 G( d- ^0 P9 j6 Y: \# f2 H9 H. _1 _/ h: {! `) ?+ k' @6 r* s
NET "red<2>" LOC = N7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L44P, Sch name = RED2' W, R0 n. Z: u- {" J5 M
3 G5 J7 l! }; Z5 @( s( C/ g8 l
NET "green<0>" LOC = P8 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L44N, Sch name = GRN0
& p% `2 c% t& e# C; |) |; [( i) o# \  R/ S: c2 N; S6 o
NET "green<1>" LOC = T6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L45P, Sch name = GRN1
, F$ j' `$ {' i) C; n% u1 {  w# t) y6 q. `
NET "green<2>" LOC = V6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L45N, Sch name = GRN2
* R1 U. p) Z# k5 k) D0 Q7 M( j! z% t+ l0 _
NET "blue<0>" LOC = R7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L46P, Sch name = BLU1* g, F, b0 k% j5 T( i/ S. b
) _9 o+ P* m' G
NET "blue<1>" LOC = T7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L46N, Sch name = BLU2+ M- F! t( ]' `& i' x" T" ]1 Y

8 Z- V: E  M# V. d! o
4 @( r0 Z( g$ a6 w' t* ?2 x* j( w: w5 ?# O  h0 N8 A; z
NET "Hsync" LOC = N6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L47P, Sch name = HSYNC
( l$ I- u  T7 q0 r2 w( r+ s1 Q8 [$ ^* U
NET "Vsync" LOC = P7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L47N, Sch name = VSYNC
7 ?( I$ N$ K/ I; o& r' U( l7 e+ n
## Switches
! P5 X7 X$ t: @7 l
) ^* W7 o- y) N5 o0 r6 v4 lNet "sw<0>" LOC = T10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29N_GCLK2, Sch name = SW07 ~; e, U  n' w4 W' M
& e7 T9 d7 T! k$ o4 O+ U7 k
Net "sw<1>" LOC = T9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32P_GCLK29, Sch name = SW1- r5 F+ w9 m% W( ]. A. I

/ x, }% x: r1 U9 a. h4 `Net "sw<2>" LOC = V9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32N_GCLK28, Sch name = SW2
; F* R9 H) {' s+ U1 c, g7 f" }& ^1 d% j0 M  n) N: r
Net "sw<3>" LOC = M8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40P, Sch name = SW3
- ~6 a/ ?+ y% t- U7 ]( d; s, s& f& E1 {# M
Net "sw<4>" LOC = N8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40N, Sch name = SW4
$ I) X- U: P) N: c& r
) r" u9 c4 P  U, l' j( V1 dNet "sw<5>" LOC = U8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41P, Sch name = SW5% \. N. t( J& M3 }' C, N6 [
# J" R' }: m  W& P7 d* n
Net "sw<6>" LOC = V8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41N_VREF, Sch name = SW6% M5 A5 [! c' M: E4 r  D% T' [

; [' W% |( W6 i5 y. I8 d/ }Net "sw<7>" LOC = T5 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW7& F1 A) {" r1 l) E' @5 C) [
0 b6 W7 Z4 K6 A  J

: g9 C. W2 {/ `0 ?& a
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2 ?: c/ I2 z9 X& r$ H8 T5 N$ x' p1 E6 M6 i* ^5 ~

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: w" ^+ w/ Q) c' S' a以上是程序的全部内容( f5 q8 a- J* ]8 k: H2 q7 n( ]
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编译后没有错误  经检验实际结果与预期结果一致
这是源程序所有文件

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relchhiclty · 发表于 2019-4-11 15:49

最近正在找这方面的资料谢谢楼主分享

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在屏幕上显示大写字母DMH的VGA控制器

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