NVMe与AHCI对比-Overview

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NVMe与AHCI对比-Overview

7 `+ R9 v3 U* `6 O# Q2 VThe differences between an inteRFace designed as an adaptive, translational layer(AHCI) and an interface designed as a simple device adaptive layer (NVMe) drivefundamental architectural and design features that are inherently encompassed in therespective interface specifications. These differences are in addition to various featuresthat are included in a specification designed to expose characteristics and attributes ofthe underlying attached device technology.

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AHCI " \# Y+ e# e% s2 M. F) `Inherent in the problem of designing AHCI, in fact many interfaces, is that it serves asthe logical element that tie two physical buses together, the system interconnect,PCI/PCIe, and the storage subsystem interconnect, SATA. " H) ?; }$ k( E* M, E 7 G9 J; G) x% ?% w- |& x, ? Adapters built on such interfaces typically provide logical translation services betweenthe two sides of the adapter. The electrical signaling and the physical transports andassociated protocols on either side of the adapter are different, PCI/PCIe on the hostside and SATA on the storage device side. The resulting logical transport and protocolimplemented by the adaptor and used to bridge between the two physical interconnectsis then shaped by the underlying physical and link layer elements of the buses which itconnects. At the time AHCI was conceived and designed the only devices connected via SATAwere IO devices such as hard drives, optical drives, and other IO peripheral devices thatwere slow as compared to the processor-memory complex of the platform. Given thisperformance disparity an aggregation point in the system topology was needed, servingas a protocol/transport translator and as an elasticity buffer and alleviating theprocessor from managing this disparity. An HBA using AHCI as the host side interfaceand SATA as the device side interface serves this purpose quite well. Thisaggregation/translation point serves to smooth the bandwidth and latency disparitybetween the SATA storage interconnect and the system interconnect, in this case PCIor PCIe. - L1 I$ ]' Q, g. S/ r3 Z) [2 F7 k In providing such functionality latency is introduced into device access. For the originallyintended environment of AHCI this is not an issue as the additional latency of theaggregation point, the HBA, is a miniscule component of the overall device access pathlatency. ; y, P: z( Q0 B( D$ c; i/ ^AHCI serves its intended architecture and design goals well. The host is able to keepattached SATA storage devices busy while minimizing the effort needed to manage thedevices and take full advantage of additional features that they may offer. 6 ^% v+ v# y5 _! ~

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Allevi 发表于 2019-4-9 13:25

NVMe ( I2 m& n( [/ vThe deployment of SSDs, with performance capabilities orders of magnitude greaterthan previous storage devices, especially the low latency characteristics of the devices,drove the transition from physical attachments based on traditional storage busses tophysical interconnects more closely tied to the processor-memory complex, namely thePCIe bus. 3 v9 i! h3 H9 G% o 8 x8 D: J7 U- f3 T! s! HWith a storage device moving from a legacy storage interconnect to the low latencysystem interconnect the need for a new storage device interface that could span boththe storage domain and function equally well within the system interconnect domain andunlock the full potential of these new devices was required. NVMe is that new interface. The interface was also designed to be highly parallel and highly scalable. Thescalability, parallelism and inherent efficiency of NVMe allow the interface to scale upand down in performance without losing any of the benefits. These features allow theinterface to be highly adaptable to a wide variety of system configurations and designsfrom laptops to very high end, highly parallel servers. ; L" O, E6 e, A$ k Another important feature of the NVMe interface is its ability to support the partitioningof the physical storage extent into multiple logical storage extents, each of which can beaccessed independently of other logical extents. These logical storage extents arecalled Namespaces. Each NVMe Namespace may have its own pathway, or IOchannel, over which the host may access the Namespace. In fact, multiple IO channelsmay be created to a single Namespace and be used simultaneously (Note that an IO channel, i.e. a submission/completion queue pair is not limited to addressing one andonly one Namespace; see the NVMe specification for details.). . h/ |% z- o* j4 _$ { 1 j8 S* l1 e) l9 ^5 y 4 E/ W% ^% g) v! v1 x7 ^The ability to partition a physical storage extent into multiple logical storage extents andthen to create multiple IO channels to each extent is a feature of NVMe that wasarchitected and designed to allow the system in which it is used to exploit theparallelism available in upper layers of today’s platforms and extend that parallelism allthe way down into the storage device itself. & _$ f, h: n; M/ B ) u$ |! A% s1 `3 N) z  \; P5 N- g% wMultiple IO channels that can be dedicated to cores, processes or threads eliminate theneed for locks, or other semaphore based locking mechanisms around an IO channel.This ensures that IO channel resource contention, a major performance killer in IOsubsystems, is not an issue.

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Allevi 发表于 2019-4-9 13:26

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Layering Aspects of Both 0 [4 m' G" N2 m. W9 q : L, y8 B' E) B2 WBoth AHCI and NVMe are interfaces that rely on PCI/PCIe to provide the underlyingphysical interfaces and transports. An AHCI HBA will plug into a PCI/PCIe bus. A PCIeSSD implementing the NVMe interface will plug into a PCIe bus. Either interface couldbe enhanced to work with devices that plug into a systems interconnect of a differenttype but this has not been done to date as PCI/PCIe is the dominant systemsinterconnect and a need for additional physical interconnect support is not there. ; E! D! _4 m( r' r ) I- N1 I9 I: G5 RThat said, AHCI is commonly implemented within the processor chipset. The processorside physical bussing is implementation dependent and may or may not be PCI/PCIe.When the AHCI controller is implemented within the processor or processor supportchipset and connected via the PCI/PCIe bus it is a referred to as a Root IntegratedEndpoint. The bus connecting the processor to the AHCI adapter within a processor orprocessor support chipset may be proprietary. Those cases are not germane to thisdiscussion and any further discussion on this topic is beyond the scope of this paper.The remainder of this paper will assume that the host side physical interconnect isPCI/PCIe.

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