FPGA学习之DS1302时钟+数码管显示

Taio · 发表于 2019-3-27 10:39

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本帖最后由 Taio 于 2019-3-27 10:43 编辑

FPGA学习之DS1302时钟+数码管显示

一、实验目的：了解DS1302的工作原理以及通过六位数码管将时分秒显示出来。
二、实验环境：FPGA开发板AX301,Quartus ii
三、实验介绍：通过启动DS1302，让RTC开始工作，同时不断读取DS1302时分秒的值，通过数码管将之显示。

DS1302工作原理，内容比较多，先附上数据手册。

四、系统框架图

五、具体模块组成，见RTL扩展图

六、源码

module exp13_demo_show
(
CLK, RSTn,
RST,
SCLK,
SIO,
Row_Scan_Sig, Column_Scan_Sig,LED
);
input CLK;
input RSTn;
output RST;
output SCLK;
output [3:0]LED;
inout SIO;
output [7:0]Row_Scan_Sig;
output [5:0]Column_Scan_Sig;
// wire [3:0]rSecond_data0;
// wire [3:0]rSecond_data1;
// wire [3:0]rMini_data0;
// wire [3:0]rMini_data1;
// wire [3:0]rHour_data0;
// wire [3:0]rHour_data1;
wire [19:0]showdata;
exp13_demo U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.showdata(showdata),
// .Second_data0(rSecond_data0),
// .Second_data1(rSecond_data1),
// .Mini_data0(rMini_data0),
// .Mini_data1(rMini_data1),
// .Hour_data0(rHour_data0),
// .Hour_data1(rHour_data1),
.LED(LED),
.RST( RST ),
.SCLK( SCLK ),
.SIO( SIO )
);
//assign showdata = rSecond_data0+rSecond_data1*10+rMini_data0*100+rMini_data1*1000+rHour_data0*10000+rHour_data1*100000;
//assign showdata = 999999;
exp07_top U2
(
.CLK( CLK ),
.RSTn( RSTn ),
.Number_Data(showdata),
.Row_Scan_Sig(Row_Scan_Sig),
.Column_Scan_Sig(Column_Scan_Sig)
);
endmodule* j c& D; D& @

module exp13_demo //将DS1302的时分秒显示在六位数码管上
(
CLK, RSTn,
showdata,
//Second_data0, Second_data1, Mini_data0,Mini_data1,Hour_data0,Hour_data1,
LED,
RST,
SCLK,
SIO
);
input CLK;
input RSTn;
output RST;
output SCLK;
inout SIO;
output [3:0]LED;
output [19:0]showdata;
// output [7:0]Row_Scan_Sig;
// output [5:0]Column_Scan_Sig;
// output [3:0]Second_data0;
// output [3:0]Second_data1;
// output [3:0]Mini_data0;
// output [3:0]Mini_data1;
// output [3:0]Hour_data0;
// output [3:0]Hour_data1;
/*******************************/
reg [3:0]i;
reg [7:0]isStart;
reg [7:0]rData;
reg [3:0]rLED;
reg [3:0]rSecond_data0;
reg [3:0]rSecond_data1;
reg [3:0]rMini_data0;
reg [3:0]rMini_data1;
reg [3:0]rHour_data0;
reg [3:0]rHour_data1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
i <= 4'd0;
isStart <= 8'd0;
rData <= 8'd0;
rLED <= 4'd0;
end
else
case( i )
0:
if( Done_Sig ) begin isStart <= 8'd0; i <= i + 1'b1; end
else begin isStart <= 8'b1000_0000; rData <= 8'h00; end
1:
if( Done_Sig ) begin isStart <= 8'd0; i <= i + 1'b1; end
else begin isStart <= 8'b0100_0000; rData <= { 4'd1, 4'd2 }; end
2:
if( Done_Sig ) begin isStart <= 8'd0; i <= i + 1'b1; end
else begin isStart <= 8'b0010_0000; rData <= { 4'd2, 4'd2 }; end
3:
if( Done_Sig ) begin isStart <= 8'd0; i <= i + 1'b1; end
else begin isStart <= 8'b0001_0000; rData <= { 4'd2, 4'd2 }; end
4:
//if( Done_Sig ) begin rLED <= Time_Read_Data[3:0];rSecond_data0<= Time_Read_Data[3:0];rSecond_data1<= Time_Read_Data[7:4]; isStart <= 8'd0; i <= 4'd4; end
if( Done_Sig ) begin rLED <= Time_Read_Data[3:0];rSecond_data0<= Time_Read_Data[3:0];rSecond_data1<= Time_Read_Data[7:4]; isStart <= 8'd0; i <= i + 1'b1; end
else begin isStart <= 8'b0000_0001; end
5:
if( Done_Sig ) begin rMini_data0<= Time_Read_Data[3:0];rMini_data1<= Time_Read_Data[7:4]; isStart <= 8'd0; i <= i + 1'b1; end
else begin isStart <= 8'b0000_0010; end
6:
if( Done_Sig ) begin rHour_data0<= Time_Read_Data[3:0];rHour_data1<= Time_Read_Data[7:4]; isStart <= 8'd0; i <= i + 1'b1; end
else begin isStart <= 8'b0000_0100; end
7:
if(i==7) i<= 4'd4;
endcase
/********************************************/
wire Done_Sig;
wire [7:0]Time_Read_Data;
ds1302_module U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.Start_Sig( isStart ),
.Done_Sig( Done_Sig ),
.Time_Write_Data( rData ),
.Time_Read_Data( Time_Read_Data ),
.RST( RST ),
.SCLK( SCLK ),
.SIO( SIO )
);
/********************************************/
assign LED = rLED;
// assign Second_data0 = rSecond_data0;
// assign Second_data1 = rSecond_data1;
// assign Mini_data0 = rMini_data0;
// assign Mini_data1 = rMini_data1;
// assign Hour_data0 = rHour_data0;
// assign Hour_data1 = rHour_data0;
assign showdata = rSecond_data0+rSecond_data1*10+rMini_data0*100+rMini_data1*1000+rHour_data0*10000+rHour_data1*100000;
// assign
/*********************************************/
endmodule
N; R8 }8 \2 F- z# S

module exp07_top
(
CLK, RSTn,
Number_Data,
Row_Scan_Sig, Column_Scan_Sig
);
input CLK;
input RSTn;
input [19:0]Number_Data;
output [7:0]Row_Scan_Sig;
output [5:0]Column_Scan_Sig;
/**************************************/
// wire [19:0]Number_Data;
wire [3:0]Hunthu_Data;
wire [3:0]Tenthu_Data;
wire [3:0]Thu_Data;
wire [3:0]Hun_Data;
wire [3:0]Ten_Data;
wire [3:0]One_Data;
number_mod_module U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.Number_Data( Number_Data ), // input - form top
.Hunthu_Data( Hunthu_Data ), // output - to U2
.Tenthu_Data( Tenthu_Data ), //output - to U2
.Thu_Data( Thu_Data ), // output - to U2
.Hun_Data( Hun_Data ), // output - to U2
//.Ten_Data( Ten_Data ), // input - from top
// .One_SMG_Data( One_SMG_Data ), // input - from top
//.Row_Scan_Sig( Row_Scan_Sig ) // output - to top
.Ten_Data( Ten_Data ), // output - to U2
.One_Data( One_Data ) // output - to u2\\U2
);
/****************************************/
wire [7:0] Hunthu_SMG_Data;
wire [7:0]Tenthu_SMG_Data;
wire [7:0]Thu_SMG_Data;
wire [7:0]Hun_SMG_Data;
wire [7:0]Ten_SMG_Data;
wire [7:0]One_SMG_Data;
// wire [7:0]Ten_SMG_Data;
//wire [7:0]One_SMG_Data;
smg_encoder_module U2
(
.CLK( CLK ),
.RSTn( RSTn ),
.Hunthu_Data( Hunthu_Data ), // input - from U1
.Tenthu_Data( Tenthu_Data ), //input - from U1
.Thu_Data( Thu_Data ), // input - from U1
.Hun_Data( Hun_Data ), // input - from U1
.Ten_Data( Ten_Data ), // input - from U1
.One_Data( One_Data ), // input - from U1
// .Ten_Data( Ten_Data ), // input - from U1
// .One_Data( One_Data ), // input - from U1
.Hunthu_SMG_Data( Hunthu_SMG_Data ), // output - to U3
.Tenthu_SMG_Data( Tenthu_SMG_Data ), // output - to U3
.Thu_SMG_Data( Thu_SMG_Data ), // output - to U3
.Hun_SMG_Data( Hun_SMG_Data ), // output - to U3
//.Ten_SMG_Data( Ten_SMG_Data ), // output - to U3
// .One_SMG_Data( One_SMG_Data ) // output - to U3
// .Row_Scan_Sig( Row_Scan_Sig ) // output - to U3
.Ten_SMG_Data( Ten_SMG_Data ), // output - to U3
.One_SMG_Data( One_SMG_Data ) // output - to U3
);
/*****************************************/
smg_scan_module U3
(
.CLK( CLK ),
.RSTn( RSTn ),
.Hunthu_SMG_Data( Hunthu_SMG_Data ), //input - from U2
.Tenthu_SMG_Data( Tenthu_SMG_Data ), // input - from U2
.Thu_SMG_Data( Thu_SMG_Data ), // input - from U2
.Hun_SMG_Data( Hun_SMG_Data ), // input - from U2
.Ten_SMG_Data( Ten_SMG_Data ), // input - from U2
.One_SMG_Data( One_SMG_Data ), // input - from U2
// .Row_Scan_Sig( Row_Scan_Sig ), // input - from U2
// .Ten_SMG_Data( Ten_SMG_Data ), // input - from U2
// .One_SMG_Data( One_SMG_Data ), // input - from U2
.Row_Scan_Sig( Row_Scan_Sig ), // output - to top
.Column_Scan_Sig( Column_Scan_Sig ) // output - to top
);
/******************************************/
endmodule
6 I+ M: |0 x- g5 i4 y

module ds1302_module
(
CLK, RSTn,
Start_Sig,
Done_Sig,
Time_Write_Data,
Time_Read_Data,
RST,
SCLK,
SIO
);
input CLK;
input RSTn;
input [7:0]Start_Sig;
output Done_Sig;
input [7:0]Time_Write_Data;
output [7:0]Time_Read_Data;
output RST;
output SCLK;
inout SIO;
/***************************/
wire [7:0]Words_Addr;
wire [7:0]Write_Data;
wire [1:0]Access_Start_Sig;
cmd_control_module U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.Start_Sig( Start_Sig ), // input - from top
.Done_Sig( Done_Sig ), // output - to top
.Time_Write_Data( Time_Write_Data ), // input - from top
.Time_Read_Data( Time_Read_Data ), // output - to top
.Access_Done_Sig( Access_Done_Sig ), // input - from U2
.Access_Start_Sig( Access_Start_Sig ), // output - to U2
.Read_Data( Read_Data ), // input - from U2
.Words_Addr( Words_Addr ), // output - to U2
.Write_Data( Write_Data ) // output - to U2
);
/*****************************/
wire [7:0]Read_Data;
wire Access_Done_Sig;
function_module U2
(
.CLK( CLK ),
.RSTn( RSTn ),
.Start_Sig( Access_Start_Sig ), // input - from U1
.Words_Addr( Words_Addr ), // input - from U1
.Write_Data( Write_Data ), // input - from U1
.Read_Data( Read_Data ), // output - to U1
.Done_Sig( Access_Done_Sig ), // output - to U1
.RST( RST ), // output - to top
.SCLK( SCLK ), // output - to top
.SIO( SIO ) // output - to top
);
/*****************************/
endmodule
" W: o z" H# l. g- Q' ]

module cmd_control_module
(
CLK, RSTn,
Start_Sig,
Done_Sig,
Time_Write_Data,
Time_Read_Data,
Access_Done_Sig,
Access_Start_Sig,
Read_Data,
Words_Addr,
Write_Data
);
input CLK;
input RSTn;
input [7:0]Start_Sig;
output Done_Sig;
input [7:0]Time_Write_Data;
output [7:0]Time_Read_Data;
input Access_Done_Sig;
output [1:0]Access_Start_Sig;
input [7:0]Read_Data;
output [7:0]Words_Addr;
output [7:0]Write_Data;
/**********************************/
reg [7:0]rAddr;
reg [7:0]rData;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rAddr <= 8'd0;
rData <= 8'd0;
end
else
case( Start_Sig[7:0] )
8'b1000_0000 : // Write unprotect
begin rAddr <= { 2'b10, 5'd7, 1'b0 }; rData <= 8'h00; end
8'b0100_0000 : // Write hour
begin rAddr <= { 2'b10, 5'd2, 1'b0 }; rData <= Time_Write_Data; end
8'b0010_0000 : // Write minit
begin rAddr <= { 2'b10, 5'd1, 1'b0 }; rData <= Time_Write_Data; end
8'b0001_0000 : // Write second
begin rAddr <= { 2'b10, 5'd0, 1'b0 }; rData <= Time_Write_Data; end
8'b0000_1000 : // Write protect
begin rAddr <= { 2'b10, 5'd7, 1'b0 }; rData <= 8'b1000_0000; end
8'b0000_0100 : // Read hour
begin rAddr <= { 2'b10, 5'd2, 1'b1 }; end
8'b0000_0010 : // Read minit
begin rAddr <= { 2'b10, 5'd1, 1'b1 }; end
8'b0000_0001 : // Read second
begin rAddr <= { 2'b10, 5'd0, 1'b1 }; end
endcase
/**********************************/
reg [1:0]i;
reg [7:0]rRead;
reg [1:0]isStart;
reg isDone;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
i <= 2'd0;
rRead <= 8'd0;
isStart <= 2'b00;
isDone <= 1'b0;
end
else if( Start_Sig[7:3] ) // Write action
case( i )
0 :
if( Access_Done_Sig ) begin isStart <= 2'b00; i <= i + 1'b1; end
else begin isStart <= 2'b10; end
1 :
begin isDone <= 1'b1; i <= i + 1'b1; end
2 :
begin isDone <= 1'b0; i <= 2'd0; end
endcase
else if( Start_Sig[2:0] ) // Read action
case( i )
0 :
if( Access_Done_Sig ) begin rRead <= Read_Data; isStart <= 2'b00; i <= i + 1'b1; end
else begin isStart <= 2'b01; end
1 :
begin isDone <= 1'b1; i <= i + 1'b1; end
2 :
begin isDone <= 1'b0; i <= 2'd0; end
endcase
/*****************************/
assign Done_Sig = isDone;
assign Time_Read_Data = rRead;
assign Access_Start_Sig = isStart;
assign Words_Addr = rAddr;
assign Write_Data = rData;
/*******************************/
endmodule
3 X/ q4 \, v: | F, R. `4 `+ I" V

module function_module
(
CLK, RSTn,
Start_Sig,
Words_Addr,
Write_Data,
Read_Data,
Done_Sig,
RST,
SCLK,
SIO
);
input CLK;
input RSTn;
input [1:0]Start_Sig;
input [7:0]Words_Addr;
input [7:0]Write_Data;
output [7:0]Read_Data;
output Done_Sig;
output RST;
output SCLK;
inout SIO;
/*****************************/
parameter T0P5US = 5'd24;//50M*(0.5e-6)-1=24
/*****************************/
reg [4:0]Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 5'd0;
else if( Count1 == T0P5US )
Count1 <= 5'd0;
else if( Start_Sig[0] == 1'b1 || Start_Sig[1] == 1'b1 )
Count1 <= Count1 + 1'b1;
else
Count1 <= 5'd0;
/*****************************/
reg [5:0]i;
reg [7:0]rData;
reg rSCLK;
reg rRST;
reg rSIO;
reg isOut;
reg isDone;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
i <= 6'd0;
rData <= 8'd0;
rSCLK <= 1'b0;
rRST <= 1'b0;
rSIO <= 1'b0;
isOut <= 1'b0;
isDone <= 1'b0;
end
else if( Start_Sig[1] )
case( i )
0 :
begin rSCLK <= 1'b0; rData <= Words_Addr; rRST <= 1'b1; isOut <= 1'b1; i <= i + 1'b1; end
1, 3, 5, 7, 9, 11, 13, 15 :
if( Count1 == T0P5US ) i <= i + 1'b1;
else begin rSIO <= rData[ (i >> 1) ]; rSCLK <= 1'b0; end //下降沿设置数据
2, 4, 6, 8, 10, 12, 14, 16 :
if( Count1 == T0P5US ) i <= i + 1'b1; //上升沿锁存数据
else begin rSCLK <= 1'b1; end
17 :
begin rData <= Write_Data; i <= i + 1'b1; end
18, 20, 22, 24, 26, 28, 30, 32 :
if( Count1 == T0P5US ) i <= i + 1'b1;
else begin rSIO <= rData[ (i >> 1) - 9 ]; rSCLK <= 1'b0; end
19, 21, 23, 25, 27, 29, 31, 33 :
if( Count1 == T0P5US ) i <= i + 1'b1;
else begin rSCLK <= 1'b1; end
34 :
begin rRST <= 1'b0; i <= i + 1'b1; end
35 :
begin isDone <= 1'b1; i <= i + 1'b1; end
36 :
begin isDone <= 1'b0; i <= 6'd0; end
endcase
else if( Start_Sig[0] )
case( i )
0 :
begin rSCLK <= 1'b0; rData <= Words_Addr; rRST <= 1'b1; isOut <= 1'b1; i <= i + 1'b1; end
1, 3, 5, 7, 9, 11, 13, 15 :
if( Count1 == T0P5US ) i <= i + 1'b1;
else begin rSIO <= rData[ (i >> 1) ]; rSCLK <= 1'b0; end
2, 4, 6, 8, 10, 12, 14, 16 :
if( Count1 == T0P5US ) i <= i + 1'b1;
else begin rSCLK <= 1'b1; end
17 :
begin isOut <= 1'b0; i <= i + 1'b1; end //IO口改为输入
18, 20, 22, 24, 26, 28, 30, 32 :
if( Count1 == T0P5US ) i <= i + 1'b1;
else begin rSCLK <= 1'b1; end
19, 21, 23, 25, 27, 29, 31, 33 :
if( Count1 == T0P5US ) begin i <= i + 1'b1; end
else begin rSCLK <= 1'b0; rData[ (i >> 1) - 9 ] <= SIO; end
34 :
begin rRST <= 1'b0; isOut <= 1'b1; i <= i + 1'b1; end
35 :
begin isDone <= 1'b1; i <= i + 1'b1; end
36 :
begin isDone <= 1'b0; i <= 6'd0; end
endcase
/********************************/
assign Read_Data = rData;
assign Done_Sig = isDone;
assign RST = rRST;
assign SCLK = rSCLK;
assign SIO = isOut ? rSIO : 1'bz;
/********************************/
endmodule
$ W( e6 R# g: Y8 Q" L8 O! O4 o

module column_scan_module
(
CLK, RSTn, Column_Scan_Sig
);
input CLK;
input RSTn;
output [5:0]Column_Scan_Sig;
// /*****************************/
//
// parameter T10MS = 19'd499_999;//50M*0.01-1=499_999
// //parameter T2MS = 17'd99_999;//50M*0.002-1=99_999 因为需要显示六位数码管，将扫描周期缩短，每个数码管扫描时间设为2ms
// /*****************************/
//
// reg [18:0]Count1; //10MS对应的计数器
//
// always @ ( posedge CLK or negedge RSTn )
// if( !RSTn )
// Count1 <= 19'd0;
// else if( Count1 == T10MS )
// Count1 <= 19'd0;
// else
// Count1 <= Count1 + 19'b1;
//
// /*******************************/
// parameter T2MS = 17'd99_999;//50M*0.002-1=99_999 因为需要显示六位数码管，将扫描周期缩短，每个数码管扫描时间设为2ms
parameter T1MS = 16'd49_999;
/*****************************/
// reg [18:0]Count1; //10MS对应的计数器
// reg [16:0]Count1; //2MS对应的计数器
reg [15:0]Count1;//1MS对应的计数器
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 16'd0;
else if( Count1 == T1MS )
Count1 <= 16'd0;
else
Count1 <= Count1 + 16'b1;
/*******************************/
reg [3:0]t;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
t <= 3'd0;
else if( t == 3'd6 )
t <= 3'd0;
//else if( Count1 == T10MS )
else if( Count1 == T1MS )
t <= t + 1'b1;
/*********************************/
reg [5:0]rColumn_Scan;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rColumn_Scan <= 6'b011111;
//else if( Count1 == T10MS )
else if( Count1 == T1MS )
case( t )
3'd0 : rColumn_Scan <= 6'b011111;
3'd1 : rColumn_Scan <= 6'b101111;
3'd2 : rColumn_Scan <= 6'b110111;
3'd3 : rColumn_Scan <= 6'b111011;
3'd4 : rColumn_Scan <= 6'b111101;
3'd5 : rColumn_Scan <= 6'b111110;//显示各位
endcase
/******************************/
assign Column_Scan_Sig = rColumn_Scan;
/******************************/
endmodule
# p7 y: i! Y2 P4 v( R% w

//module number_mod_module
//(
// CLK, RSTn,
// Number_Data,
// Hunthu_Data,Tenthu_Data,Thu_Data,Hun_Data,Ten_Data, One_Data//定义十万万千百十个位
//);
//
// input CLK;
// input RSTn;
// input [19:0]Number_Data;
// output [3:0]Hunthu_Data;
// output [3:0]Tenthu_Data;
// output [3:0]Thu_Data;
// output [3:0]Hun_Data;
// output [3:0]Ten_Data;
// output [3:0]One_Data;
//
//
// /*********************************/
// reg [31:0]rHunthu;
// reg [31:0]rTenthu;
// reg [31:0]rThu;
// reg [31:0]rHun;
// reg [31:0]rTen;
// reg [31:0]rOne;
//
// always @ ( posedge CLK or negedge RSTn )
// if( !RSTn )
// begin
// rHunthu <= 32'd0;
// rTenthu <= 32'd0;
// rThu<= 32'd0;
// // rThu<= 32'd0;
// rHun<= 32'd0;
// rTen <= 32'd0;//？高级版本中，除法器默认是32位的，经过“编译”后，编译器会自动优化到何时的位宽
// rOne <= 32'd0;
// end
// else
// begin
// rHunthu<= Number_Data/100000;
// rTenthu <= (Number_Data / 10000)%10;
// rThu<= (Number_Data/1000)% 10;
// rHun<= (Number_Data/100)% 10;
// rTen <= Number_Data/10;
// rOne <= Number_Data%10;
// end
//
// /***********************************/
// assign Hunthu_Data = rHunthu[3:0];
// assign Tenthu_Data = rTenthu[3:0];
// assign Thu_Data = rThu[3:0];
// assign Hun_Data = rHun[3:0];
// assign Ten_Data = rTen[3:0];
// assign One_Data = rOne[3:0];
//
// /***********************************/
//
//endmodule
//
//
module number_mod_module
(
CLK, RSTn,
Number_Data,
Hunthu_Data,Tenthu_Data,Thu_Data,Hun_Data,Ten_Data, One_Data//定义十万万千百十个位
);
input CLK;
input RSTn;
input [19:0]Number_Data;
output reg [3:0]Hunthu_Data;
output reg [3:0]Tenthu_Data;
output reg [3:0]Thu_Data;
output reg [3:0]Hun_Data;
output reg [3:0]Ten_Data;
output reg [3:0]One_Data;
/*********************************/
reg [3:0]rHunthu;
reg [3:0]rTenthu;
reg [3:0]rThu;
reg [3:0]rHun;
reg [3:0]rTen;
reg [3:0]rOne;
reg [19:0]input_buffer;
reg [19:0]next_input_buffer;
parameter OUTPUT=1'b0,INPUT=1'b1;
reg state;
reg next_state;
always @ (Number_Data or state or Number_Data or Hunthu_Data or Tenthu_Data or Thu_Data or Hun_Data or Ten_Data or One_Data)
begin
if(state==INPUT)
begin
next_input_buffer = Number_Data;
rHunthu= Hunthu_Data;
rTenthu = Tenthu_Data;
rThu= Thu_Data;
rHun=Hun_Data;
rTen = Ten_Data;
rOne = One_Data;
next_state=OUTPUT;
end
else
begin
next_input_buffer=input_buffer;
rHunthu= input_buffer/100000;
rTenthu = (input_buffer / 10000)%10;
rThu= (input_buffer/1000)% 10;
rHun= (input_buffer/100)% 10;
rTen = (input_buffer/10)%10; //這行應該是這樣
rOne = input_buffer%10;
// rHunthu <= 4'd8;
// rTenthu <= 4'd7;
// rThu <= 4'd6;
// rHun <= 4'd5;
// rTen <= 4'd4;
// rOne <= 4'd3;
next_state=INPUT;
end
end
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
Hunthu_Data <= 32'd0;
Tenthu_Data <= 32'd0;
Thu_Data<= 32'd0;
Hun_Data<= 32'd0;
Ten_Data <= 32'd0;
One_Data <= 32'd0;
input_buffer<=20'h0;
state<=INPUT;
end
else
begin
Hunthu_Data<=rHunthu;
Tenthu_Data<=rTenthu;
Thu_Data<=rThu;
Hun_Data<=rHun;
Ten_Data<=rTen;
One_Data <=rOne;
input_buffer<=next_input_buffer;
state<=next_state;
end
endmodule
1 e; L$ F, |. G. z* w# s1 O9 Q9 }

module row_scan_module
(
CLK, RSTn,
Hunthu_SMG_Data, Tenthu_SMG_Data,Thu_SMG_Data, Hun_SMG_Data,Ten_SMG_Data, One_SMG_Data,
Row_Scan_Sig
);
input CLK;
input RSTn;
input [7:0] Hunthu_SMG_Data;
input [7:0]Tenthu_SMG_Data;
input [7:0]Thu_SMG_Data;
input [7:0]Hun_SMG_Data;
input [7:0]Ten_SMG_Data;
input [7:0]One_SMG_Data;
output [7:0]Row_Scan_Sig;
/*******************************/
// parameter T10MS = 19'd499_999;//50M*0.01-1=499_999
//
// /*******************************/
//
// reg [18:0]Count1;
//
// always @ ( posedge CLK or negedge RSTn )
// if( !RSTn )
// Count1 <= 19'd0;
// else if( Count1 == T10MS )
// Count1 <= 19'd0;
// else
// Count1 <= Count1 + 19'b1;
//
/*******************************/
// parameter T2MS = 17'd99_999;//50M*0.002-1=99_999 因为需要显示六位数码管，将扫描周期缩短，每个数码管扫描时间设为2ms
parameter T1MS = 16'd49_999;
/*****************************/
// reg [18:0]Count1; //10MS对应的计数器
// reg [16:0]Count1; //2MS对应的计数器
reg [15:0]Count1;//1MS对应的计数器
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 16'd0;
else if( Count1 == T1MS )
Count1 <= 16'd0;
else
Count1 <= Count1 + 16'b1;
/*******************************/
reg [3:0]t;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
t <= 3'd0;
else if( t == 3'd6 )
t <= 3'd0;
// else if( Count1 == T10MS )
else if( Count1 == T1MS )
t <= t + 1'b1;
/**********************************/
reg [7:0]rData;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rData <= 8'd0;
// else if( Count1 == T10MS )
else if( Count1 == T1MS )
case( t )
3'd0 : rData <= Hunthu_SMG_Data;
3'd1 : rData <= Tenthu_SMG_Data;
3'd2 : rData <= Thu_SMG_Data;
3'd3 : rData <= Hun_SMG_Data;
3'd4 : rData <= Ten_SMG_Data;
3'd5 : rData <= One_SMG_Data;
endcase
/***********************************/
assign Row_Scan_Sig = rData;
//assign Row_Scan_Sig = 8'b1111_1111;
/***********************************/
endmodule
' e+ H% f* J. h8 X2 g) o

module smg_encoder_module
(
CLK, RSTn,
Hunthu_Data,Tenthu_Data,Thu_Data,Hun_Data,Ten_Data, One_Data,
Hunthu_SMG_Data, Tenthu_SMG_Data,Thu_SMG_Data, Hun_SMG_Data,Ten_SMG_Data, One_SMG_Data
);
input CLK;
input RSTn;
input [3:0]Hunthu_Data;
input [3:0]Tenthu_Data;
input [3:0]Thu_Data;
input [3:0]Hun_Data;
input [3:0]Ten_Data;
input [3:0]One_Data;
output [7:0]Hunthu_SMG_Data;
output [7:0]Tenthu_SMG_Data;
output [7:0]Thu_SMG_Data;
output [7:0]Hun_SMG_Data;
output [7:0]Ten_SMG_Data;
output [7:0]One_SMG_Data;
/***************************************/
parameter _0 = 8'b1100_0000, _1 = 8'b1111_1001, _2 = 8'b1010_0100,
_3 = 8'b1011_0000, _4 = 8'b1001_1001, _5 = 8'b1001_0010,
_6 = 8'b1000_0010, _7 = 8'b1111_1000, _8 = 8'b1000_0000,
_9 = 8'b1001_0000;
/***************************************/
reg [7:0]rHunthu_SMG_Data;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rHunthu_SMG_Data <= 8'b1111_1111;
end
else
case( Hunthu_Data )
4'd0 : rHunthu_SMG_Data <= _0;
4'd1 : rHunthu_SMG_Data <= _1;
4'd2 : rHunthu_SMG_Data<= _2;
4'd3 : rHunthu_SMG_Data <= _3;
4'd4 : rHunthu_SMG_Data <= _4;
4'd5 : rHunthu_SMG_Data <= _5;
4'd6 : rHunthu_SMG_Data<= _6;
4'd7 : rHunthu_SMG_Data<= _7;
4'd8 : rHunthu_SMG_Data<= _8;
4'd9 : rHunthu_SMG_Data <= _9;
endcase
/***************************************/
/***************************************/
reg [7:0]rTenthu_SMG_Data;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTenthu_SMG_Data <= 8'b1111_1111;
end
else
case( Tenthu_Data )
4'd0 : rTenthu_SMG_Data <= _0;
4'd1 : rTenthu_SMG_Data <= _1;
4'd2 : rTenthu_SMG_Data<= _2;
4'd3 : rTenthu_SMG_Data <= _3;
4'd4 : rTenthu_SMG_Data <= _4;
4'd5 : rTenthu_SMG_Data <= _5;
4'd6 : rTenthu_SMG_Data<= _6;
4'd7 : rTenthu_SMG_Data<= _7;
4'd8 : rTenthu_SMG_Data<= _8;
4'd9 : rTenthu_SMG_Data <= _9;
endcase
/***************************************/
/***************************************/
reg [7:0]rThu_SMG_Data;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rThu_SMG_Data <= 8'b1111_1111;
end
else
case( Thu_Data )
4'd0 : rThu_SMG_Data <= _0;
4'd1 : rThu_SMG_Data <= _1;
4'd2 : rThu_SMG_Data<= _2;
4'd3 : rThu_SMG_Data <= _3;
4'd4 : rThu_SMG_Data <= _4;
4'd5 : rThu_SMG_Data <= _5;
4'd6 : rThu_SMG_Data<= _6;
4'd7 : rThu_SMG_Data<= _7;
4'd8 : rThu_SMG_Data<= _8;
4'd9 : rThu_SMG_Data <= _9;
endcase
/***************************************/
/***************************************/
reg [7:0]rHun_SMG_Data;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rHun_SMG_Data <= 8'b1111_1111;
end
else
case( Hun_Data )
4'd0 : rHun_SMG_Data <= _0;
4'd1 : rHun_SMG_Data <= _1;
4'd2 : rHun_SMG_Data<= _2;
4'd3 : rHun_SMG_Data <= _3;
4'd4 : rHun_SMG_Data <= _4;
4'd5 : rHun_SMG_Data <= _5;
4'd6 : rHun_SMG_Data<= _6;
4'd7 : rHun_SMG_Data<= _7;
4'd8 : rHun_SMG_Data<= _8;
4'd9 : rHun_SMG_Data <= _9;
endcase
/***************************************/
reg [7:0]rTen_SMG_Data;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTen_SMG_Data <= 8'b1111_1111;
end
else
case( Ten_Data )
4'd0 : rTen_SMG_Data <= _0;
4'd1 : rTen_SMG_Data <= _1;
4'd2 : rTen_SMG_Data <= _2;
4'd3 : rTen_SMG_Data <= _3;
4'd4 : rTen_SMG_Data <= _4;
4'd5 : rTen_SMG_Data <= _5;
4'd6 : rTen_SMG_Data <= _6;
4'd7 : rTen_SMG_Data <= _7;
4'd8 : rTen_SMG_Data <= _8;
4'd9 : rTen_SMG_Data <= _9;
endcase
/***************************************/
reg [7:0]rOne_SMG_Data;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rOne_SMG_Data <= 8'b1111_1111;
end
else
case( One_Data )
4'd0 : rOne_SMG_Data <= _0;
4'd1 : rOne_SMG_Data <= _1;
4'd2 : rOne_SMG_Data <= _2;
4'd3 : rOne_SMG_Data <= _3;
4'd4 : rOne_SMG_Data <= _4;
4'd5 : rOne_SMG_Data <= _5;
4'd6 : rOne_SMG_Data <= _6;
4'd7 : rOne_SMG_Data <= _7;
4'd8 : rOne_SMG_Data <= _8;
4'd9 : rOne_SMG_Data <= _9;
endcase
/***************************************/
assign Hunthu_SMG_Data = rHunthu_SMG_Data;
assign Thu_SMG_Data = rThu_SMG_Data;
assign Tenthu_SMG_Data = rTenthu_SMG_Data;
assign Hun_SMG_Data = rHun_SMG_Data;
assign Ten_SMG_Data = rTen_SMG_Data;
assign One_SMG_Data = rOne_SMG_Data;
/***************************************/
endmodule
7 N8 h9 p0 U! E g7 S0 Q

module smg_scan_module
(
CLK, RSTn,
Hunthu_SMG_Data, Tenthu_SMG_Data,Thu_SMG_Data, Hun_SMG_Data,Ten_SMG_Data, One_SMG_Data,
Row_Scan_Sig, Column_Scan_Sig
);
input CLK;
input RSTn;
input [7:0] Hunthu_SMG_Data;
input [7:0]Tenthu_SMG_Data;
input [7:0]Thu_SMG_Data;
input [7:0]Hun_SMG_Data;
input [7:0]Ten_SMG_Data;
input [7:0]One_SMG_Data;
output [7:0]Row_Scan_Sig;
output [5:0]Column_Scan_Sig;
/*****************************/
row_scan_module U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.Hunthu_SMG_Data( Hunthu_SMG_Data ), // input - from top
.Tenthu_SMG_Data( Tenthu_SMG_Data ), // input - from top
.Thu_SMG_Data( Thu_SMG_Data ), // input - from top
.Hun_SMG_Data( Hun_SMG_Data ), // input - from top
.Ten_SMG_Data( Ten_SMG_Data ), // input - from top
.One_SMG_Data( One_SMG_Data ), // input - from top
.Row_Scan_Sig( Row_Scan_Sig ) // output - to top
);
column_scan_module U2
(
.CLK( CLK ),
.RSTn( RSTn ),
.Column_Scan_Sig( Column_Scan_Sig ) // output - to top
);
/********************************/
endmodule
4 }2 w0 y4 R. y6 C/ l

七、实验结果

gaoxings · 发表于 2019-3-27 15:34

最近正在找这方面的资料谢谢楼主分享

wu68aq · 发表于 2019-8-16 17:36

谢谢楼主分享。

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