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VHDL流水灯设计 ' r# l& U n+ n2 T. o1 O
" t- T% D- Q0 G! Q' i Y, {2 f3 x! ^library ieee;
3 }6 Y* S# p; C% |- buse ieee.std_logic_1164.all;
2 u# k- [4 L$ d) C: U8 Huse ieee.std_logic_unsigned.all;
1 ?- s7 ^5 F5 Kuse ieee.std_logic_arith.all;" g' H) M3 y# G6 w3 [+ f
entity liushui is- D! B, A/ Q2 l/ s8 d P
port(
3 D9 ~: S' e z; }$ y: M# \clk:IN std_logic;
4 O. y- k6 }( C. _4 Mclr:IN std_logic;# N1 ~) T) {9 ~* z( s8 l5 B
ena:IN std_logic;
) {" d4 m; L) O7 \y ut std_logic_vector (7 downto 0) );( h4 |2 j2 E7 A" v, L$ X
end;( M! T) ~- n9 a( s, D' V
architecture behave of liushui is
5 d' w9 |, l1 E& U1 M% E' L* V/ L4 W! bbegin
' Q) f0 x. P- l$ U! R# w2 J, Isignal y_out:std_logic_vector(7 downto 0); process(clk,clr,ena) if clr = '0' then y_out<= "00000001"; elsif clk'event and clk = '1' then if ena = '1' then y_out <= y_out<<1; end if; end if;end process; y <= y_out; end behave; |
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发表于 2019-3-11 11:30
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支持！
反对！