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VHDL流水灯设计
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& M' ]+ v- @, ~! l- Ilibrary ieee;
/ P& W( J$ C4 o% y! E, zuse ieee.std_logic_1164.all;
1 @9 B2 i6 z+ ]# A& m+ n( uuse ieee.std_logic_unsigned.all;; C$ B6 r1 U; o4 q+ m$ _
use ieee.std_logic_arith.all;
. X# p2 C, o! t( H1 L5 Uentity liushui is0 C* g0 s/ k1 m( e: w
port(
% x% M# |5 v9 f' Zclk:IN std_logic;
2 w8 W+ }3 m& Z9 o- A/ s4 cclr:IN std_logic;" l0 n2 h4 _: Y
ena:IN std_logic;6 ~* @3 b9 ?+ l- F" Z6 }! _
y ut std_logic_vector (7 downto 0) );
% l0 b1 _, {! v6 M! Gend;7 G U3 @4 V7 O, E
architecture behave of liushui is
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signal y_out:std_logic_vector(7 downto 0); process(clk,clr,ena) if clr = '0' then y_out<= "00000001"; elsif clk'event and clk = '1' then if ena = '1' then y_out <= y_out<<1; end if; end if;end process; y <= y_out; end behave; |
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