verilog 基础语法-端口

Taio

verilog 基础语法-端口

1 模块结构 ( A- d& ^3 v( h  G/ @3 k# n&nbsp; &nbsp; 端口： module 模块名(端口1, 端口2, 端口3) 5 [  V: \, J. ^$ l! t&nbsp; &nbsp; 内容： ! q+ Y( J& `5 |; E2 e  E1 W* b&nbsp; &nbsp; &nbsp; &nbsp; I/O说明： &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; input 端口名; 0 m$ k# A3 h+ B- \( F&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; output 端口名; $ U- ~% G2 i! _% t: I3 E&nbsp; &nbsp; &nbsp; &nbsp; 内部信号： $ U3 K8 j: h; M4 u. W( c$ n&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; reg [width-1:0]&nbsp; r变量1,r变量2; 1 v4 K) ^. h7 W, a5 x2 ]0 [. L7 s&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; wire [width-1:0] w变量1,w变量2; &nbsp; &nbsp; &nbsp; &nbsp; 功能定义： &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; a. assign 连线 " ^) h9 a+ c8 }6 d&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; assign a = b&c; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; b. 实例化其他元件 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; and and_inst(q, a, b); 4 J7 J$ E, |- Q& u, @* F6 ~) f&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; c. always模块 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; always @(posedge clk or posedge clr) &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; begin &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; if(clr)&nbsp; $ I2 d8 {# e  x3 V5 A&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; q <= 0; ) @& u, J: ?- X, C: c9 M&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; else &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; if(en) 2 a; @+ {5 A8 Y6 z) u1 b9 h( m0 I) V8 u&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; q <= d; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; end 4 \- x: K# X' V& |, Q ---------------------

) X- V( y$ ^% l" B/ T

fanichicl

谢谢楼主的分享