verilog 基础语法-端口

Taio

verilog 基础语法-端口

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1 模块结构 &nbsp; &nbsp; 端口： module 模块名(端口1, 端口2, 端口3) / b+ j/ f: b* o1 l* }- q: F7 i5 `/ I&nbsp; &nbsp; 内容： 6 O+ ~' Q+ u( f( N3 e) Z3 B&nbsp; &nbsp; &nbsp; &nbsp; I/O说明： 0 |  W- x% D& u; x" x# w, K/ v' h, r&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; input 端口名; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; output 端口名; &nbsp; &nbsp; &nbsp; &nbsp; 内部信号： &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; reg [width-1:0]&nbsp; r变量1,r变量2; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; wire [width-1:0] w变量1,w变量2; - f) i: S( y  O&nbsp; &nbsp; &nbsp; &nbsp; 功能定义： &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; a. assign 连线 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; assign a = b&c; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; b. 实例化其他元件 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; and and_inst(q, a, b); &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; c. always模块 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; always @(posedge clk or posedge clr) &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; begin " D1 h! W2 `) i1 J! A! }  X2 T&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; if(clr)&nbsp;   u# V5 ~% k4 M&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; q <= 0; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; else &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; if(en) &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; q <= d; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; end # `5 H. R0 `; w% k$ V% p8 Z " @2 k9 l9 z. |4 Y( v0 j6 }- G---------------------

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谢谢楼主的分享