verilog 基础语法-数据类型 常量 变量

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verilog 基础语法-数据类型 常量 变量

8 G) u- ?" C! K) J&nbsp; &nbsp; 常量： &nbsp; &nbsp; &nbsp; &nbsp; 整数：<位宽 num'><进制 b|o|d|h><数字>，例如 4'b1010 # I1 M; J: ?- |% q' I&nbsp; &nbsp; &nbsp; &nbsp; x值(不定值)和z值(高阻值，也可用?代替) &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; x和z可以标识某一位或者某一个数字 + L& h- T1 c, u1 O8 W&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 4'b10x0,4'bx,4'b101z,4'bz,4'b? 7 O/ a  @+ h8 i; E9 w&nbsp; &nbsp; &nbsp; &nbsp; 负数：整数最前面加- 8 Z1 y* t) @+ w+ G  ^! W&nbsp; &nbsp; &nbsp; &nbsp; 下划线：分割数字部分，更加易读(8'b1000_1000) , Z! u6 I# g$ s+ k3 Y9 T: J( R&nbsp; &nbsp; 参数：parameter &nbsp; &nbsp; &nbsp; &nbsp; parameter 参数名=表达式; $ B& H% V8 z& l* O( G" E&nbsp; &nbsp; &nbsp; &nbsp; 表达式只能是数字或者定义过的参数 &nbsp; &nbsp; 变量： &nbsp; &nbsp; &nbsp; &nbsp; wire型：wire [n-1:0] 数据名; 0 ?- w7 U2 n5 ~  ?$ n$ r0 O" _/ y&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; wire表示信号，常用来表示assign关键字指定的组合逻辑信号 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; wire型信号可以用作输入，输出 &nbsp; &nbsp; &nbsp; &nbsp; reg型：reg [n-1:0] 数据名; ! I# S( }# U/ m% T8 }, \* R&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 对存储单元的抽象 # D( w: [0 k* w& c&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 常用来表示always模块内的指定信号，常代表触发器 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; always块内被赋值的每一个信号都必须定义为reg型 &nbsp; &nbsp; &nbsp; &nbsp; memory型：reg [n-1:0] 存储器名[m-1:0]; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; reg [n-1:0]表示基本存储单元的大小 . ^" W3 e- l, B' o+ @+ a: S$ I+ N&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 存储器名[m-1:0]表示基本存储单元的个数，存储空间的容量 ; @8 A6 }+ X* ?&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 对存储器进行地址索引的表达式必须是常数表达式 8 N% ~5 K* |9 A& m, @( i; t' v/ c) n&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 一个n位寄存器可以在一条赋值语句里进行赋值，而一个完整的存储器不行 8 P0 K9 p' Q( l" k0 j6 f, N&nbsp; &nbsp; 运算符及表达式： # C$ m) m- }+ B  P' R$ }&nbsp; &nbsp; &nbsp; &nbsp; 基本运算符：+ - * / % &nbsp; &nbsp; &nbsp; &nbsp; 位运算符：~ & | ^ ^~ &nbsp; &nbsp; &nbsp; &nbsp; 逻辑运算符：&& || ! &nbsp; &nbsp; &nbsp; &nbsp; 关系运算符：< > <= >= &nbsp; &nbsp; &nbsp; &nbsp; 等式运算符：== != (不管x、z，结果可能是不定值) % x4 A3 x) Q+ i9 a( H* p  E: N' F&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; === !==(对参数的x、z都进行比较) ( O! o; ~) i/ _# {6 B&nbsp; &nbsp; &nbsp; &nbsp; 移位运算符：<< >> + _& I* c: e  J&nbsp; &nbsp; &nbsp; &nbsp; 位拼接运算符：{ }，将几个信号拼接起来，例如{a,b[3:0],w,3'b100} 0 }% R3 B  O, f+ y. e; A. x- q&nbsp; &nbsp; &nbsp; &nbsp; 缩减运算符：C =&B;C =|B;C =^B; 6 {: E) x* A- `$ B6 i. _/ L* V&nbsp; &nbsp; &nbsp; &nbsp; 优先级别：和c语言差不多，加括号 &nbsp; &nbsp; 赋值语句： 6 h2 V7 r9 m2 Q9 M6 n6 {- E/ l&nbsp; &nbsp; &nbsp; &nbsp; 1)非阻塞赋值方式(b <= a) ! p8 I% _. Q( X; Z0 W  K&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; a.块结束才完成赋值 * e7 L/ L2 ^) [&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; b.b的值不是立刻就改变的 2 j/ p8 J" e, i6 c7 V( S0 n&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; c.在可综合的模块中常用 3 n; E) W6 _  s/ s7 ]&nbsp; &nbsp; &nbsp; &nbsp; 2)阻塞赋值方式(b = a) / p& d+ G" T. ]&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; a.赋值语句执行完成后，块才结束 5 x6 e, j& ?# [8 ^9 s$ B&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; b.b的值在赋值语句执行后立刻改变 * r4 M  ~+ `7 \- r7 G' O: A! r&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; c.可能会产生意想不到的结果 &nbsp; &nbsp; &nbsp; &nbsp; 简单理解： 3 z* w: h8 O! s$ @& b2 O3 x&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 非阻塞赋值用了多个触发器，每次时钟到达，所有触发器都触发一次 . _* C6 Y, K. |&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 阻塞赋值连到同一个触发器上，时钟到达，导致所有寄存器被赋值 ---------------------

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