问点Quartus II 的问题

sutee7907

为什么我用Verilog HDL语言在 Quartus II 里加上'timescale 10ns/1ns 会提示出错 Error: Verilog HDL syntax error at mult_tp.v(3) near text '
9 C$ h3 C" S8 V0 w6 CError: Verilog HDL syntax error at mult_tp.v(3) near text "'";  expecting "module", or "macromodule", or "primitive", or "(*", or "config", or "include", or "library"
Error: Ignored module "mult_tp" at mult_tp.v(4) because of previous errors
Error: Ignored module "mult8" at mult_tp.v(21) because of previous errors
源程序是这样的，
, N  l3 F  M+ Z) {: M'timescale 10ns/1ns
module mult_tp;
% M+ T) C5 N) s7 t3 Greg[7:0] a,b;
8 F4 {# u) }* V. @wire[15:0] out;
. v; z3 c: G( ~& Q( o, c, K: O# x% ?integer i,j;
mult8 m1(out,a,b);
; J$ S4 l7 ~3 i+ pinitial begin
; h6 d) P# m+ }* ]        a=0;b=0;
! X$ o' C& U1 A6 x# ~        for(i=1;i<255;i=i+1) #10 a=i;
' o$ I" |* n7 ]end
initial begin
        for(j=i;j<255;j=j+1) #10 b=j;
% i8 I- v3 Z. y: ~% E                end
: k" m6 u4 d) Jinitial begin
2 l& {4 }0 A4 |; b& g7 V( V5 R        $monitor($time,,,"%d*%d=%d",a,b,out);
& m/ x. _+ _  Y. u, I* }5 ]        #2560 $finish;
, g: j$ E1 [9 i% T* L        end
7 W! g) T9 w3 C1 Y# x3 |endmodule
; |3 N0 n( O0 j$ {1 Y$ h) Pmodule mult8(out,a,b);
parameter size=8;
input[size:1] a,b;
output[2*size:1] out;
assign out=a*b;
4 U* J, v1 `3 \, _! Jendmodule
请问还需要设置什么吗？时序和功能仿真都有错。

maochencw

是`timescale，注意那个点，不是'是而是`

sghgfmu

回复 1# sutee7907

5 z  j0 J' l, o! N
" f# Y' M7 I" u7 O$ C   就是二楼所说的问题呀，那个·是跟~一个键的那个点