问点Quartus II 的问题

sutee7907

为什么我用Verilog HDL语言在 Quartus II 里加上'timescale 10ns/1ns 会提示出错 Error: Verilog HDL syntax error at mult_tp.v(3) near text '
5 A2 K2 x" N9 Z* ?2 s. PError: Verilog HDL syntax error at mult_tp.v(3) near text "'";  expecting "module", or "macromodule", or "primitive", or "(*", or "config", or "include", or "library"
Error: Ignored module "mult_tp" at mult_tp.v(4) because of previous errors
Error: Ignored module "mult8" at mult_tp.v(21) because of previous errors
源程序是这样的，
  M7 }. g% p: [) t# s'timescale 10ns/1ns
module mult_tp;
reg[7:0] a,b;
& t6 z/ F. q$ C" h: r2 X' fwire[15:0] out;
- |. \2 w) k# o0 `' @integer i,j;
& C  b5 l0 r: gmult8 m1(out,a,b);
initial begin
* d* r3 d/ `& V2 Y1 y; s9 z        a=0;b=0;
        for(i=1;i<255;i=i+1) #10 a=i;
end
initial begin
        for(j=i;j<255;j=j+1) #10 b=j;
                end
5 S9 y7 [& c  ~* D6 Xinitial begin
' d& \9 G: V! Z( C- i9 `8 q        $monitor($time,,,"%d*%d=%d",a,b,out);
        #2560 $finish;
        end
- F& V+ c5 D. R4 j% Vendmodule
- m" a4 F, s1 H- s: }module mult8(out,a,b);
! y8 D- w1 x' Hparameter size=8;
, X5 Z; U) A0 u$ v0 Z, K0 T. H5 N' jinput[size:1] a,b;
7 f- ^9 q( T. x: X) c( ooutput[2*size:1] out;
! n$ d: y) V) N. s6 _; rassign out=a*b;
6 I& |2 a, }* O4 V; rendmodule
请问还需要设置什么吗？时序和功能仿真都有错。

maochencw

是`timescale，注意那个点，不是'是而是`

sghgfmu

回复 1# sutee7907
5 B* w# P1 C7 c% A

   就是二楼所说的问题呀，那个·是跟~一个键的那个点