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为什么我用Verilog HDL语言在 Quartus II 里加上'timescale 10ns/1ns 会提示出错 Error: Verilog HDL syntax error at mult_tp.v(3) near text '
5 M% E+ J3 D; F; C3 eError: Verilog HDL syntax error at mult_tp.v(3) near text "'"; expecting "module", or "macromodule", or "primitive", or "(*", or "config", or "include", or "library"
3 D9 C. d2 K8 R1 ^6 f6 kError: Ignored module "mult_tp" at mult_tp.v(4) because of previous errors
k: Z' e( e8 _Error: Ignored module "mult8" at mult_tp.v(21) because of previous errors
8 ]/ ?: R a3 |) _源程序是这样的,3 _4 L0 l" b* n
'timescale 10ns/1ns
+ m) N) E( v% z& y6 Z3 A* Z0 Q- E. ?0 lmodule mult_tp;5 ^3 i7 Y! {, n1 v ~: O
reg[7:0] a,b;
9 Q: p' C' W' L: ?: L8 c. vwire[15:0] out;
! O. ^. f m) L4 Pinteger i,j;9 n6 I; G8 Z- l" P! K
mult8 m1(out,a,b);
& \% F+ p* a- V, o: u% J8 p' Kinitial begin
2 M; P+ j, k1 ^0 I& l a=0;b=0;
0 k3 j4 S3 ]$ `; d3 U% ?; Z7 s for(i=1;i<255;i=i+1) #10 a=i;+ `2 E; U5 u' m$ K
end/ A) D. T3 D5 z+ \: d
initial begin4 s D5 \5 E$ ~5 M
for(j=i;j<255;j=j+1) #10 b=j;% u! _+ u& I- d
end1 |1 r" u# Q! x% Z! _" k) E p& x
initial begin
! X* Z1 t. _' g7 a $monitor($time,,,"%d*%d=%d",a,b,out);
0 `5 O1 D' g& c! E9 x& A# C4 \& `) @ #2560 $finish;
! D8 B0 ]& A9 _* I+ C end
1 e. E+ ^4 g7 F' qendmodule
. ], s% x8 \( l; e+ t7 \6 nmodule mult8(out,a,b);
$ A! `4 v+ k9 Rparameter size=8;1 N) Q2 b' S: Y0 K- R* V
input[size:1] a,b;) p& X0 x" J. V
output[2*size:1] out;4 R% M: l }% @5 b( L$ S5 |& F' O6 e
assign out=a*b;
" i, }. Q+ y( Qendmodule1 w8 S, D& g# V% J2 C
请问还需要设置什么吗?时序和功能仿真都有错。 |
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