问点Quartus II 的问题

sutee7907

为什么我用Verilog HDL语言在 Quartus II 里加上'timescale 10ns/1ns 会提示出错 Error: Verilog HDL syntax error at mult_tp.v(3) near text '
5 M% E+ J3 D; F; C3 eError: Verilog HDL syntax error at mult_tp.v(3) near text "'";  expecting "module", or "macromodule", or "primitive", or "(*", or "config", or "include", or "library"
3 D9 C. d2 K8 R1 ^6 f6 kError: Ignored module "mult_tp" at mult_tp.v(4) because of previous errors
  k: Z' e( e8 _Error: Ignored module "mult8" at mult_tp.v(21) because of previous errors
8 ]/ ?: R  a3 |) _源程序是这样的，
'timescale 10ns/1ns
+ m) N) E( v% z& y6 Z3 A* Z0 Q- E. ?0 lmodule mult_tp;
reg[7:0] a,b;
9 Q: p' C' W' L: ?: L8 c. vwire[15:0] out;
! O. ^. f  m) L4 Pinteger i,j;
mult8 m1(out,a,b);
& \% F+ p* a- V, o: u% J8 p' Kinitial begin
2 M; P+ j, k1 ^0 I& l        a=0;b=0;
0 k3 j4 S3 ]$ `; d3 U% ?; Z7 s        for(i=1;i<255;i=i+1) #10 a=i;
end
initial begin
        for(j=i;j<255;j=j+1) #10 b=j;
                end
initial begin
! X* Z1 t. _' g7 a        $monitor($time,,,"%d*%d=%d",a,b,out);
0 `5 O1 D' g& c! E9 x& A# C4 \& `) @        #2560 $finish;
! D8 B0 ]& A9 _* I+ C        end
1 e. E+ ^4 g7 F' qendmodule
. ], s% x8 \( l; e+ t7 \6 nmodule mult8(out,a,b);
$ A! `4 v+ k9 Rparameter size=8;
input[size:1] a,b;
output[2*size:1] out;
assign out=a*b;
" i, }. Q+ y( Qendmodule
请问还需要设置什么吗？时序和功能仿真都有错。

maochencw

是`timescale，注意那个点，不是'是而是`

sghgfmu

回复 1# sutee7907

. ^# U% o, ]$ F+ f* [' x
  B$ u8 r" J% ~7 ], W% G   就是二楼所说的问题呀，那个·是跟~一个键的那个点