hsipce 不收敛的解决

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解决spice在tran时的internal timestep too small问题的方法
Transient Analysis: 也就是一般的暂态分析.一般错误的
6 l8 t; p5 u3 N( Z; r, qMessage 为:-"Internal timestep too small."
$ z+ k. B6 ~2 ~# z* m# ^另外,也会常看到 "Singular Matrix", or "Gmin/Source Stepping
! Q* P1 o$ I* t& A' F- F2 q% q. IFailed" 这样的 Error Message.解决这个问题没有一定的方法,根
据我们的经验,我们大致把它们说明如後:
7 `6 N4 e& X& ~! b# J: B2 T4 F1. 电路错误:指的是由使用者本身电路,有不正常的接线或短路等,例如将电源
接到输出端,而造成SPICE在运算的时候无法收敛.根据Ref[38] 的建议,请
你确认以下之状况:
' H8 h1 y( m5 w( j2 d8 hMake sure that all of the circuit connections are valid. Check for
7 W& t9 r2 m4 sincorrect node numbering or dangling nodes. Also, verify component
" C$ G; F; U5 g0 U- p5 _" f: [polarity.
Make sure you didn't use the letter O instead of a zero (0).
Check for syntax mistakes. Make sure that you used the correct SPICE
units (i.e. MEG instead of M(milli) for 1E6).
Make sure that there's a DC path from every node to ground.
1 }" k, ?3 Z: o$ l0 f1 h$ lMake sure that there are at least two connections at every node.
* C, o' Q! v& d7 P. M* x" s' QMake sure that there are no loops of inductors or voltage sources.
Make sure that there are no series capacitors or current sources.
* h1 M4 Y8 }$ W* U% }$ E* z2 f: HPlace the ground (node 0) somewhere in the circuit. Be careful when
you use floating grounds; you may need to connect a large resistor from
* n5 ]$ U1 O/ ]% Z; u- B4 M6 xthe floating node to ground.
Make sure that voltage/current generators use realistic values, and
verify that the syntax is correct.
9-46 VLSI 设计概论 / 实习
Make sure that dependent source gains are correct, and that B element
expressions are reasonable. If you are using division in an expression,
* n! Z- C' u% everify that division by zero cannot occur.
' R6 q! a! ]  b$ s8 [Make sure that there are no unrealistic model parameters; especially if
you have manually entered the model into the netlist.
$ n$ I2 [$ i. G. N0 hMake sure that all resistors have a value. In SPICE 3, resistors without
; A4 [8 W5 `  {6 z# \# tvalues are given a default value of 1k Ohm.
4 I. D. S8 R6 ONegative capacitor and inductor values are allowed in SPICE 3. They
% q# w0 k8 I* f" awill not be flagged as an error, but can cause timestep problems,
depending on the topology of the circuit.
2. 检查Feedback : 所指的是在序向逻辑电路中所产生的,你可以检查一下你的
# c( a2 G  y. w8 W电路的FeedBack Path的Delay,在不影响电路功能的情形下,是否可以调快一
) \* q$ V- q* d3 T. x点或慢一点.
6 b; X* P3 Q3 v+ d

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谢谢分享

lxuande

好好学习，天天向上。