hsipce 不收敛的解决

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解决spice在tran时的internal timestep too small问题的方法
Transient Analysis: 也就是一般的暂态分析.一般错误的
Message 为:-"Internal timestep too small."
另外,也会常看到 "Singular Matrix", or "Gmin/Source Stepping
# [; f5 a* z5 c, A& K# h/ X+ RFailed" 这样的 Error Message.解决这个问题没有一定的方法,根
据我们的经验,我们大致把它们说明如後:
* }) A6 L: x- ]! e1. 电路错误:指的是由使用者本身电路,有不正常的接线或短路等,例如将电源
接到输出端,而造成SPICE在运算的时候无法收敛.根据Ref[38] 的建议,请
你确认以下之状况:
3 e5 ?5 {2 z- A2 eMake sure that all of the circuit connections are valid. Check for
incorrect node numbering or dangling nodes. Also, verify component
7 \4 m2 H8 w& A$ q/ z3 x6 b2 V- _: apolarity.
Make sure you didn't use the letter O instead of a zero (0).
- A+ n' [. k6 j) h) ZCheck for syntax mistakes. Make sure that you used the correct SPICE
% K+ m2 N" o/ Munits (i.e. MEG instead of M(milli) for 1E6).
8 H" C7 S! @: K  r: GMake sure that there's a DC path from every node to ground.
Make sure that there are at least two connections at every node.
# j/ o/ v$ |9 PMake sure that there are no loops of inductors or voltage sources.
8 D4 L* a' w* O* k3 CMake sure that there are no series capacitors or current sources.
Place the ground (node 0) somewhere in the circuit. Be careful when
, m. k  D7 |3 _. n4 Xyou use floating grounds; you may need to connect a large resistor from
& \3 r" ~  y" a5 s, [1 f  t2 Hthe floating node to ground.
3 V/ a9 |# ^5 n# }9 zMake sure that voltage/current generators use realistic values, and
verify that the syntax is correct.
$ ]9 \# c  R6 d9 E9-46 VLSI 设计概论 / 实习
6 S- r5 K0 h1 V$ L, Q( P% VMake sure that dependent source gains are correct, and that B element
expressions are reasonable. If you are using division in an expression,
7 [! c+ |+ `' ^+ ?( i7 M& Zverify that division by zero cannot occur.
Make sure that there are no unrealistic model parameters; especially if
you have manually entered the model into the netlist.
Make sure that all resistors have a value. In SPICE 3, resistors without
values are given a default value of 1k Ohm.
* j3 H7 u9 |- K) m6 p% DNegative capacitor and inductor values are allowed in SPICE 3. They
will not be flagged as an error, but can cause timestep problems,
depending on the topology of the circuit.
2. 检查Feedback : 所指的是在序向逻辑电路中所产生的,你可以检查一下你的
1 {& y3 I( l2 c9 `5 V1 |; O0 x2 U电路的FeedBack Path的Delay,在不影响电路功能的情形下,是否可以调快一
2 i: C. s/ I" ?4 E8 q+ E1 y# x! u点或慢一点.

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wu68aq

谢谢分享

lxuande

好好学习，天天向上。