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高速数字信号设计和高速互连7 o. Y0 T! W% K* S4 z2 f* [* |
CHAPTER 1 Transmission Line Fundamentals.......................................... 1
( n+ ?, U+ `0 z& B; sBasic Electromagnetics.................................................................... 1" @. f8 ]: p; Y) R$ `
Electromagnetics Field Theory................................................... 1+ U- _% j/ K# }4 Z# l4 @
Propagation of Plane Waves....................................................... 6' j" l5 [6 L" p Z+ b7 ^
Transmission Line Theory............................................................. 10
# @6 I8 R! w+ b2 u" ~6 x/ v/ rWave Equations on Lossless Transmission Lines.................... 11
* K5 c' \ Q- f2 B5 F. [. }* OImpedance, Reflection Coefficient, and Power Flow* J, D( s5 n/ }2 Q: ^ j5 v
on a Lossless Transmission Line......................................... 14- B* K6 h0 @; F
Traveling and Standing Waves on a Transmission Line ......... 16
# q( g! ]4 u' E0 g, Z( K6 d2 yTransmission Line Structures ........................................................ 188 ]4 G$ Y: Z9 o' U( G3 h0 E
Stripline ..................................................................................... 19! Y; r6 h- n7 U9 N! ?
Microstrip.................................................................................. 20/ R% `# r& v* q3 Y( B! M6 e
Coplanar Waveguides ............................................................... 21( G% d9 C @- h' M* M# z/ G
Novel Transmission Lines ........................................................ 22
1 @* D4 R) {, [- v! f+ `9 aReferences ...................................................................................... 26/ |% |. n: N7 }3 L% Z
CHAPTER 2 PCB design for Signal Integrity........................................... 27
! l: o w0 N N; Y5 i! j) EDifferential Signaling..................................................................... 27
5 z! }& S( \2 M8 Z+ vImpedance ................................................................................. 28
: {7 Q, h* A6 p( S8 P9 C/ uTime Domain Analysis .................................................................. 31
7 ~0 g; s# E/ j% t1 ]# E3 rEye Diagram ............................................................................. 31
- q) p* c" {" v7 b6 `Jitter........................................................................................... 33! [6 ?! J4 x# a6 y! s- o
Frequency Domain Analysis.......................................................... 420 ^$ J7 J& b) B& `/ [- u# t8 ?' Q$ k
Spectral Content........................................................................ 42' e* A/ B! d( L7 T! Z; Q. S$ h& F
Insertion Loss............................................................................ 44/ C: t( X1 g. z/ |: c% D
Integrated Insertion Loss Noise................................................ 46
8 ?" N! U% T0 Z) q* z! A& w1 h, N4 NReturn Loss ............................................................................... 499 ~! Z7 `7 ^1 V
Crosstalk.................................................................................... 51/ o( ]7 `* F; I# B
Integrated Crosstalk .................................................................. 54
& j* k" b+ X' pSignal-to-Noise Ratio................................................................ 552 { o9 L3 K9 Y, Z
Stack-Up Design ............................................................................ 58- [/ P* J0 h- a( u J0 J* h
Impedance Target (Routing Impedance) .................................. 59
$ c* W1 s* W1 jPCB Losses ............................................................................... 61( {0 ^" J) A0 `* ^( J, H
Dielectric Loss .......................................................................... 62 M: [7 u+ l* w4 Z
Conductor Loss ......................................................................... 65
5 z9 N) v( _* \1 A6 bCrosstalk Mitigation through StackUp..................................... 685 X3 G7 B3 _$ l1 j1 g
Dual Stripline ............................................................................ 73
+ D; P$ a( P* H" e- tv
( v; @# ^# |$ d9 pDensely Broadside Coupled Dual Stripline.............................. 84
; V, c6 f" w- r+ C5 @! x( LVia Stub Mitigation .................................................................. 868 R1 F" T- \) B, `9 [6 i8 x0 z
PCB Layout Optimization ............................................................. 95
) R) v% S- w. N( l, q( aLength Matching....................................................................... 96, x r' E; q+ ?% w9 d) \
Fiber Weave Effect ................................................................... 99; n' d6 c1 d( h6 {; }7 H6 t7 R/ d
Crosstalk Reduction ................................................................ 101
9 ~+ t* i& H5 Z" Y/ O A6 [Non-Ideal Return Path ............................................................ 107$ l4 l# h7 s* }1 g0 w/ g
Power Integrity........................................................................ 1108 K9 \9 m4 u) ~; v: g
Repeaters ................................................................................. 111: \ q: B6 a! p. X; R
References .................................................................................... 115+ I3 a0 v/ d7 s! _& Q4 K6 y
CHAPTER 3 Channel Modeling and Simulation.................................... 117
1 D8 w! b/ p7 S; f! oTransmission Lines ...................................................................... 117) u6 A+ Z7 N) ` u9 _% U+ j9 d. [. }
Causality.................................................................................. 117# R9 |: b+ H: H8 X+ v
Checking for Model Causality................................................ 118& ^2 `2 m8 _" q6 H% p* b8 w5 K8 d
Causal Frequency-Dependent Model...................................... 120! o# `5 M5 Q: {
Copper SuRFace Roughness..................................................... 121
" n# y% C8 i1 n D. N) ]% zConductivity............................................................................ 126
; g4 ]% |" O* E) \* p, L4 sEnvironmental Impact............................................................. 127
4 j$ M: k1 y9 i5 fModel Geometries................................................................... 130! S* s0 m3 ]: H; V# B8 `
Corner Models......................................................................... 133
% {, m7 t( y3 e9 ? cIdeal Assumptions: Homogeneous Impedance....................... 137
0 `- l7 Q/ n T3 F; gIdeal Assumptions: Crosstalk Aggressors .............................. 137- p: p- z# a, r% V4 C6 h+ h
Transmitters.................................................................................. 138: \2 P" |6 f3 }
IBIS Models ............................................................................ 1384 @1 d) P4 J! C+ y3 W9 R B
Spice Voltage Source Model .................................................. 139# c0 n( j' F9 ?. d1 v
3D Modeling ................................................................................ 141
6 C" U3 o9 I* oPorts/Terminals ....................................................................... 142 m6 Y% i7 v# ^$ [+ i
Model Analysis Settings ......................................................... 144
' ]5 z# u5 c0 [1 n: i( }Plated-Through-Hole Via............................................................. 146
/ P, i- h/ _# AModel Techniques................................................................... 147* d, Z' x9 ]8 t
Pre-Layout Approximation ..................................................... 148
7 b2 N6 s, a9 P3 O. ?, {Pre-Layout Modeling .............................................................. 148
2 H: |# X3 w3 t8 k& I) Q xPost-Layout ............................................................................. 149# T% Y: J$ l ?
Connectors.................................................................................... 150, p( V7 X# X( Y9 o: i2 K! w" p- Y, T
Connector Variability.............................................................. 150
" q0 j6 J' [% K/ j* RSignal Selection....................................................................... 150
W8 }. q5 ^5 w& T% A9 QSeparated Via Models............................................................. 1522 d9 f0 d" g, ?% V
Unconnected Pins.................................................................... 153
) D) n5 Q2 v4 w+ I: R# ]Physical Features..................................................................... 154
" L5 k: B$ W6 X" k$ ADesign Optimization ............................................................... 154 r( p" B2 {0 w1 H% e3 @
Packages....................................................................................... 156( F% n+ O0 P( H+ J2 v& D9 c
C4 Escape................................................................................ 158
" Z1 ^8 c3 d7 I+ p8 nvi Contents
6 E; B/ x4 y( l% |5 j* [ S4 o/ VTransmission Line................................................................... 158
2 Y3 k5 f% {* y% G5 h* Z$ F9 c" ^PTH Via .................................................................................. 160$ w* s1 ~( u7 L! m' x; K- a5 g* r
BGA Model............................................................................. 160! K) E. f Y: M8 Z
Signal Selection for 3D Package Structures........................... 161
/ c+ Z5 M& B& T6 q) l0 ?& n* [References ....................................................................................161. P9 B5 C5 c, w2 t
CHAPTER 4 Link Circuits and Architecture .......................................... 1631 f8 U p3 L+ P& L
Types of Link Circuit Architectures............................................163
4 P( P6 P/ D( Q/ O9 E3 f* u9 }1 yEmbedded Clock Architecture................................................ 163
; @) [' H G; P% N3 p" K: qForwarded Clock Architecture................................................ 164
1 x y7 P+ R4 k- _Termination ..................................................................................165# U2 W; M( _6 z, _7 |2 h* @
DC and AC Coupling.............................................................. 1651 M% M$ I _0 y3 p1 k. D4 L
Termination Type.................................................................... 1669 Z2 O0 x& b0 l I2 o* u, e
Termination Circuits ............................................................... 167; F" g& u0 j+ y6 y6 J% u5 @; z
Termination Calibration Circuits............................................ 168
% Y; o' {; Z( R# o! _8 A3 oTermination Detection Circuits .............................................. 169
9 X' I/ A8 v2 e: H4 `& lTransmitter ...................................................................................170. w! U6 |" w- h6 y4 H* r
Transmitter Equalization......................................................... 171
) u0 K0 ~- L$ v7 m5 j. M) H& S& T, L1 C. ]Transmitter Data Path ............................................................. 1731 m+ p6 L0 [8 ]! e. h1 k3 {7 X; X
Current-Mode Driver .............................................................. 174
3 u" |7 K$ r- v$ G( tVoltage-Mode Driver.............................................................. 177
% |2 G+ I) ]! E3 pReceiver........................................................................................179
4 c T1 w# I6 |, d+ ?( tReceiver Equalization ............................................................. 180' h5 b% o: B$ ], }" v
Receiver Data Path.................................................................. 1829 p( m) ]( ?8 _" [( n
Continuous-Time Linear Equalizer ........................................ 184) H2 `7 |- `, d2 N
Decision Feedback Equalizer.................................................. 184
" Z: I" p9 N4 [% R4 y) oData Sampler........................................................................... 1860 J) u- S( ]2 [- v
Error Sampler.......................................................................... 186: C+ |* V' c0 s4 e% \: Q9 b
Receiver Calibration ............................................................... 187. G5 i6 w" ~/ _( @ g6 p5 t7 G! ~
Receiver Adaptation................................................................ 1881 F) ^/ A( h( M6 [# R2 m8 ^. W0 A5 U
Clock and Data Recovery............................................................190
5 p# W0 _7 B1 {" fClock and Data Recovery Loop ............................................. 191
F; l3 {$ S, }6 X5 PPhase Detectors....................................................................... 1920 u( S0 ~& w+ V# j9 W3 `# ?
Forwarded Clock Receiver ..........................................................195
$ K1 q9 ?5 u2 q7 z# }* aDelay-Locked Loop ................................................................ 195
1 L2 u& I3 D% z3 r8 ~+ F/ B2 x! e5 B, pDesign for Test/Manufacture.......................................................195
$ \/ X9 Z- b Z6 JAnalog DFx Features .............................................................. 196
! n* P6 M: n; k+ LDigital DFx Features............................................................... 196
# J4 y* X' u# Q- f$ s) m2 PReferences ....................................................................................198/ F% u" b$ B1 k4 E" J
CHAPTER 5 Measurement and Data Acquisition Techniques............... 199
! I/ \5 ?& V6 v3 O! e& rDigital Oscilloscope Measurement..............................................1992 _" r' p1 ^) n* W- k
Real-Time and Equivalent-Time Sampling Scopes ............... 199
0 J v7 V7 c! U) X* V- U1 ~. gContents vii
1 O" E+ o5 b8 h0 bBandwidth ............................................................................... 200
, m. L! a: D3 l2 m, ~& G$ lScope Digital Filter Applications ........................................... 2029 W* `: _* H' y0 Y) l% U V7 t8 t% K
TDR Measurements ..................................................................... 204+ j0 p2 }( w/ c% a
De-skew Differential Pairs with TDR .................................... 2054 f; H- i0 f$ o9 d
Channel Characterization with TDR ...................................... 2070 D# y5 E; R2 R" w, p) [0 R0 q
Return Loss Measurement with TDR..................................... 2099 X( |& e' d2 `" {( G5 j0 C, I
Vector Network Analyzer Measurement..................................... 211
6 M( f1 ]; ]/ B1 _2 Q' g3 e5 p- cWhat is VNA?......................................................................... 211
% u5 U: N1 j, b6 W) ?- mVNA Error Sources and Calibration....................................... 2137 E' M# M0 S$ x3 o6 z
Full Two-Port SOLT Calibration Procedure .......................... 217: g& F- _1 b. p' P; ]" o. w
Example of Measurement Using VNA................................... 217
% ]& a+ V/ j+ X+ h9 k# zVNA Measurement Procedure................................................ 2183 P/ }2 h8 S" o1 G, D! H6 Z
References .................................................................................... 219" z, h5 {7 N: b" v
CHAPTER 6 Designing and Validating with Intel Processors............... 221# v9 b; f# W- ]4 m/ @8 T3 E
Designing Systems with Intel Devices........................................ 221; d& o/ K1 j& R7 U9 @- X! F5 N
Interconnect Model ................................................................. 221; @+ W& h8 s U/ Q2 K5 S; P
Equalization Models ............................................................... 223
8 ^$ s; z W, }1 d- N2 s+ [Automatic Equalization Adaptation ....................................... 225
. W. |! V- ]1 e) BPerformance Analysis ............................................................. 227/ c( R" u2 k7 q% i; _
Solution from Design of Experiments.................................... 232
! X, V' [2 _4 I3 C* Q6 BSolution from Typical Models................................................ 234) z U" t/ M0 L
System Validation with Intel Devices ......................................... 237' U* J. P. k# e! m6 j o
Power-on Preparations ............................................................ 237
u7 a4 ]1 b' j! ~2 e; @( C! @Types of I/O Design Validation ............................................. 2382 C e; Q/ z9 R1 N% i( t2 A2 f
System Margining Validation Overview................................ 239
2 E# u, |2 R! c+ SDDR System Margining Validation ....................................... 244
8 Z* I, k7 N/ N& I& }. [& u: J0 WHigh-Speed Serial I/O Margining Validation ........................ 246
, O* e, i( o2 y9 W( y% I4 L' |# }Low-Margin Debug Guidance ................................................ 2499 j0 a# m2 r& ]& T B6 c& D
Summary ...................................................................................... 250
- ?1 o7 {! d: ~; T& nReferences .................................................................................... 250
2 P5 I+ I7 z: j/ M+ s+ t$ GIndex ............................................................................................................., _, a2 `% T+ D/ M2 h0 V: w
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