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Electrical(电气规则) 0 w1 l% G$ S8 z' Z. N4 T% x* u& l
Clearance(安全间距规则) ) m( ]0 i+ l/ r, B
short-circuit(短路规则) 5 P3 ~& w! s% y7 ^* B" f g
Unrouted Net(未布线网络规则) & B5 Z) H& b: b1 ]
Unconnected Pin(未连线引脚规则)
# W: Z. [% N, |+ r4 NRouting(走线规则)
: X. c# l3 M( D, O' Q @+ o Width(走线宽度规则)
2 V3 `" y1 R* B* O Routing Topology(走线拓扑布局规则)
7 }% _. X9 o5 N$ r* t! v. | Routing Priority(布线优先级规则)
9 V# L; f- M1 p/ @. C+ x3 e Routing Layers(板层布线规则) , y/ L* N) H3 o! q% V) G: r
Routing Corners(导线转角规则)
# N0 D3 w0 B) g% K* M- L Routing Via Style(布线过孔形式规则) 2 V" U# a2 f9 s
Fanout Control(布线扇出控制规则)
' p! }0 D6 k( _0 Y$ w/ \: lSMT(表贴焊盘规则)
^% M; e4 i' @( e# ~* @0 t. d% | SMD To Corner(SMD焊盘与导线拐角处最小间距规则) ( S D; e: e6 v, V
SMD To Plane(SMD焊盘与电源层过孔最小间距规则) 2 ?5 v' p3 j9 J
SMD Neck-Down(SMD焊盘颈缩率规则)
5 A* T; f y. k7 B0 J8 y& |* kMask(阻焊层规则)
: U6 K3 I% i6 m8 J- T- u; S Solder Mask Expansion(阻焊层收缩量规则)
/ m. d) S$ A- r; j1 h" m Paste Mask Expansion(助焊层收缩量规则)
& m5 W& w3 _6 ` N8 _; M* PPlane(电源层规则) / e# i- }% h" ~; _
Power Plane Connect(电源层连接类型规则)
) }7 k. d$ ]' p! A g$ c# G2 X Power Plane Clearance(电源层安全间距规则) $ M% z4 j8 C1 k% [" L) L
Polygon Connect Style(焊盘与覆铜连接类型规则)
) k6 f" i; W5 I, u. d- ETestpoint(测试点规则)
?, ], C6 s {* u9 F. @! m Testpoint Style(测试点样式规则)
- ]. J9 D! y3 B' A& s- o Testpoint Usage(测试点使用规则)
u9 U9 S2 H% |# Y* z WManufacturing(电路板制作规则)
8 v$ @. e- V" [+ t# ?4 X Minimum Annular Ring(最小包环限制规则) 5 e- f9 O) D( k- S
Acute Angle Constraint(锐角限制规则) - `% j, |2 ?, D0 L& w
Hole Size(孔径大小设计规则) ) a6 ~+ t; h* y
Layer Pairs(板层对设计规则) . @" O# C; }3 i; s
Highspeed(高频电路规则) 7 Z7 m, H, s, I
Parallel Segment(平行铜膜线段间距限制规则)
' X% n2 s' }! H Length(网络长度限制规则) % q# J% ^* m3 R1 L& L0 q
Matched Net Lengths(网络长度匹配规则) : G8 U+ w2 W& j' b
Daisy Chain Stub Length (菊花状布线分支长度限制规则) 7 W& W# G i+ [2 \2 z, Q) i
Vias Under SMD(SMD焊盘下过孔限制规则)
2 w6 d- o' k* r; G" w# J5 | ~ Maximum Via Count(最大过孔数目限制规则) # U( M4 C1 Y" e# _
Placement(元件布置规则)
o0 G1 m. }3 E& p Room Definition(元件集合定义规则)
/ O& H6 N7 |* h% D2 ~ Component Clearance(元件间距限制规则) 2 S1 ?7 Y. m) m @6 K- e
Component Orientations(元件布置方向规则) + J9 x, x3 v5 P2 v4 _
Permitted Layers(允许元件布置板层规则)8 Z9 l7 N( X5 e0 n; m! r o
Nets To Ignore(网络忽略规则)
4 i/ v. z- K1 x# T c Hight(高度规则)
. J9 ?8 q- r- v3 R# r) r! q: @$ vSignal Integrity(信号完整性规则) ! [% Q" z7 P2 i, h8 Z' x; o
Signal Stimulus(激励信号规则) 7 E. B2 Z% o# {% I; |% j
Overshoot-Failing Edge(负超调量限制规则)
* [; T# X x- G Overshoot-Rising Edge(正超调量限制规则)
+ S8 Y4 I- r3 l! C Undershoot-Falling Edge(负下冲超调量限制规则)
- r" d) W) [ z* G* _% j4 s+ b1 E/ N Undershoot-Rising Edge(正下冲超调量限制规则)
0 X& X! ^' m1 k Impedance(阻抗限制规则) & D1 R$ r. b6 g S% Y# R
Signal Top Value(高电平信号规则)
9 B) H2 h# Y" {( r# D Signal Base Value(低电平信号规则)
) @4 @3 ?& J( p$ ~0 f( F0 e7 M Flight Time-Rising Edge(上升飞行时间规则) / L9 D5 p5 u, d/ {5 \. H
Flight Time-Falling Edge(下降飞行时间规则) ) r' R, Q2 H1 ?9 X3 \
Slope-Rising Edge(上升沿时间规则) ( e7 v. h6 d9 x1 y7 W: v
Slope-Falling Edge(下降沿时间规则) ?# x1 m. m/ a0 L
Supply Nets(电源网络规则)
S l7 n4 v: N6 f# d9 I- z! R& ]+ I2 K+ F& K) y
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