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Electrical(电气规则) 0 d) q r9 o& E
Clearance(安全间距规则) 1 M3 @$ v# r/ c. y
short-circuit(短路规则) 2 K9 k9 ]: v: c1 d
Unrouted Net(未布线网络规则) 6 _' x; ?) J3 ?2 e: ]' y: i; B
Unconnected Pin(未连线引脚规则) ' d) m, L) P! W9 M+ i/ x2 T. ?
Routing(走线规则) % v" v8 t8 I3 V% t
Width(走线宽度规则)
% U% n) [. z/ V. f! B2 @+ } Routing Topology(走线拓扑布局规则)
/ e5 d5 u; e% k4 T0 h. Y" ~3 K Routing Priority(布线优先级规则) / M9 H n8 O: x+ W
Routing Layers(板层布线规则) / n7 ^' u' Q }( r( S+ o0 Z
Routing Corners(导线转角规则)
# N% m4 K |+ n0 F Routing Via Style(布线过孔形式规则) , H. T# Q& X8 K) d0 c+ t& {. ]; W
Fanout Control(布线扇出控制规则)
! v: c `; y' \6 _( D( eSMT(表贴焊盘规则) . h: j" Y3 j* i) l5 J# r
SMD To Corner(SMD焊盘与导线拐角处最小间距规则) ! a* U( X& u1 i0 k% i
SMD To Plane(SMD焊盘与电源层过孔最小间距规则)
; M8 `* t: O7 o' [3 d- s SMD Neck-Down(SMD焊盘颈缩率规则) 2 N+ \1 V9 Y9 F
Mask(阻焊层规则)
# ~6 T+ C/ e4 n! Q. H Solder Mask Expansion(阻焊层收缩量规则) 7 C% O( K8 X" ^8 l% g. Z# |/ S
Paste Mask Expansion(助焊层收缩量规则)
# W$ b9 F6 |5 o2 ^; XPlane(电源层规则)
6 ~2 S- T# \2 Z" n4 R% u& o Power Plane Connect(电源层连接类型规则)
) }' L9 l# {' \ Power Plane Clearance(电源层安全间距规则)
6 m: B0 x; j2 m Polygon Connect Style(焊盘与覆铜连接类型规则)
- F, S- D1 {( p* tTestpoint(测试点规则)
) l' ]0 v5 i" k. K+ m+ v- Z4 K Testpoint Style(测试点样式规则) , z$ Y9 b# x7 k C
Testpoint Usage(测试点使用规则)
! G* `7 U5 f; ?* jManufacturing(电路板制作规则) ) V5 v- h0 u* e9 f9 u1 W7 U0 S# y
Minimum Annular Ring(最小包环限制规则) % L# D% y1 _- {- _6 l* g' K
Acute Angle Constraint(锐角限制规则)
& n; U7 x2 Q/ ~- m Hole Size(孔径大小设计规则) & ]3 r7 h$ t4 [9 V
Layer Pairs(板层对设计规则) & Y8 u1 u; s @! J) p& j( m u
Highspeed(高频电路规则)
4 a* f/ f" b0 G( \. w* }1 y! k9 ^ Parallel Segment(平行铜膜线段间距限制规则) 8 S+ }# ~7 n7 i7 {4 q# V2 n8 d- }0 O
Length(网络长度限制规则)
6 x/ B/ Q. m. J" P$ [ Matched Net Lengths(网络长度匹配规则)
, H, f R( D0 q+ T8 Y Daisy Chain Stub Length (菊花状布线分支长度限制规则) 8 `; |) m$ ?1 p6 q# _
Vias Under SMD(SMD焊盘下过孔限制规则) W9 l p& }: Q
Maximum Via Count(最大过孔数目限制规则)
$ ?0 f6 a' {; _Placement(元件布置规则) 5 M5 e; ^, P8 y/ V0 ?: }
Room Definition(元件集合定义规则) ' p, D2 f+ P: _' Z
Component Clearance(元件间距限制规则) 7 w) h8 p9 N+ m) K7 f9 o
Component Orientations(元件布置方向规则)
9 ^2 B7 z1 z+ z/ b' S Permitted Layers(允许元件布置板层规则)" Y" c7 f6 m4 ]+ U2 V+ U, \
Nets To Ignore(网络忽略规则) ! P: b' ]& C! _( y" j5 E+ Y- \2 b, ]) d
Hight(高度规则)
$ S+ l2 E; R8 l7 C, PSignal Integrity(信号完整性规则)
1 }8 |& j6 q# O" c( x/ U2 k( | Signal Stimulus(激励信号规则) 9 K9 P. X8 u- ]# b
Overshoot-Failing Edge(负超调量限制规则) 6 P: Y- _1 m- K& l2 O% Y
Overshoot-Rising Edge(正超调量限制规则)
2 S Y$ T% }' g6 K: l0 C' E Undershoot-Falling Edge(负下冲超调量限制规则) / T$ G1 o6 y$ a) n' J
Undershoot-Rising Edge(正下冲超调量限制规则) , J( Z$ S+ ^- e# `
Impedance(阻抗限制规则) 9 q2 K) T, r0 B/ U/ C, W
Signal Top Value(高电平信号规则)
4 s# ?( @" j4 X# h, n7 `; [* y Signal Base Value(低电平信号规则)
( r: j. p. i$ [; t! j7 e: t0 o) f" e Flight Time-Rising Edge(上升飞行时间规则)
. B2 W# _8 \$ ?, \ Flight Time-Falling Edge(下降飞行时间规则) ) `! U% Z0 w% X% U: c' ?' J: o
Slope-Rising Edge(上升沿时间规则) & m* E( x/ ?, F3 M: h1 R3 D
Slope-Falling Edge(下降沿时间规则) 5 I1 @6 G6 y6 U
Supply Nets(电源网络规则)
$ @8 E e. I4 H, \: d
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