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在网上寻找数字地与模拟地的英文材料;
r; _! ?( D- Q0 G; b6 b( L( ~0 x无意间浏览到一个国外的的cpld/FPGA论坛,点击进入; }: h- e6 Y) L* [2 g% O6 H: F
发现了有人求51的IP CORE,在回帖里面看到这个,所以下载了。* [2 ~1 ]6 {! w+ K
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& V1 z0 w/ Q) W7 ^" q6 F@: mc8051@oregano.at4 v( v6 X, I( F: g# C; t
W: http://oregano.at/ip/8051.htm
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' F% t$ h' U6 ~, z) M************************************************************% x! [9 ~" o$ ]6 V8 m' S
This is version 1.4 of the MC8051 IP core.& d( x5 D* R) |. H9 c: A4 ^
November 2004: Oregano Systems - Design & Consulting GesmbH
^# p6 M+ I1 S% J6 p============================================================- f0 _8 ?6 v$ J3 T: S0 i
Changes:
" v) U4 ^; }4 c9 z; d& N- corrected behaviour of RETI instruction handling' R! O; ^- F, r8 K1 o6 c# z8 \0 r
- added synchronization for interrupt signals
2 ]0 B: s- K. D# E3 E- corrected timer problems: }5 ~6 Z0 ]" P1 a& u
6 \* Y. m: V. {5 O% Q" d************************************************************/ `. a+ a8 N5 I6 i2 w t. `
This is version 1.3 of the MC8051 IP core.
" S' r( a1 ^- J2 Q$ R' r9 zSeptember 2002: Oregano Systems - Design & Consulting GesmbH! Q; s- f! n' E P
============================================================/ A- v# s) c- T* l5 O% ]* Y
Change history:
7 n1 ~" g$ z: h- Improved tb_mc8051_siu_sim.vhd to verify duplex operation.
0 H5 A2 K4 g& l3 ] g4 d/ Y- Corrected problem with duplex operation in file
. }/ o+ e8 o6 S mc8051_siu_rtl.vhd9 C ^$ `* Q9 v6 i' y, t
3 [' f3 p7 ^3 F************************************************************7 M+ C: j' Z$ f# I' @5 C3 O9 r4 a5 t9 u
This is version 1.2. of the MC8051 IP core." h+ Q5 G/ V% V8 I
June 2002 - Oregano Systems - Design & Consulting GesmbH
2 a H+ o) q1 T============================================================8 R% O0 r) r9 _8 t2 S# X
Change history:0 \+ w7 k! a/ ~" {: q) L$ {
- Eliminated the scr subdirectory form the distribution.) l ]2 d! f' r6 W, U
- Improved documentation./ L5 a2 `9 H% |% h
- Corrected several bugs in the source code (see the4 w' V7 G7 H. L" s" B
website for more details).
7 z7 K/ H, ~/ n2 {8 b# F; V7 M! p- Improved the testbench with respect to the I/O port
" O, }* H3 @/ h; a1 l behavior. R, ?. F4 `! V" r; U$ n
- Enriched the msim directory with the assembler source
9 S. M7 O. u, z0 R7 `/ R) b code of an example program.
+ ]8 t$ n/ o$ R) \% J p- n' T- Provided the source code of a Intel hex to binary
/ O& z. P* @# L! {" [ textfile converter to ease simulation of the user's2 C2 h* w; E! V/ j4 j
assambler programs.* d! W6 ]7 x5 a" s) V
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************************************************************6 c( i; L' ^ N( _$ \
This is version 1.1. of the MC8051 IP core.( N: W% e1 _( t; Q9 g5 `
Jan 31st 2002 - Oregano Systems - Design & Consulting GesmbH
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下面是里面的部分VHDL
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library IEEE;
/ W& W1 s" P7 suse IEEE.std_logic_1164.all; * H- A8 J2 i! W: M: D
use IEEE.std_logic_arith.all;
3 N' d4 \6 b* m1 Clibrary work;
9 d* S' x' A4 e) L* Zuse work.mc8051_p.all;
2 |5 e. H" k1 Z5 v
2 E* D# M8 [) s0 }* k( }-----------------------------ENTITY DECLARATION--------------------------------' ^9 z7 w1 e. S) ]
entity addsub_core is
; O3 |+ S! _0 E
) n9 N2 x$ y4 N5 S; P generic (DWIDTH : integer := 16); -- Data width of the ALU+ u% a3 O* O6 E
port (opa_i : in std_logic_vector(DWIDTH-1 downto 0);
9 S6 `% _8 t9 C6 m0 \7 I" [ opb_i : in std_logic_vector(DWIDTH-1 downto 0);
* }6 q% J6 e4 g- k- ? addsub_i : in std_logic;
6 x6 B6 }1 E5 |/ [6 [% \ cy_i : in std_logic;! Q$ b# Q; o( C
cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);: P: [; p, C4 |" U. D& i
ov_o : out std_logic;
}3 c# G; b3 B8 h2 ] rslt_o : out std_logic_vector(DWIDTH-1 downto 0));
* d0 C- d9 b! `' S0 d8 n
/ M; m8 M W* H rend addsub_core;! i; }- ^3 r7 h4 t; J$ W6 _2 A
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% H5 J9 }/ `1 X) |" B& k: `entity mc8051_alu is& S/ I, ~. t! P! Q; F- y. M' h8 _
generic (DWIDTH : integer := 8); -- Data width of the ALU/ P- i* g0 k3 Y& L5 z* v2 f
port (rom_data_i : in std_logic_vector(DWIDTH-1 downto 0);8 W7 R) B: _2 D. c
ram_data_i : in std_logic_vector(DWIDTH-1 downto 0);6 v) c1 x: _! L g5 f
acc_i : in std_logic_vector(DWIDTH-1 downto 0);
, x, Q: Y0 t; |6 N6 C, p) \ cmd_i : in std_logic_vector(5 downto 0);3 H2 w+ P" m; V! B, E7 H5 L2 m
cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0);4 X& ~7 f# W, b' Q5 n" q
ov_i : in std_logic;
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3 }2 e7 l ]. j* z- K new_cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);
5 Z& ?" E% D# V( \' c" H$ Y/ v new_ov_o : out std_logic;+ r7 q4 l# y7 s! L, l: x# P$ y
result_a_o : out std_logic_vector(DWIDTH-1 downto 0);
+ p3 G& d& P1 d result_b_o : out std_logic_vector(DWIDTH-1 downto 0));
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end mc8051_alu;% f7 B6 D: n1 t3 B
--Inputs:( ]1 h* P0 }" s3 k7 m
-- rom_data_i...... data input from ROM
9 p& n5 q r' w- x/ v-- ram_data_i...... data input from RAM
5 U6 ?' h+ C m-- acc_i........... the contents of the accumulator register
5 |3 \# O# `7 e6 @# i1 K) q1 m-- cmd_i........... command from the control unit
# u# W7 V8 F7 y1 p5 `- D8 Q- G-- cy_i............ CY-Flags of the SFR
0 O0 S1 I$ ?, }7 z: \) [-- ov_i............ OV-Flag of the SFR
2 _" P/ T& W7 x* _* k9 T4 t--Outputs:& s$ y/ a. X. L9 l6 s5 s
-- new_cy_o........ new CY-Flags for SFR- p) D6 D" ^& }3 H2 ]
-- new_ov_o........ new OV-Flag for SFR. `: q0 ~" C1 J3 @( P0 w4 m
-- result_a_o...... result
/ F( A4 v. O8 v& G- b% [9 {-- result_b_o...... result
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8 |- e# y$ `' z. C* w" Tarchitecture struc of mc8051_alu is
$ S% b+ r1 e' W0 U5 z: [ signal s_alu_result : std_logic_vector(DWIDTH-1 downto 0);2 O+ f( {) D$ |: ?% \4 s( F
signal s_alu_new_cy : std_logic_vector((DWIDTH-1)/4 downto 0);, U0 Q: v" H5 m8 d2 R* F+ X& w
signal s_alu_op_a : std_logic_vector(DWIDTH-1 downto 0);
! `- r: R5 z, h signal s_alu_op_b : std_logic_vector(DWIDTH-1 downto 0);, |4 L m* Y5 y6 Z- A" l! t
signal s_alu_cmd : std_logic_vector(3 downto 0);
2 ]- i7 C: p( Q$ N# N signal s_dvdnd : std_logic_vector(DWIDTH-1 downto 0);2 f3 N$ x7 D/ L
signal s_dvsor : std_logic_vector(DWIDTH-1 downto 0);
# A+ z' z5 } _' ^5 [6 y signal s_qutnt : std_logic_vector(DWIDTH-1 downto 0);6 I2 U4 z- T$ \$ u5 j1 T' G! Y2 C& b P
signal s_rmndr : std_logic_vector(DWIDTH-1 downto 0);
) M" d0 [% H% _( S signal s_mltplcnd : std_logic_vector(DWIDTH-1 downto 0);
+ ] m3 S% e8 s' J signal s_mltplctr : std_logic_vector(DWIDTH-1 downto 0);
! Z: M) J9 @# V) ^5 R signal s_product : std_logic_vector((DWIDTH*2)-1 downto 0);
+ h* ]( P8 R, w0 ?! N) L signal s_dcml_data : std_logic_vector(DWIDTH-1 downto 0);7 Q$ t( Z( x3 u7 p( r; P
signal s_dcml_rslt : std_logic_vector(DWIDTH-1 downto 0);
" b: C- r- _8 g6 T* _+ j. k signal s_dcml_cy : std_logic;
0 b& R9 v' Z& U+ ~- {' u I signal s_addsub_rslt : std_logic_vector(DWIDTH-1 downto 0);
2 u. Y) m; {# t* ~4 l5 G. @ signal s_addsub_newcy : std_logic_vector((DWIDTH-1)/4 downto 0);4 {4 Y5 q8 L. u
signal s_addsub_ov : std_logic;2 d8 I: H, s# G) U( Y5 ^7 b
signal s_addsub_cy : std_logic;9 y6 [; D% Q9 g% x" z2 W8 K3 l
signal s_addsub : std_logic;9 i! W* w# l$ E% |! e' m
signal s_addsub_opa : std_logic_vector(DWIDTH-1 downto 0);
5 y! S- x1 l `6 a' I- Y signal s_addsub_opb : std_logic_vector(DWIDTH-1 downto 0);
' i- r0 G3 ?0 Z0 E4 i0 Kbegin -- architecture structural( v- `$ e, t W/ k
i_alumux : alumux
+ }/ l8 V. B4 z generic map (
. T; X, {. U3 g DWIDTH => DWIDTH)
' ^( c) S5 l" f8 M0 n8 W port map (' J B) r8 w. B9 E7 [
-- Primary I/Os of the ALU unit.
2 i! Y( ]8 n1 h0 x( y rom_data_i => rom_data_i,
; A1 e, Z9 S$ M# S+ D ram_data_i => ram_data_i,
5 A- l: J6 @% M& T5 r acc_i => acc_i,
. Y7 D! r% J: B7 u cmd_i => cmd_i,2 ^; i% i& y$ N# Q, x
cy_i => cy_i,
% U4 E- q: x9 c' \, N ov_i => ov_i,! |! J4 {, R) M- W/ `* x
cy_o => new_cy_o,
4 f) C( R9 V% ]" |) e: k ov_o => new_ov_o,$ `, ^' l. H& ?! i- o' S' S( b0 }
result_a_o => result_a_o,
' I) `( w9 g( W+ }3 x& q: Y result_b_o => result_b_o,# ? y; w/ W; ?. |: _+ e6 S5 c
-- I/Os connecting the submodules.
% @: f% m. U$ ]6 ^0 E/ Z1 n result_i => s_alu_result,
" b7 r- h' Y/ t. v1 l S new_cy_i => s_alu_new_cy,
0 j$ u R2 k5 E; [; V1 m8 E) ?9 S! k addsub_rslt_i => s_addsub_rslt,
- r7 \- s: c2 n, C3 W% ] addsub_cy_i => s_addsub_newcy,
3 L# i& ^: \- u; b1 E* |8 u addsub_ov_i => s_addsub_ov,
1 A" N' K/ P: V l0 ? op_a_o => s_alu_op_a,
# `4 W2 c9 }8 S% O op_b_o => s_alu_op_b,
3 H' W5 f, i: u/ g. R8 K alu_cmd_o => s_alu_cmd,. @$ D# @$ q3 I! Z) Z
opa_o => s_addsub_opa,+ ^4 u" O% L- S8 ~! [6 ^$ l$ K6 D
opb_o => s_addsub_opb,
0 k( }3 T' c1 O; b. }6 B O addsub_o => s_addsub,
! u# f* D! V$ j7 Q6 U; k addsub_cy_o => s_addsub_cy,4 E9 t9 }% v: a9 a
dvdnd_o => s_dvdnd,
9 C: T! o% |# m( { dvsor_o => s_dvsor,4 ^ d% z6 _$ H4 U
qutnt_i => s_qutnt,% R9 v, M( l, H2 a5 F
rmndr_i => s_rmndr,
1 { `/ m% H7 n4 N9 ^5 _ mltplcnd_o => s_mltplcnd,
) |9 y( m [$ U" ]4 I9 ~8 v4 k mltplctr_o => s_mltplctr,
; Q/ I$ U+ H7 c1 g product_i => s_product,
" p5 g" a$ T: Z4 C! B) |7 x( S dcml_data_o => s_dcml_data,
! Q" i3 ^8 N6 v dcml_data_i => s_dcml_rslt,) x! X n* [& n" f: P# D: s
dcml_cy_i => s_dcml_cy);( ]; Z- `) L5 J7 n5 r
i_alucore : alucore% W `% ?' j; q% ]0 I: ^7 Z% W
generic map (
, E* L0 i; B/ o# P2 B- q g* s+ p DWIDTH => DWIDTH). ?: Q+ e; ]1 D) e
port map (
9 _& P# p6 u! y# ~0 |: _ op_a_i => s_alu_op_a,
! J* x$ I3 j! f2 v' |, F! _ op_b_i => s_alu_op_b,4 H( A, v' t: M. E4 V9 v$ D K9 v
alu_cmd_i => s_alu_cmd,
/ Q+ @* x; @3 s0 V7 x* ] cy_i => cy_i,% C* i/ `3 w+ t0 A+ a- h1 h
cy_o => s_alu_new_cy,
( H8 e t4 R, H) _' M3 j7 G1 X result_o => s_alu_result);
! T% z$ K- {* H0 X! \ i_addsub_core : addsub_core
5 K% A, A2 j% X' z: D generic map (DWIDTH => DWIDTH)
+ o" ]' Z. u; a: ~3 \1 G port map (opa_i => s_addsub_opa,
* f! I" M* `- K7 { opb_i => s_addsub_opb,
, u3 U7 ^' c8 W' p! }2 t+ k& @ addsub_i => s_addsub,
0 m7 k) ?4 s& ] cy_i => s_addsub_cy,
: s3 i) Q, p* O# j( N" ^/ f) R4 z cy_o => s_addsub_newcy,
" v$ H4 s1 j. M9 w' E. _ ov_o => s_addsub_ov,
4 i: M( x$ [* E; G3 b0 ?6 | rslt_o => s_addsub_rslt);4 z0 m" z' @. O
gen_multiplier1 : if C_IMPL_MUL = 1 generate
# k4 l: c: h% `: K4 d) Y4 C i_comb_mltplr : comb_mltplr
& B6 q) }/ p) K' j1 O$ f4 H1 _ B generic map (
7 p2 {. C4 \! Z- _9 u7 D& ?) ?! I DWIDTH => DWIDTH)8 _! U) N8 E8 {* \$ k6 c
port map (
, [) C: o8 `) Z; e! V mltplcnd_i => s_mltplcnd,
% N" D8 w8 x' w& A) W mltplctr_i => s_mltplctr,$ K, L4 p1 H8 g" F
product_o => s_product);8 I7 J1 M& M/ f% Y9 m) o. o
end generate gen_multiplier1;: f3 ~4 G" |. n Z6 Z$ j; l/ b% W
gen_multiplier0 : if C_IMPL_MUL /= 1 generate
/ d+ @9 o& d- R/ s s_product <= (others => '0');* d P4 ?# M# i# b6 P) a" y" r4 u) c
end generate gen_multiplier0;- q% Z: Y4 i) p2 _% g) J5 s# t
gen_divider1 : if C_IMPL_DIV = 1 generate
! r& } z3 R$ ~/ p i_comb_divider : comb_divider/ B3 s: Y7 E" z* ^' t+ i$ A7 Z
generic map (, j# |. o" b% [3 E
DWIDTH => DWIDTH)
s8 T6 ]6 d( t# Y7 r port map (8 h5 q/ L3 j# y
dvdnd_i => s_dvdnd,3 H6 X: E" { S# R* b3 m
dvsor_i => s_dvsor,$ d2 e7 x: a2 _2 ?7 w! Y/ _
qutnt_o => s_qutnt,
$ S; D1 }6 @% Y$ H2 X rmndr_o => s_rmndr);
9 Z7 j }, E3 y3 g. K end generate gen_divider1;3 s- w, M6 Z% G! V
gen_divider0 : if C_IMPL_DIV /= 1 generate
0 [1 `; a1 w0 R# K& H8 o* e) b7 z2 ^ s_qutnt <= (others => '0');
# j) v8 Y8 m8 S( T/ V1 [8 X s_rmndr <= (others => '0');
}5 I \: M P: V) x A6 {& j end generate gen_divider0;; }4 F/ m; f1 a# ]" I: \/ x5 a! Q0 b
gen_dcml_adj1 : if C_IMPL_DA = 1 generate
: B& M1 s; H2 f% v' B/ n i_dcml_adjust : dcml_adjust
" t3 c9 {; t3 b& @& f: b) G generic map (
1 s- ^2 {- T/ t- W3 e& Y DWIDTH => DWIDTH)+ [. P+ w2 {3 V, J4 F
port map (
/ q# [: ~1 G( w7 U9 v# w4 }- O data_i => s_dcml_data,
& M9 K. P5 |) ~' r: A0 s cy_i => cy_i,% k1 R- }# \6 B
data_o => s_dcml_rslt,
; z! [# b5 e8 [ Y2 E cy_o => s_dcml_cy);
% O: B- t& M+ D2 Q! V& I end generate gen_dcml_adj1;
# P6 }0 \' j5 [) |8 V& g5 E gen_dcml_adj0 : if C_IMPL_DA /= 1 generate m& \) K! r7 h! [# P! Q
s_dcml_rslt <= (others => '0');, m9 Y9 y! G$ e! P' l" e$ d$ d& R6 d
s_dcml_cy <= '0';% @7 L* g( p4 Y: W0 ]
end generate gen_dcml_adj0;# U' Z4 V7 f; P+ E" z
end struc; |
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