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在网上寻找数字地与模拟地的英文材料;
8 W; v9 [" u; L- c/ I9 ]( E2 n无意间浏览到一个国外的的cpld/FPGA论坛,点击进入) }, A. t2 Y. L3 I; z
发现了有人求51的IP CORE,在回帖里面看到这个,所以下载了。1 n, q& Y, I- S
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, v! _& ]0 s) }+ m- m8 f, F@: mc8051@oregano.at
* [3 d. y! \! H% z# YW: http://oregano.at/ip/8051.htm7 j" Z% f, \9 B2 H* j7 |
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************************************************************' l6 ], v( t8 V# y
This is version 1.4 of the MC8051 IP core.
1 b5 ?7 ]* i0 H. H% L* w. d; H( ~$ uNovember 2004: Oregano Systems - Design & Consulting GesmbH
- X2 N, A1 x8 k' N5 Q3 m& k# [: u============================================================
; N; C$ V* p/ q* P! I3 W. eChanges:
. c7 B0 b) r9 R2 D/ N7 r4 z- corrected behaviour of RETI instruction handling5 h* s% x9 C" Q1 e; B2 e* b
- added synchronization for interrupt signals6 o5 M7 S0 C# ]+ N8 w, Z
- corrected timer problems
7 F' A) j4 P* w6 @! g+ [, W- j1 `$ y7 v# Q# N8 ~. b3 D
************************************************************
+ `: V0 a% u, d: u0 ?This is version 1.3 of the MC8051 IP core.* }/ x+ C [7 l( [7 M( d
September 2002: Oregano Systems - Design & Consulting GesmbH
) d9 I; X/ b7 @6 @& S============================================================5 s) P( d% z1 D* v" b9 @3 W
Change history:. z: C. D5 N; q1 q- [
- Improved tb_mc8051_siu_sim.vhd to verify duplex operation.* {" Y2 z( `/ j8 h
- Corrected problem with duplex operation in file
4 q; Z. v1 S1 k( p3 O# N- J mc8051_siu_rtl.vhd
* {3 q7 j0 j% o: _& s4 _
8 f9 e$ k5 x- {# I************************************************************6 L R, T0 t0 Z/ x2 e
This is version 1.2. of the MC8051 IP core.
7 W; ^) A h; z' F8 OJune 2002 - Oregano Systems - Design & Consulting GesmbH0 r' p \- E: K Q
============================================================" @/ ^* }- y) m. C5 m
Change history:
; e0 D: p5 p3 m# Q7 K J4 O9 E) A( R- Eliminated the scr subdirectory form the distribution.
, N( J+ s; b/ w9 Y7 V5 R# C- Improved documentation.+ [( X2 z8 w" {/ {, Q& {
- Corrected several bugs in the source code (see the; _9 P2 L4 s6 s! `6 S% A
website for more details)./ _% h0 t/ e, U1 s3 C
- Improved the testbench with respect to the I/O port
0 Z1 c$ {8 F. u0 L' y/ _ behavior.
; e5 |+ M3 }! v8 [2 H* v- Enriched the msim directory with the assembler source: Y8 d! y! y6 A7 P# d& v
code of an example program.0 C2 X( f: E+ S1 h
- Provided the source code of a Intel hex to binary- R t" o0 H; g j
textfile converter to ease simulation of the user's7 B9 @; y- l& i$ I$ T, s
assambler programs.4 e" G0 p8 u. }2 x1 L1 v1 H* {
1 b1 L# |# U6 X+ v X1 N
************************************************************
0 J' k2 e+ m& s: Q' A1 z/ SThis is version 1.1. of the MC8051 IP core.
% R7 q) R$ C% ]9 d' |( h7 c S0 c! FJan 31st 2002 - Oregano Systems - Design & Consulting GesmbH
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( A l: q/ l2 G$ p g! Z* U下面是里面的部分VHDL4 s7 } N1 e9 x2 R' o% ?
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* W# |4 Z* g) Slibrary IEEE;
2 |2 b* D# u$ A7 juse IEEE.std_logic_1164.all; * h( s: w" a( g' f9 \- Z, ]3 s
use IEEE.std_logic_arith.all; E$ O, w' z" R$ }% L! R; Y
library work;" f' g2 z9 F ~! l q4 V/ }
use work.mc8051_p.all;
# ?% k: f- i6 x7 H0 p" u
/ g( ^9 Q. U$ ?( ]& @-----------------------------ENTITY DECLARATION--------------------------------
7 u, G. @1 { y& Y, `! U0 }entity addsub_core is' x N6 K0 x+ L/ v1 |
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generic (DWIDTH : integer := 16); -- Data width of the ALU
; g) X" o0 t3 ^% S port (opa_i : in std_logic_vector(DWIDTH-1 downto 0);* t% v; g0 S" [. ?8 N C* B8 N2 m
opb_i : in std_logic_vector(DWIDTH-1 downto 0);
: R, O G4 t, Y& P addsub_i : in std_logic;2 w1 ?0 f6 g' q% ?+ N
cy_i : in std_logic;/ o- A- z1 j: v* [1 L* g
cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);/ n9 R9 ?, O( q2 g6 b, O/ A
ov_o : out std_logic;
: C% Z: O) c$ V: h' O2 Y rslt_o : out std_logic_vector(DWIDTH-1 downto 0));
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end addsub_core;5 a& u1 X$ x* x
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7 z; H/ e5 u8 l6 P. [entity mc8051_alu is; n- e1 V8 `/ t1 a
generic (DWIDTH : integer := 8); -- Data width of the ALU
" M2 n0 k5 ?6 a! ^3 D% b- j port (rom_data_i : in std_logic_vector(DWIDTH-1 downto 0);
& C+ I6 V T1 ~/ X7 V ram_data_i : in std_logic_vector(DWIDTH-1 downto 0);
8 Y- M6 P/ R; W2 E8 ]4 V acc_i : in std_logic_vector(DWIDTH-1 downto 0);; g( v; X( U( D! u
cmd_i : in std_logic_vector(5 downto 0);
; A2 N) p6 K0 G# j2 a cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0);
9 h+ ]6 h! l; n" a$ S ov_i : in std_logic;
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new_cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);
1 p" E# y) B+ } new_ov_o : out std_logic;" n" q8 V/ ^2 X; ?
result_a_o : out std_logic_vector(DWIDTH-1 downto 0);' Z2 g: p% h3 i. N+ d+ r
result_b_o : out std_logic_vector(DWIDTH-1 downto 0));2 q' l0 |+ e* H3 q" ` J" h& K
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end mc8051_alu;
2 b! l' K, W2 o! d; J--Inputs:
) A2 W, j* Z7 q2 j8 ?5 a-- rom_data_i...... data input from ROM
4 t; r1 e+ N' h5 s7 l L4 U; J2 i-- ram_data_i...... data input from RAM5 P* U$ M9 G1 I8 L
-- acc_i........... the contents of the accumulator register
' V3 Q; ~0 a1 h' l# V-- cmd_i........... command from the control unit* t1 P9 p/ ~# Q1 C, s7 p3 m8 g
-- cy_i............ CY-Flags of the SFR
$ [4 Q0 x# `3 U5 G9 d-- ov_i............ OV-Flag of the SFR
8 Y* M S6 `. `) d- \--Outputs:
# H2 d O( E5 M' a" [' S-- new_cy_o........ new CY-Flags for SFR
: D# V. U+ c: i$ d-- new_ov_o........ new OV-Flag for SFR
z* i: ?1 Q$ c/ r* @) p9 _-- result_a_o...... result5 E; L2 b9 Z4 }; j' r$ G+ a
-- result_b_o...... result
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architecture struc of mc8051_alu is
* _% R+ s) E% k$ Y8 P signal s_alu_result : std_logic_vector(DWIDTH-1 downto 0);
$ M6 p- L3 K; y# t* x signal s_alu_new_cy : std_logic_vector((DWIDTH-1)/4 downto 0);
& ]7 p$ w) p p signal s_alu_op_a : std_logic_vector(DWIDTH-1 downto 0);
7 x( r9 x, r! {$ k' B2 T signal s_alu_op_b : std_logic_vector(DWIDTH-1 downto 0);; W9 @ ^) S- N2 j, k" h
signal s_alu_cmd : std_logic_vector(3 downto 0);
, h% t8 z2 u& |) E, C- E; ~' l signal s_dvdnd : std_logic_vector(DWIDTH-1 downto 0);
/ j) L' j. [7 q1 y signal s_dvsor : std_logic_vector(DWIDTH-1 downto 0);9 ^/ X' J2 M' J) f4 b
signal s_qutnt : std_logic_vector(DWIDTH-1 downto 0);
n6 _ _- v. c+ m1 G# C signal s_rmndr : std_logic_vector(DWIDTH-1 downto 0);" x" m9 i& v) `; u& c
signal s_mltplcnd : std_logic_vector(DWIDTH-1 downto 0);
+ E: M4 c0 E. H7 A* u. O signal s_mltplctr : std_logic_vector(DWIDTH-1 downto 0);! N9 m$ `. z; v$ `
signal s_product : std_logic_vector((DWIDTH*2)-1 downto 0);5 x' {4 ]' d4 C# j
signal s_dcml_data : std_logic_vector(DWIDTH-1 downto 0);! ?$ H2 r* l, K7 [# N
signal s_dcml_rslt : std_logic_vector(DWIDTH-1 downto 0);
@' ^6 }! b; N- Q$ _ signal s_dcml_cy : std_logic; N# Q4 E6 j$ D5 Q4 ^
signal s_addsub_rslt : std_logic_vector(DWIDTH-1 downto 0);7 m% u/ |* i9 m# ?# }
signal s_addsub_newcy : std_logic_vector((DWIDTH-1)/4 downto 0);
, J0 U3 ?$ [$ w0 q signal s_addsub_ov : std_logic;( z2 s- u# a2 T( v
signal s_addsub_cy : std_logic;
/ Q7 ~8 V# g$ |8 h signal s_addsub : std_logic;( Z- Y1 e" S1 H' L; w! X1 m0 j* D
signal s_addsub_opa : std_logic_vector(DWIDTH-1 downto 0);5 i6 i y7 _: O/ Z7 W
signal s_addsub_opb : std_logic_vector(DWIDTH-1 downto 0);: {* q& e! K) e1 m$ s
begin -- architecture structural! O% \+ e) D4 k6 A) S! A( L
i_alumux : alumux `& D3 B" s; i9 X3 t* I0 j
generic map (
w0 n4 j( D) [4 K DWIDTH => DWIDTH); \ R8 S. I4 x B9 M
port map (
' O" X5 @6 r p( v -- Primary I/Os of the ALU unit.; W% B+ D, j" f7 X+ {4 I' ~
rom_data_i => rom_data_i,$ y( D% C3 N' L. P3 T( X$ t" ~
ram_data_i => ram_data_i,
9 p$ V/ G7 C) ^' z acc_i => acc_i,
3 k: ]8 t- n% f' }1 a3 C cmd_i => cmd_i," T: j( m# Q/ V: y1 z5 \
cy_i => cy_i,% I0 T, ?1 B z! `$ q" G8 R& X
ov_i => ov_i,
+ H# [( [! X+ @0 p" W# a; I1 a cy_o => new_cy_o,
8 k, v, {1 s8 Q ov_o => new_ov_o,
x* E. Q8 h4 v/ n( G result_a_o => result_a_o,- t5 C% Z- L# n5 G, w/ i0 r( q
result_b_o => result_b_o,
8 n2 S! ~ ]" C1 P4 |- p F* [ -- I/Os connecting the submodules.
2 @. }& B1 e$ h1 y result_i => s_alu_result,
. L. U: f. [6 u new_cy_i => s_alu_new_cy,5 T& D; f5 I- k1 s3 X
addsub_rslt_i => s_addsub_rslt,
+ Y2 |% r, o6 n0 N( {7 Q addsub_cy_i => s_addsub_newcy,2 B& J @: J3 K% q5 v _
addsub_ov_i => s_addsub_ov,1 G' Q4 k3 Y% M# u. E
op_a_o => s_alu_op_a,, s- ] X% ~ u# q- q
op_b_o => s_alu_op_b,1 |- Y4 [! j8 [7 { P
alu_cmd_o => s_alu_cmd,
7 h0 s; k6 Q0 r' m+ |- y opa_o => s_addsub_opa,- N' ], w, k" K) H1 N
opb_o => s_addsub_opb,. U6 d5 o+ [. p, m+ A! V( C7 {( X6 H3 z
addsub_o => s_addsub,
; z. r6 A! ^- K4 ]9 K/ ~2 Q# R addsub_cy_o => s_addsub_cy,6 X, ~* H7 p& }+ f! s& R
dvdnd_o => s_dvdnd,
$ c' L* e/ z5 ]7 h! F2 z7 ~9 ] dvsor_o => s_dvsor,( o; c" I5 T' a; M& d
qutnt_i => s_qutnt,, a4 n* ]& \8 k8 o* w! ~
rmndr_i => s_rmndr,
0 g0 [& ^/ h6 c1 } mltplcnd_o => s_mltplcnd,2 a( x) [) Q" `' ~( y9 u
mltplctr_o => s_mltplctr,! P( E' |. e0 I# S) t& j' p! g1 p' \
product_i => s_product,
* [. g7 ] N5 p- u) m1 E dcml_data_o => s_dcml_data,! X6 y. ~3 l* ?- k5 n0 o$ O
dcml_data_i => s_dcml_rslt,6 b4 I% N. p# M( ^
dcml_cy_i => s_dcml_cy);
4 G7 W' ^% ?% j r6 s: ? i_alucore : alucore
- h1 s, l( Q9 r/ K0 d2 T generic map (7 H, D' m. ]4 E
DWIDTH => DWIDTH)
) B8 I7 Q2 ?% P1 M" G- a6 U port map (
' y% R$ [+ |8 ]# ` S, d op_a_i => s_alu_op_a,0 u+ _6 ?) h7 ~6 Z) L, U$ \
op_b_i => s_alu_op_b,
' m) _ D# p8 P+ j4 e4 c alu_cmd_i => s_alu_cmd,6 I7 }/ d9 D8 }8 t6 e: v
cy_i => cy_i,, A/ K/ M. B `" X- c! a. w1 q5 F) K
cy_o => s_alu_new_cy,
+ a& ~$ C! S7 o0 y. C( H5 N result_o => s_alu_result);4 Q4 L) L T& }1 [. y2 ?3 S
i_addsub_core : addsub_core* V7 k. r. M4 }, F7 m9 h
generic map (DWIDTH => DWIDTH)/ ?& B t+ [# `+ C9 j9 K
port map (opa_i => s_addsub_opa,
5 w7 i. ^- L" ?4 i$ I opb_i => s_addsub_opb,
* B" ?6 @) Z; M addsub_i => s_addsub,/ ~# }1 d+ R) W% n1 l* ?, B
cy_i => s_addsub_cy, o2 o+ {9 y1 d3 b+ f
cy_o => s_addsub_newcy,2 }& W1 ]8 _2 y" u7 G& }0 C
ov_o => s_addsub_ov,
7 Y: |! V0 c0 E4 ^ [4 p rslt_o => s_addsub_rslt);: Z c0 W% _; \, Z8 ^
gen_multiplier1 : if C_IMPL_MUL = 1 generate
) q8 l. @/ `7 f0 s- D/ e i_comb_mltplr : comb_mltplr
' s( G h' F4 g; m& G6 T generic map (
; b$ s4 }" W2 E9 f' q" S DWIDTH => DWIDTH)3 Y- W) {% k. S. A, T" C: b2 r
port map (
; w5 D6 v6 t- V7 q! @4 T, [+ m8 T mltplcnd_i => s_mltplcnd,
; v8 \4 V/ a' K2 Y3 H3 E mltplctr_i => s_mltplctr,
, ?! J! x h: n" H9 C; q product_o => s_product);
/ L9 L8 U; Q1 v" K5 y6 ` end generate gen_multiplier1;
7 I- o3 s A8 ] gen_multiplier0 : if C_IMPL_MUL /= 1 generate
/ B/ g: _1 c0 E s_product <= (others => '0');* F4 ?" t2 s! |' H: ?
end generate gen_multiplier0;2 K) F( L: C5 _9 g- d8 O6 r
gen_divider1 : if C_IMPL_DIV = 1 generate
$ {/ I" X9 R p h T/ o7 `/ z* ` i_comb_divider : comb_divider2 a8 o7 Z1 G3 ~: ~9 B
generic map (( A, Y8 d6 n4 h `6 R
DWIDTH => DWIDTH)
( z' ?0 k4 I2 J, `/ m' {. ]0 E port map (
' d. g9 ?3 k( ]0 r+ e" j dvdnd_i => s_dvdnd,
7 p, K W# j7 k. d dvsor_i => s_dvsor,5 ~1 i' n3 P+ E% \: ~% }) a. V! x; _
qutnt_o => s_qutnt,5 S4 {0 n: j; r; f' O X
rmndr_o => s_rmndr);8 u' F+ T+ [$ j% s% G) W6 w- F0 n
end generate gen_divider1; [7 `5 |$ z4 {1 |* w
gen_divider0 : if C_IMPL_DIV /= 1 generate
" n- L- M. c0 c* ?) w, M( e s_qutnt <= (others => '0');
. }/ x1 n2 |2 U6 k2 A) y s_rmndr <= (others => '0');( G+ [7 \0 D# V+ p2 N% l0 ]
end generate gen_divider0;
" Z3 F: z( p- o; T gen_dcml_adj1 : if C_IMPL_DA = 1 generate
T; Y5 i* T9 }5 J i_dcml_adjust : dcml_adjust
9 _9 e) Q9 m; p/ f' t- y generic map (
( I h5 Z8 {+ F) U; R ?- @ DWIDTH => DWIDTH)
& T( I; X5 ^+ z port map (
! k; A7 h! Y8 {$ \* `' g; K. a data_i => s_dcml_data,7 l8 K, I8 J! i) C
cy_i => cy_i,5 u, V3 x) T6 O. T$ v6 T
data_o => s_dcml_rslt,
) Y* p# ?! T/ K1 [ cy_o => s_dcml_cy);$ j3 q" Z+ k; d7 |: \2 ]
end generate gen_dcml_adj1;* N: h l! }; q& O) C f. t
gen_dcml_adj0 : if C_IMPL_DA /= 1 generate3 h& k# \$ e4 S3 ~
s_dcml_rslt <= (others => '0');
. p2 p: c" k/ P2 @- }3 | s_dcml_cy <= '0';$ H, ?4 w5 Z2 h6 _$ M
end generate gen_dcml_adj0;, `3 E# T' K( a. i7 F+ Z1 q
end struc; |
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