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DATE: 05-28-2016 HOTFIX VERSION: 0716 Q# y! z5 K- {+ _" B$ B9 S
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3 A; y* b9 E) M1 J7 j( i7 m/ w1452838 concept_HDL CORE Apparent discrepancy between Bus names and other nets( }. ?1 v: G& \
1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package
6 v3 b4 i. l* [9 h( E! H1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser' N5 r. N% S" D3 O# d" f1 u
1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly
1 ?4 I: Z( P' u p' n/ y. {1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.
3 j9 C, q) o( r. T# b( x1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.2 K8 A- D6 o: u- Y. O
1544675 allegro_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)/ @) H# H2 T5 H' S3 N4 I7 ^
1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set# u0 E# u: M+ Q/ D! e) D
1551934 ALLEGRO_EDITOR skill axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
) g, u, w2 m Z1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library
/ r) Y9 O4 ?. Y" y: L# P7 C' X1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG3 m* A f# A* M1 G- n, O
1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon
- W6 }9 u: i5 |& U. M- m1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets
3 d& A. p$ n% ?/ V1 u( X1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open5 m& J6 } ^/ u, q
1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters, f; P5 a e8 r9 e4 [
1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC0 P1 U4 I$ p0 O% ]( H$ m- t! v
1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins/ N3 N, [# T8 a: J, Q1 D4 T
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas
( J' I v* M$ F8 q2 I1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions
1 E9 U% y$ c, P9 I- T1 n5 {. x1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete; g' t0 Q% b0 u4 A( @. E
1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.1 `6 A7 n. j3 A
1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct: O# q' _" P3 Z% R) P5 [
1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window
1 r6 \% N3 b8 T1 s1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'5 L% z& U; q* t: n$ e2 \6 X( C
1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed
8 B& |: p1 |% I9 O5 a1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...9 w" v. n! E7 j5 O/ U3 m
1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager
* c' a$ F: ~( ^, U6 h i1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short
0 ~! i0 t) Q/ }9 T& Y% O1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property7 m6 ^- t/ h+ S7 o; q
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only0 V4 u, E* U6 n- @9 e% h' R4 `
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display; C- ? |: a- S3 w" J
1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET), e0 R5 e# R- k3 l% k% j+ z+ h! Q4 m0 r/ t
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file! o/ O4 c2 B! `6 x- y% P$ P2 P3 \
1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings
3 K4 U' ~) q6 B$ H! E3 K2 W1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'
0 r% d" A9 R a, S3 L2 W' j1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files
; h. {' W8 J$ a) C. y* q) c! g8 Q4 l2 m# X; s
DATE: 04-22-2016 HOTFIX VERSION: 0692 f5 [" B3 P7 ]
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CCRID PRODUCT PRODUCTLEVEL2 TITLE6 ^5 ?7 Z7 S+ ^
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1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output
k( _) a; F* N* f1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode7 i1 e0 u9 w/ q( r( A
1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail
4 e: M; o5 m: B6 M1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol+ r% Y, P- _" n7 b3 t
1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing2 x9 ^* N' V( D4 K- `" Z+ z
1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute5 j3 W, {" n: w: _4 F3 M, e
1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals
0 b7 J% ~5 D0 b7 `) x' W1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork
8 H* t0 F9 I8 @1 ~- x' }2 B9 T9 I) P+ n' q1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed: H9 j& m2 {+ Y) {% h# t% V, F
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
3 W) q1 x5 o& [* p1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work" Z& U% s6 M+ `' z
1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork
/ e* B% b5 P7 H- F1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message/ p3 m+ `9 {1 l3 u% R7 C# ]; J
1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point$ d! S: w' \9 b8 d
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines
% X6 \* ~/ t. s- l1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems* ?' t5 \' c% \! z' F
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro; h5 x; C0 ~7 X* k
1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups6 ~0 M$ ~# O. K7 m2 c
1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons# g# N7 ?. s+ ^9 y/ R1 v
1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes
2 x& ~$ _/ S( r; k4 O- m) {1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted0 f* c: Z! n6 ?$ h n- x) R
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die
- Q' w$ v8 s0 l1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM0 E+ x. c8 k' z6 h! o+ S* E
1562537 ALLEGRO_EDITOR mentor Mentor BS to Allegro 16.6 results in Fatal Error
& b$ e7 G3 T4 u5 ^3 p$ R4 O( M& V1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film./ S: }' s1 R* [5 ~# S
* q/ [2 S( c: o+ p7 c) _9 l& lDATE: 03-23-2016 HOTFIX VERSION: 068( `+ m$ P" i3 y; z& W' y: V/ H
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1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager3 y! {2 E6 z) o
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
& }7 T& r$ J3 t; {- Z2 h9 t1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license
6 |$ L5 x8 I9 w" a1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short
$ R: O: O7 ~' ~( j1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system* ^5 P( {, }4 k9 x4 B* L4 M
1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.* U$ d% A# h3 `$ D# x! j
1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol0 Q1 r# z, b( A, o# _! T
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file
& S4 A' c% B, i) l$ a6 g1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report& d, w9 J- ^& [8 L
1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'; e: c9 ?; r! n5 R
1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have ." H4 O; ^0 o0 X3 h
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts* m! T3 v8 ?1 v; Q8 d
1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols
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DATE: 03-11-2016 HOTFIX VERSION: 067
. ]- Q U9 G) B) h& Z===================================================================================================================================
; p% B7 R9 Q' t A( Y% bCCRID PRODUCT PRODUCTLEVEL2 TITLE! p: g# M0 d* r
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; [9 o& t+ e0 m6 R1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group7 D( c# s( q) j, {& @7 W( [ Q0 y
1484075 ALLEGRO_EDITOR pads_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines6 h% S3 o1 e Q9 N1 S
1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error
% ]) P& u8 n/ k; {4 ^1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
: Y- f; f9 G( S) {1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property
. \8 K* a$ e$ m6 v$ h' m1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net4 E* [/ @; m y$ t" j
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file4 }0 [( _5 L) u& B2 G+ t7 V0 Q
1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes
) s+ X/ G4 W3 D# D% b7 G/ y1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing1 s/ u" D7 b! W
1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager
+ c, { a h6 }# J$ b1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters
) P: g( @" C( ^* }1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties! H4 M" i; l/ C/ O! j( f" g+ k
1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer
3 x) M6 x7 A8 w% J1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
: [' N+ C% N, l* Y; }: I. N" g1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform
e8 O" h4 T" G2 Z$ Z1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
# {5 I# }& w0 z; s3 W2 |1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error$ _3 \7 W/ b' A7 A6 R4 C
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.. L! G6 Z) l: _1 ~+ A
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib
" J5 j" l4 E, Y0 m# p* v0 t7 S" {1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines( l% U& S- J: ]; i4 l
1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols
5 u* T6 r0 ]/ f# z6 j8 m- U1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board$ @% K, h+ W) E$ h: d P
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
8 t$ P: Z- ^+ c1 N. [) @$ j% h1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash
# }# P- u0 M' N2 V' s k9 k0 f% V1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked
* a3 A1 I0 u! _1 { n# U, ~) H/ P9 e1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.
! w0 Z- u6 u* R& B* g1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
! W/ O: n/ m2 l: V0 H5 @1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design- U& V% ^/ Z m8 m P
& E" I7 M( O% h1 b2 [3 A& BDATE: 02-26-2016 HOTFIX VERSION: 066
8 X' V6 w+ u0 }3 f' |===================================================================================================================================
# a8 [9 ~1 E8 q! |% [0 PCCRID PRODUCT PRODUCTLEVEL2 TITLE0 D9 m, [5 H# z9 y! w
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1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated
S$ b& c( V3 s. C d' [) A/ W# Q1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes- L2 Z; @! w% G
1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions' ]5 k/ _4 c( k
1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message
, Y q2 S; Z4 F( L% C; e/ A" B1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
- F) `! }2 W( o1 a) w) u1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue
' y# v& T; i) ?# K1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer) E$ J- s+ Z. z# T' M9 _
1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins4 U9 g/ ]. Q6 Z G
1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run- Q! E- X/ N- F3 j2 F/ S
1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed% s; W0 k! P! E0 |
0 L9 O2 f* n# l* [. c* `, yDATE: 02-12-2016 HOTFIX VERSION: 065$ M( P* @* y U1 t0 b" I
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( a N. i, D0 l, L+ ^1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
; Y* N. b. r8 p- d) t4 H- c1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via1 W% D, j; i4 `" v- N/ ^( p
1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit
7 J/ B, v: |) F9 u3 u. n- o1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.; h. W2 W5 P9 F: F+ F. }
1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms
5 k& l- L6 G4 Y0 o( i7 G& K1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine
. f' \: R) K" V) Z8 S x1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger8 e( \( x& C9 I9 x
1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design& x' q- ?/ P" w" z" a
1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup
; }% `) W _5 ~5 T& s, D1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license.
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DATE: 01-29-2016 HOTFIX VERSION: 0644 ]7 |0 b/ X: D, ?
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1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain9 d. U3 ~% e; d# u$ a6 c
1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF
" ]5 N; b& Y! N: C, P8 V. U' S1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.$ n0 h" q8 P6 m m
1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected
' z' T/ S Q4 S: R' d5 n6 y1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.4 v5 C# |" v3 w5 M _) f
1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default: Y" y1 p9 K i6 J& r& u
1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas+ S' m" g1 q% d! g t
1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net
+ M+ d0 G; F2 z" a2 [# [# n1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
5 a0 }. i( y# f5 F. W1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic7 c! ~' ?9 S1 _# V2 `3 T
1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor% d; t2 Z+ k- N$ [; @# k
1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file)9 Y% L( V/ c8 B
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design4 q: J8 {9 I* e. ]: Z7 i! k
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash' W' x) G9 Z6 R& e* n
1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes0 I' o& H% l/ `2 X( m! A
1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor
; C, r# t0 o {" ~/ W. ^, w1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct; e- v! R$ `5 u& U4 n, I& q1 ~5 _
1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in orcad PCB Editor' option in Hotfix 63
/ I! S, `7 {4 t- p. M1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes! a+ ?5 }' G2 _
; \$ }9 F& x" Z2 A$ f) c
DATE: 01-15-2016 HOTFIX VERSION: 063
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1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region; L% e$ t3 x! Q0 C M
1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs
5 _! Z) q' U8 d5 T/ R( y S& y1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs
, w4 T& y1 u/ i: I' ?; B* ^8 x1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant
8 {. W& U' R. H4 o% f0 z1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork5 t+ d7 S( p; x9 ?! @
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.66 c, l7 R9 I$ k4 d% f* W
1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance
( s K2 U# q. b3 @. y1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command. W* Y& l% a8 ?1 H' l# t
1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.
* f$ @$ \; y+ Q2 G1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out
) n/ s4 m6 w7 L+ M; K$ \: ^1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor7 T$ p a1 Y7 D1 K
1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property
U, j! `' l! @ _! Y1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly
/ A0 n4 f; u- ~8 Z1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation. `) t5 }' x2 c# D1 N
1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol
* v: @; v' [' Y0 H8 y% O1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'. q5 D/ S/ g/ ^" y+ i1 O
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes
. t& G* F9 w; Z& H' y1519518 CONCEPT_HDL OTHER Genview does not generate split symbols
% U8 ^* L9 v2 Q2 n5 N6 Q* q% H% y1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas/ _+ i+ L/ R# {1 o1 O9 {4 P& f
1520207 CONCEPT_HDL CORE Genview crashes after renaming ports
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DATE: 12-11-2015 HOTFIX VERSION: 0621 @4 ]1 z- u, J7 y- _
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# n1 p4 j% ~8 [4 D1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output
; c7 _- j! I8 I2 q3 V& [3 {1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
: f T' T( i! n0 o* K1 y1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option
0 |- v) [: M3 e8 j$ p1 ?1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC; a& L; Y: g1 C
1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view6 H* S& a* p& G" r v& T
1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked! f' \ r" {8 x! r, P7 S% k/ G7 J7 l
1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.% N# ^4 Z, d) b' G" w8 T
1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
0 T: U# m/ }6 {/ C( ~1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding$ ^0 A& z- r; T
1490311 SCM OTHER Block Packaging reports duplication when it should not
1 y( W4 C& V- O) q0 ^4 T1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'
2 b+ N% N& P& V' e+ y! t0 y1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message) n% j7 p9 O' j* ~$ j+ l
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)
% A* [+ A5 J9 i0 S1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit
' e1 W2 C! k7 @9 Z1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout
; J0 \% }7 @5 [0 r) Q1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )
$ U* H$ X2 A5 @: x2 m$ v1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types
: x5 @$ X) E. r: N1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'5 m/ I; ^! F0 O% y N1 N
1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly
6 Z7 Q" {' w. l! H n3 T, ?" v1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this
( p9 ]2 k2 c' @+ w1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch4 L/ h( M* [$ `' `
1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default
. ~: Z0 S& s: H& p. n: W1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts
4 C. {- N J( R1 m4 ]1 V9 d1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks; Z- J" ]& [3 J; H5 r
1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out
6 ]. Q( ^" G k1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF
" f2 |, Q c7 s' T1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form
5 K4 G' n2 ^3 @7 Z, l' f1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL& r3 l3 b5 q" h3 n8 C |
1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings8 b( f7 U2 K9 e! j! D. k% t! ^
1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location! P+ y9 S9 b4 ]* k$ k
1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized
) I6 h" ]7 u3 G- T1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary- T* N# e/ d# e
1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items
* h. }. t& [9 Y. U+ y7 \9 _1 P1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin8 ]- o, A$ i. `% o: Y
1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving/ J) @ L4 q& |& \. l
1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None/ l/ e, y# k* l( y! a2 o
' \0 t [* q3 r% b: q1 }. I/ Q) ODATE: 11-20-2015 HOTFIX VERSION: 061$ O( @) Z! f2 ]! P J |
===================================================================================================================================
5 z; t: F1 E+ qCCRID PRODUCT PRODUCTLEVEL2 TITLE
" Z. u6 a& M( [4 q===================================================================================================================================1 v% b7 o, X, G
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value4 V$ _1 q- w- L
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init8 L5 H9 P5 }1 ]- g( q. l
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only
5 K3 g; R) ^+ B5 x" H. ]' N1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle: {7 f N; J( O" L" e8 ~- O5 ~
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins8 s; H5 H4 K8 o; E4 k
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
6 K2 b4 U6 A0 A, {1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin5 A2 y( x" G5 k. R
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
' `4 ~# U: F) v7 c+ h2 S+ t1 B) j' m1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename, l8 T/ v7 q7 ?
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
" h* K+ O: p# h5 n1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL" { C* ]* p6 ~- M: O2 r0 t
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy( }" ?1 A) ?9 V7 N# K0 s
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
! ~5 g% D# I- ^$ x9 U& L1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets! l+ i4 N2 X4 `
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice
4 s5 B' c9 q( a" ^1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
# e( U1 D; Q: t4 S$ x; Y0 ?. n v1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
2 R& v' a+ @2 A" @3 Q1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project+ D* C/ M/ u5 ]& }- V. Z
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.
; a/ C }: Q5 A; X a3 {1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility
+ H; d/ G( P& c' Z9 w) W* {1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems1 i+ k- t) t' f
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported2 j1 {3 R) A" S6 M
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior
' |5 n9 U' ?. y+ ?; I1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
0 H) [3 z/ ~! m& v4 i. G N, k2 F: |1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
( r+ G( q! q8 y. a1490299 SCM OTHER ASA does not update revision properly
+ S7 l9 d9 E J5 j4 K+ \1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer7 P* _! \2 K4 m$ [
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
0 _* h( @9 e& P7 @1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working' b8 C- [6 m' Q ?) K
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong( M: A5 k% O* a' T9 }' O3 b2 Y
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash, }% }) E, r3 z& W! F
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL7 G" j# ~+ S7 D6 W
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581/ G" d0 t$ K8 v' d0 b
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size
9 B" ^' ^* r' H7 N8 i1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root' O! k( D# |2 U3 f8 l4 s
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file
2 T% L( T' |3 N1 r* X# y) O1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
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发表于 2016-6-29 12:21
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发表于 2016-8-17 13:05