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DATE: 05-28-2016 HOTFIX VERSION: 0712 B' M. T$ R& w% u3 W
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CCRID PRODUCT PRODUCTLEVEL2 TITLE# `2 n/ f! k$ d# P: ?6 H7 H8 a
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8 p7 C1 S/ \0 O* b' Q1452838 concept_HDL CORE Apparent discrepancy between Bus names and other nets
& U f0 B0 Z' y9 s; g2 z- Y0 o1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package" `8 V& F/ w, F$ L3 m
1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser! w5 R: V4 Q* C8 @
1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly
: I* _& E4 A" P- l1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.6 E$ ^$ D/ p6 z! e6 A& V- f' \
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.5 {* V6 E; z9 _2 n. \ q2 G& J7 ^
1544675 allegro_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)
5 R+ h2 |) e* B1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set
$ {- [; W( t( w' ?1551934 ALLEGRO_EDITOR skill axlBackDrill command is not analyzing new layer set when application mode is set to 'None'* x! W7 Y6 c9 G2 O: U
1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library, x2 z7 s) }3 L
1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG
( Q8 u C7 ]8 j/ @7 F9 I; C1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon o, r; @) p( _5 A& X! b% j
1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets
6 O) c8 u0 j; G+ N1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open7 u9 t" l% j; F; U- _
1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
( Y# D) i4 e5 \8 Z# [1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC9 Q' t" g/ C* i8 a. |9 P( P. S
1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins: W' U* j: }2 m2 a+ a: V
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas: I9 Q( X3 L! X9 [1 r, u7 L) O
1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions" ?3 w# z4 M2 j/ M4 D# P/ W# R
1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete
) J4 L' x; P# J' b) t1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.* H/ Y" B ]2 Z# P+ y
1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct! |7 a+ @/ Q2 w/ _+ i3 X& B
1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window
( E2 _. p4 o4 _* l1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'8 K" t s) m2 j2 z
1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed
, _4 m3 ~1 f6 R1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...
4 J3 B; f4 j/ b; ]% m* I! \1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager
# x$ i1 K/ } j4 p1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short6 n! p) K4 @& P
1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property
3 c& U, z! p( Y8 n$ V" I- C1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only4 {* z! L5 t5 J( l3 D& h
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display
( `2 S( e r2 e2 A1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)
: m. m" H9 r& y# W E c* v) X. M1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file
$ R, B6 r* i0 m u C$ u( M0 F0 d1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings
2 {/ l. z1 z) Z I6 V1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'- k2 M7 o/ J) q$ E/ _
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files
( s1 \% _& L" Q. ?, G; e
* l# Z8 x1 G! Y, IDATE: 04-22-2016 HOTFIX VERSION: 069
* J4 A/ P/ u& H0 l4 Y===================================================================================================================================
4 S" v8 T& }2 M6 t% `CCRID PRODUCT PRODUCTLEVEL2 TITLE# P( [/ f2 S8 q3 d* E
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1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output
l" f y+ v8 a1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode* O5 V2 F3 N& p6 N0 ?3 a# M
1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail
# O" N/ d- W `; q* G4 o/ z1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
6 P' Y6 q+ z: u" ?' e1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing2 L, h4 N9 V6 r2 H
1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute* s, K- o3 a; |' y) g* I
1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals$ x! h- s# w* X3 Q# E% I" ^
1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork( t0 h( R9 D& H/ }
1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed6 {. x* [. v4 f J
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
) ^+ F9 B# K: M9 E1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work
- B2 b2 W' i1 _0 [1 ?6 }1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork1 i4 B3 z- F; [! P, c: e
1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message. ?* k5 d8 X, Q& K
1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point' ^- z! y' x5 n6 G
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines$ j& G, F/ `3 Q
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems
, D7 x% j- J) p% V- C& u1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro
* Q3 R7 v4 x6 ?9 g! {3 B4 G# k. R1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups% @* C( G0 }5 o4 D& y" g+ e% L& R
1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons* h! s9 B" q. C2 w4 J) Y
1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes- A D+ t+ K6 Z3 |& g8 |2 u
1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted, @% D/ @( i- R. U. u1 h9 U! n
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die
0 H B6 p# d8 v, S5 Q4 p, t1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM
9 U5 e l. d: @: s" |2 b# Z/ n1562537 ALLEGRO_EDITOR mentor Mentor BS to Allegro 16.6 results in Fatal Error/ S1 N& y" X& D4 w" M7 E6 z m
1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.6 ~0 N) ~$ j# I% U# O& ]
% e& v2 H7 L5 W& V! }DATE: 03-23-2016 HOTFIX VERSION: 068$ u! s( s/ ]4 `/ N1 O1 X6 K7 P
===================================================================================================================================
% M. g( Z, A L* {( kCCRID PRODUCT PRODUCTLEVEL2 TITLE& E5 h7 c. p. v7 A8 m' {' a3 {
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1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager; R" T4 ^6 E2 B0 \3 S
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
5 a* b5 @+ b u" C1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license3 b: d: Y; X! j: V* s
1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short: j& @, H! q! A e; m5 n
1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system
6 a; }# _8 {" O6 Z& h. [* J; K/ I1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.
3 {+ Y" ~8 p+ j% j) ~" A! }/ |1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol Y% N' ~2 r) [* |2 W
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file1 Z- s2 s! M) B5 \$ ~
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report
# ~# a: f+ p* B P2 c6 k) R1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'5 L: H: y/ D7 v" Y' s% l `
1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have .& A: z/ r% _1 }8 E; x
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts
! S" S# z# B+ E1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols
2 P" _- e' P9 P/ Z* n" |
- Q# ^/ g$ v* n/ `" ZDATE: 03-11-2016 HOTFIX VERSION: 067
) @- O7 u9 q6 A! x, [8 \===================================================================================================================================6 G+ ]- L% ?+ l& P$ p
CCRID PRODUCT PRODUCTLEVEL2 TITLE3 E# r1 X; j# M% a
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1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group/ M" X4 A& E: A' T- E N
1484075 ALLEGRO_EDITOR pads_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
0 a/ z, g# }3 b7 K7 Y1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error$ U/ g5 y& |# {8 o+ Z
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
& {! O% x/ k3 D! v* o" e1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property$ O7 ~ f V+ i0 O0 F+ U u
1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net
: P/ u9 d# u! i# {6 d4 D8 w* j1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file1 Y" p' e1 C) y6 z5 S! M
1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes
. Q2 ^ f5 g2 X% d: H! I1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing
; |0 J, f4 ?( V/ m8 A* s g2 V1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager4 ]( U0 \8 a5 l/ A
1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters t6 V$ p, G* ^4 P, V) ?* P6 s
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties% q: F# }8 p6 ^( k7 A
1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer1 D2 s. ^+ t6 o
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net1 v& x: m( g9 T. X- `) d1 s. f; N* z
1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform/ v# d, m w. V8 \3 P
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
2 P) B7 P, N& W' l1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error. g* }8 t! x5 q2 V) `: `
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.
, Y: o( [( S& W) U1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib+ ]0 {0 s C7 |* C
1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines* |$ `% ?) e; U
1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols
3 P# z, ~% c9 E9 @8 h' d! z1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board
( W+ H X/ N: N4 \! R" y6 e1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
8 Q) v# k4 B# j( a5 c1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash2 i9 e: N3 l8 Y
1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked
5 P9 R! @4 f6 R+ g2 [$ ~* j1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.
7 c2 x z6 b4 B! ]1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
! ]% q/ c$ B+ M9 `$ I3 i3 L1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design
- `6 U; q, A6 W" r [4 U4 \ I
0 I& d6 b2 Q9 h" h* \! v9 i! CDATE: 02-26-2016 HOTFIX VERSION: 066
, v* c% x$ U4 w: X4 o g===================================================================================================================================- T% u! L; e0 f% ^: U
CCRID PRODUCT PRODUCTLEVEL2 TITLE/ X- w, D" U2 y8 v" r& h. o6 F
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8 F$ s& N6 i! g1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated
; `+ T" W7 \: ~ K) J1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes
% S, M" D* z( S. c: w1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions% _7 _; B' S7 B$ v3 m2 e a
1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message
$ I+ c$ T7 }, p q1 N1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
) G7 f& ]# @" Y$ B) \1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue
; V# u5 R2 b' c( @" n/ s1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer
x; v! ]% @( p' q O4 A1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins K( ]3 i, U: P/ t- R- c9 X
1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run4 N( F% y1 d, M' n5 V4 h
1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed- H& m {' ~, B2 _8 L$ `2 n2 w
6 ?. f1 i5 X) j; g5 i4 a
DATE: 02-12-2016 HOTFIX VERSION: 065
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
0 v' ~2 r+ I( k! Q6 d) t. ~===================================================================================================================================) y/ \' f0 r' l& T6 l
1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
* s3 G& Q- D) h, i7 H* ~; q5 s! f1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
R1 [) v; M, T; T. [1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit
- b8 L0 E& O* Y8 L1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.
7 U! h3 e. j" S0 @1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms
1 D* c2 n" S+ o( A/ P4 {4 o4 S2 F. j1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine
; t. c4 b; B4 t `! M9 g, b/ b5 V/ g2 T& p1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger' I5 p, b5 Z% N4 K% C# w
1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design1 i( ]' i" }6 ~1 _' h: J$ A
1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup5 J8 [/ C8 s4 r( t9 Y: k p
1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license.
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DATE: 01-29-2016 HOTFIX VERSION: 064, |& {6 ^5 Y$ B- a8 h
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6 [$ q3 v3 P8 c" ~( x1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain3 ~* ?. A b6 k" C4 ^2 |
1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF! G& x! F; V+ N* x
1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.
7 d# g& Y: o9 k! B, ~2 a1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected
% |' u) A) v% x% H2 o1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.
$ N/ N# u1 d) z: l1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
; x7 M9 I% e. l0 {" R5 G1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas" v4 Z* B2 s3 a" e/ ]- f
1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net1 b* u) x) P- x- A
1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
! |% d1 i3 E& N1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
3 ]# @+ ^5 e& P1 X& Y: z& S1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor
% j# X. w( \5 `' w( ^6 ~& O0 T1 R1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file)6 H& `& v% J9 M% r
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design
1 P# Z) o8 g. A0 `1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash9 H+ s) F5 x9 J! n8 K8 x! [: x
1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes
8 v& B& u# @* {6 ]0 R0 B1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor
1 s6 o5 [& q2 ^# T/ K8 \, U1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
5 k' _+ \. i+ ?: y C% p7 B. T" X* O1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in orcad PCB Editor' option in Hotfix 63$ K6 M$ s5 i2 R) ^# s0 V! J+ n
1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes
$ ^4 U* B! Q5 x9 n* @" l2 n* U, Y) |: H s7 f j9 U+ y5 ^+ H
DATE: 01-15-2016 HOTFIX VERSION: 063
4 O) h3 d! Q/ J- X===================================================================================================================================# J2 f0 f7 t$ U1 m( K) P" B3 v
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1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region
! n1 k r" d5 @2 }1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs
5 }* L- }1 V3 {+ W! G/ j. y) G: c1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs
- S, T+ y* ~) f j- ], I; F% g" j9 R1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant# w; A8 Y- }. R0 y' E3 n, v9 _
1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork4 V, e1 g1 k0 v
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6' s6 g* M2 o& q- w5 |) S3 V T/ x
1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance
* m2 X3 J$ `$ J- u4 S1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.
4 \4 G. @3 U; b& i# i* i5 Y1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.4 Q8 F4 D& ?% k& ^
1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out
" @" i2 R" V9 k/ d# b: E3 k1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor8 Z5 g( L% Y* v; O3 U9 y
1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property
5 E3 t+ Z- |/ N1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly% W0 Y3 Z( G* w% x% q6 n
1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation% u% `- S3 U* _ m
1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol* X3 `; D6 C) e, x; B
1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'
( U+ }: d' H( I3 r. W1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes3 U- c6 L! f) C% t' B' F, {
1519518 CONCEPT_HDL OTHER Genview does not generate split symbols- {' B% x& ^9 n
1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas
% z' e! v9 W. y3 k7 B# n' N1520207 CONCEPT_HDL CORE Genview crashes after renaming ports
# [- r% g% _- C/ A
; `" i, L- U- I# v: S- HDATE: 12-11-2015 HOTFIX VERSION: 062
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CCRID PRODUCT PRODUCTLEVEL2 TITLE8 K7 |4 x! k9 D
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1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output9 f, m& c+ Q% j8 B6 d! q9 o
1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
4 V k, F3 @1 `& Z4 A8 A1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option
0 U" B: j+ F+ z' M- [/ S1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC* K2 M: n( m. E$ a: O! Y( B
1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view5 v+ W; c; m4 E& r! ^* V& k
1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked; {& y: t- X, n1 j9 M& Y
1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.
- {+ Q, U" m/ [8 f9 `" r1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
- l7 [4 V& [0 R# u' Q* m8 H1 g! b1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding
, j3 b0 s3 @# ~2 U' |1490311 SCM OTHER Block Packaging reports duplication when it should not3 Q/ j% v0 t' D4 v- A1 F1 q
1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'
, M/ C/ M+ S2 }- n9 a- Q% Y$ d1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message1 T6 j4 h( K3 n. {
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)
, P* T8 `7 \! y! O1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit5 j! w& ~) D# d3 K3 i0 u: g
1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout
# _7 X F0 W. K( d. g/ `, r% A1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )
* v, I5 X6 K, s" l7 `8 ^1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types5 F* {2 Q2 H! m/ M
1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'
, S; c' i; l8 x" {1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly' \' v3 e/ W, M4 a
1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this3 n1 ^7 m8 T2 G: A
1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
: x0 s- q6 E" ]! Y1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default( n8 g1 R( g/ \) N% d
1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts a& I9 D# s' b n
1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks" g0 n5 c: V) h. r$ u5 F5 q
1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out+ }% a! k! Q/ k( S# C9 \8 r! [
1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF
6 ^5 v5 R/ K% c8 u9 H% ` T1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form6 N# T9 o& t/ y' O
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
$ X2 Z" {7 F) T7 D) K1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings1 v7 F6 b: Z/ Y3 d
1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location
9 s. T! S9 j7 M+ \, U1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized% q4 K l8 P# \# @8 R
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
6 ?' P G) y4 ?# N6 n0 `1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items- P% L1 l8 U* G9 u* X* \1 ^
1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin
! q# g) M; M; S, Q; X% {6 w' P1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving" c* O' M$ v9 i
1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None
- S. V7 D; R$ _* f0 {. t1 v/ d% j0 b: h
DATE: 11-20-2015 HOTFIX VERSION: 061
+ N- y# m/ l% e" S7 u! `===================================================================================================================================
0 D: N g& U& v1 P! t3 SCCRID PRODUCT PRODUCTLEVEL2 TITLE
! x3 ~9 C3 B$ [2 o4 Q9 Z; U===================================================================================================================================
4 _3 U1 ~- g, v# h3 t1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value. c6 s6 N" Y' _ q( o
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init
! I# y. l; [6 _+ J1 y: Y7 P2 z1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only2 j! R) F3 f% x2 Y, F! i# D& t
1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle* y2 J& f8 \1 }0 r$ z. z' D
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins' q; E/ Q6 i) A2 I" ^6 i
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set/ g) q) g; s. O9 t1 g! C
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin6 Y1 D, J: R9 X. }8 W4 {( s L( D N
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools# q1 Q" A, J8 ?6 `' Z# D$ ~
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename7 u" _" C7 K$ `
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets: I8 _; L/ v P* ~
1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL+ q. p* D b Y5 v) ]
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
$ b( [1 m3 D0 f. ]/ S4 T5 F* v1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
1 }. s! I6 O" b- ~1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets' j# V5 n4 b7 B' q
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice! s: I5 \/ S" U$ k6 z! K
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues: h5 u$ B. D& b
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
1 D7 V2 O X( A# D1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project7 J# I+ I' r7 U. x
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.2 J0 [! X* j% o, \3 h
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility' ]: l% n5 M% a9 _
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems! [5 _2 c" @1 V. q6 [7 y1 x
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported; y' B: d8 b; ~5 L1 O; `
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior& V" a- k! V* l9 V" d
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board% P( D) X+ E2 H: {7 k4 I
1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
4 f* A( l& s+ h( e) n1490299 SCM OTHER ASA does not update revision properly7 B1 d- s# H8 P9 [! F: I# L
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer
' c" d$ D+ M3 p8 J% q$ t1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
7 l" ]9 `" _! E; ?# J2 |7 o1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
/ R; b# O1 n9 F& j' c& Q1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong) m) V2 U7 \2 e- k, q
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash
# n& a {! n3 H# o- E a; f+ u, P3 W1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL7 \6 c1 h- _6 C, r1 U' z3 e& Y5 J
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581
- l, O \6 P1 N" h0 k" @7 C1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size
$ R+ U" }+ v2 q( P1 B2 \1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root: b9 M* p" {. d3 t* D, \1 Y
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file# d9 ]) y* y4 P/ {1 }8 H
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
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发表于 2016-6-29 12:21
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发表于 2016-8-17 13:05