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SPB 16.6 從061到071版的補丁內容

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发表于 2016-6-29 12:21 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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DATE: 05-28-2016   HOTFIX VERSION: 0714 M, d# M& @, d/ K4 U
===================================================================================================================================
, C; ~6 n% A' K& ~CCRID   PRODUCT        PRODUCTLEVEL2   TITLE# v' e2 a5 {$ J/ W6 Q
===================================================================================================================================
! l0 E# W# B2 G5 ^3 s1452838 concept_HDL    CORE             Apparent discrepancy between Bus names and other nets! i. s3 }. o. x! _+ B. w# a* Y2 ]
1469146 ADW            LRM              ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package: A1 A# Y. v7 X& @( C8 L4 G0 w
1499515 ADW            COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser+ l1 S6 M' z/ q% J9 |
1524947 SIG_INTEGRITY  SIGNOISE         SI Base, PCB SI: Custom Stimulus is not recognized correctly% ]' e9 Z' w) H: {" p( B0 f
1532162 CONCEPT_HDL    CORE             The Rename Signal command does not update split symbols.+ T  g( t" I+ X( y# S
1543997 CONSTRAINT_MGR OTHER            Import Logic is overwriting the constraints in attached design.
$ |7 ~1 }! E2 `. A2 M1544675 allegro_EDITOR OTHER            Export libraries corrupts symbols if paths do not include the current directory (.)
( N4 i$ O& \6 ]8 q1549097 CONSTRAINT_MGR XNET_DIFFPAIR    Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set0 N9 l: d5 o2 B6 V/ _
1551934 ALLEGRO_EDITOR skill            axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
# t. D' K- L6 V* O1554919 ADW            LRM              LRM does not find PTF data for cell 'res' in the reference library: E. o8 [* i& }
1555009 CONCEPT_HDL    INTERFACE_DESIGN Not possible to rename NG
5 G1 I$ Q" B+ B" H/ [* {1557542 ALLEGRO_EDITOR OTHER            DXF export creates strange result for donut-shaped polygon
; u: @* i4 b0 L* B0 v1559136 ALLEGRO_EDITOR EDIT_ETCH        Cannot connect floating clines to vias with nets! F% V8 {3 s* I3 [% k' K
1560301 CONCEPT_HDL    CORE             DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
( l" B/ R5 M0 U1560804 ALLEGRO_EDITOR OTHER            Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters, v% D  \# D6 I1 S! i5 L) u* _( u; D( w
1564036 CONCEPT_HDL    CORE             User-defined custom variables are not getting populated in the TOC
0 f0 |+ U0 C* Q. P7 }3 d: S; H! `1564545 CONCEPT_HDL    OTHER            Signal model property deleted from an instance is not deleted from the instance pins  G1 A) F* C, R. G
1564552 CONCEPT_HDL    CORE             Find Net should zoom to the nets on schematic canvas3 R: e: B& A9 {4 o
1566119 CONCEPT_HDL    CORE             Right-clicking the schematic to add a component does not show all the schematic symbol versions- U, Z  s$ c6 e$ M0 b* t
1566848 ALLEGRO_EDITOR ARTWORK          Board Outline artwork is incomplete
3 f( ~* R: P3 I1567290 ALLEGRO_EDITOR MANUFACT         Import Artwork fails to import a shape.0 m) K: n* F2 s. ?: `# `# f
1567587 ALLEGRO_EDITOR MANUFACT         Extended tool name in header of drill file is not correct3 x& P/ U' O! O9 l; Y
1569056 CONCEPT_HDL    CORE             Opening New Cascaded Window Causes Graphics Artifacts on Old Window+ m. F6 o/ r$ n
1569087 ALLEGRO_EDITOR DRC_CONSTR       Running DRC Update gives the message  'Figure outside of drawing extents. Cannot continue.'2 b. M1 k  G) K6 l% ^. k& _% d
1569147 CONCEPT_HDL    CORE             Signal Name AutoComplete Drop Down List Not Correctly Displayed
; _0 D. Z7 P1 x0 h3 }1569924 CONCEPT_HDL    CHECKPLUS        ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...1 n" j1 \% R" G* P! P
1570419 CONSTRAINT_MGR CONCEPT_HDL      How do I add a customized worksheet custom property weblink in Constraint Manager9 E& s( x/ C$ s9 u3 B5 r
1570624 APD            ARTWORK          Artwork file has missing voids on a layer and is causing a short3 }. ~6 N$ h3 f. u) w! `
1570678 F2B            DESIGNVARI       Variant Editor error when adding an RSTATE property) j$ x9 O, y& @& N; {2 \+ ]! x! p
1571113 CONSTRAINT_MGR DATABASE         Reports generated from cmDiffUtility show the differences in mm units only
2 A/ p' J# r1 M& g1572593 ALLEGRO_EDITOR ARTWORK          ARTWORK: 'Draw holes only' option does not match display0 ^8 g% R2 H& Q. P7 f9 d9 q$ |8 O
1573205 CONCEPT_HDL    CORE             dsreportgen is unable to resolve the physical net names (PHYSNET)9 P$ z" ~# ~, l0 L
1573970 CONCEPT_HDL    ARCHIVER         archcore fails to archive the <project CPM>.arch file$ T2 p7 N" g' |- e
1574381 CONCEPT_HDL    OTHER            Packager crashes with some advanced settings( ?3 y2 M' @+ F7 U1 h' z- E
1576100 ALLEGRO_EDITOR SYMBOL           Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'( t1 s( y- t9 ~; g) w/ U, }
1580103 ALLEGRO_EDITOR DATABASE         dbstat of 16.6 does not recognize 17.X files
6 \1 l: @- J/ n! @  H4 O) P/ t
4 w; d; D/ R- T2 z" tDATE: 04-22-2016   HOTFIX VERSION: 069
2 R' m; `7 D  J===================================================================================================================================8 ~$ r' P3 f; f
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
# {) y3 q2 A: J4 y  C) V===================================================================================================================================
0 k2 }; h8 M6 t- E% H1272355 F2B            DESIGNVARI       Property changes on replaced component shows incorrect result in BOM output  ~+ u0 F9 l) r4 W# F& Y" ~
1483136 ADW            COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode
# m0 ~7 x- b6 n& Y  k1488909 ALLEGRO_EDITOR DRC_CONSTR       Test Via causes net scheduling verification to fail+ x6 Q3 D, A+ A
1498389 SIP_LAYOUT     DIE_GENERATOR    Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
4 ^4 y! d: v9 k. b" s2 B2 _- s1506672 ALLEGRO_EDITOR INTERACTIV       Replicate Place - Shapes are missing6 q: I2 H9 t- g6 i
1523532 F2B            PACKAGERXL       Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute
' Z) a) X4 q& E! K* y. m0 A2 H% }1525783 CONCEPT_HDL    CORE             \BASE scope does not work for SYNONYMed global signals
% P. {$ l9 d. q  k2 @6 Z' |0 I2 Y1529846 ALLEGRO_EDITOR SHAPE            Some shapes are not generated in the artwork
) ~- J0 D9 K- u1537499 CONCEPT_HDL    CORE             Adding the same version (already placed) with the same split block name should not be allowed) D( d/ i: G& ]0 ]
1542334 CONCEPT_HDL    CREFER           creferhdl leaving lock files in sch_1 folder; Y5 I  Y% c* W4 p: t: e* h8 j
1543410 ADW            LRM              LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work
+ _: I7 y: l, \: O8 C1546141 ALLEGRO_EDITOR SHAPE            Shapes missing from Artwork
# h, I* Y: i+ c. l  H6 }* {1546877 CONCEPT_HDL    CORE             Align Left on Wires Fails With Incorrect Error Message
2 ~$ M. I$ e- q& V" y1 w) I1548953 CONCEPT_HDL    CORE             Genview generates a symbol with strange graphics - lines going to a single point
2 H$ B3 ^: M& D& z8 o( I" r1548978 ALLEGRO_EDITOR MANUFACT         Shape not voiding clines
/ B( |) c6 h  \1 S3 Q5 h3 o1550941 PCB_LIBRARIAN  PTF_EDITOR       PDV Part Table Editor new column sorting causing problems
* g! H) u* S  u3 n1553950 ALLEGRO_EDITOR SKILL            Executing axlUIControl('pixel2UserUnits) crashes Allegro1 S, e8 h& }- p5 l
1554333 CONCEPT_HDL    CORE             Changed connectivity error when aligning ports attached to netgroups) P6 \2 \/ Q1 A# v; l
1555092 SIP_LAYOUT     DEGASSING        Degass offset is not working with hexagons
) h% Y, j* o1 o% }8 I/ U$ L1556261 ALLEGRO_EDITOR DATABASE         Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes: I$ M& l8 R$ B
1557716 APD            OTHER            Stream out fails with request to terminate detected - Program aborted3 z3 y) S5 G8 B
1559951 SIP_LAYOUT     SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die% @+ ^8 n6 ]* ?$ |/ _- A9 ^4 q
1560197 CONCEPT_HDL    CORE             bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM4 m3 L$ ?" Y: W* j# p( I! r
1562537 ALLEGRO_EDITOR mentor           Mentor BS to Allegro 16.6 results in Fatal Error
6 g5 C1 g7 I. W* `6 F1564203 ALLEGRO_EDITOR ARTWORK          ARTWORK : Can't generate negative film./ r. ]0 N! X: W$ {  \
: h" F3 Y, ]- d; H9 K; {
DATE: 03-23-2016   HOTFIX VERSION: 0688 a% w$ s+ O6 U, {/ C; C/ x3 s; u
===================================================================================================================================9 l. b/ _3 C( m0 b
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE8 {1 t8 B' J. E% D
===================================================================================================================================' c0 l2 s! ~: Y2 d/ ^$ c& R3 o
1522411 FLOWS          PROJMGR          License selection should persist on invoking Layout from Project Manager# @" o9 a% ^0 m( {
1544614 ALLEGRO_EDITOR SKILL            Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
% j$ g& {, D2 o1545909 ALLEGRO_EDITOR UI_FORMS         Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license7 r" Z; K- A  c4 H9 U4 W5 S2 ?
1546842 ALLEGRO_EDITOR OTHER            Unsupported characters: Not being reported by 'netrev' and causing nets to short2 G: ], a; @% o2 Y9 C5 X
1547224 CONCEPT_HDL    CORE             Lock the 'PATH' property once it is assigned by system; D7 v6 @: X; q& a
1547584 SIP_LAYOUT     OTHER            SiP - Design Variant - delete embedded layer if not selected.
6 V& Q, h! R+ b+ \% d7 s1548116 CONCEPT_HDL    CORE             Some versions of Technology Independent Library do not appear when adding a symbol) l& E: `, g' D* r4 v
1548151 ALLEGRO_EDITOR INTERFACES       Exporting a step file gives a component rotation mismatch in the *.stp file
& L2 U' d% E. ?1 t1 p* Q, h1548421 F2B            BOM              Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report
" c' j) t5 Y0 C# r+ K4 k% |1549105 APD            OTHER            'Stream out' fails with message: 'Request to terminate detected. Program aborted'
. a' s1 I8 m1 y! o% o- t1549662 ALLEGRO_EDITOR OTHER            Import parameters fails if your parampath does not have .# P+ L$ \" m; F4 j% B
1549836 CONCEPT_HDL    CORE             Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts1 R, Z  z6 d% ?! q6 r7 p, n( I
1550052 ALLEGRO_EDITOR PLACEMENT        PCB Editor crashes when copying symbols* Q6 D) }2 B1 o, n# ^

; ?4 l/ \, u* EDATE: 03-11-2016   HOTFIX VERSION: 0674 u% K; O- d2 N+ d$ h
===================================================================================================================================
. ~2 w. r! P1 N/ J5 `1 bCCRID   PRODUCT        PRODUCTLEVEL2   TITLE) X* Q$ S  o6 D3 k9 j8 r# L6 R
===================================================================================================================================
6 b5 _; o3 v% A+ f+ B1482953 ALLEGRO_EDITOR DATABASE         Part change disassociates parts from Group
0 @0 w6 D% v2 ]9 O% L1484075 ALLEGRO_EDITOR pads_IN          'pads_in' imports ASSEMBLY_TOP  and PLACE_BOUND_TOP outlines that are defined as shapes as lines
. b; {) T1 [0 \! O/ ]. f1519155 ALLEGRO_EDITOR OTHER            IPC-2581-B Negative Plane Error: M5 i5 G" m2 R2 Y1 |( I
1528075 CONCEPT_HDL    OTHER            Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'8 i6 }/ z, N& t9 p4 A6 l/ v
1528398 ALLEGRO_EDITOR SCHEM_FTB        Problem with pin number format used in NC property5 v: ]  l9 ?  o2 V7 K
1529178 SIG_EXPLORER   OTHER            Values not transferred correctly for PinPairs when created ECSET from a net
1 x6 j  J% x( j* J; N" R8 w4 Z9 G) `1529720 CONCEPT_HDL    COPY_PROJECT     Running ADW copy project does not update the 'master.tag' file0 \6 S* [% |7 W' ]  C
1530707 CONCEPT_HDL    CORE             Request to recover a 16.6 design after DE-HDL crashes
2 F+ [, k+ ^4 _/ I7 P1532124 CONSTRAINT_MGR SCM              'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing
  ^6 J5 s7 r  L2 r( y' i" v5 @6 f1532788 CONSTRAINT_MGR OTHER            Pin pair is hidden when Highlight Filter is ON in Constraint Manager$ m8 ^* c* U  e
1536912 CONCEPT_HDL    CORE             Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters
: h" r" B5 t+ {% ?7 m4 I& N8 c1537055 CONCEPT_HDL    CHECKPLUS        Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties2 b6 L8 M- }- J% S% f% d/ I
1537278 SIG_EXPLORER   SIMULATION       SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer% R) i6 d; E; e& s( w; k6 {
1537339 CONCEPT_HDL    INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
0 s- U* L" G$ y# ~3 N/ Q2 I1537521 FLOWS          PROJMGR          Do not allow project creation if there are spaces in directory or file names on the Linux platform
& d% i1 A) O$ v% d- _1539227 CONCEPT_HDL    CORE             Renaming a page from the hierarchy browser crashes the schematic editor.2 l% G2 T3 Y* `' B* `
1541532 SCM            SCHGEN           Generate Schematics crashes with 'Out of Memory' error
& G  w- r6 ?2 Z1541589 ALLEGRO_EDITOR INTERFACES       STEP model incorrectly shown in 3D viewer. Shows pins as angled.  z" |' t8 [5 _
1541680 CONCEPT_HDL    DOC              A dot (.) or period in design name created 2 separate design folders in worklib
- D4 T( e3 d: `2 _) C) D1541687 ALLEGRO_EDITOR PADS_IN          PADS closed polygons are imported as lines& |# K5 @+ E) T4 P% F6 w2 x$ k
1542722 ALLEGRO_EDITOR INTERFACES       IDX export: RefDes and PART_NUMBER missing for mechanical symbols  V1 {( {, e! a7 C
1542817 ALLEGRO_EDITOR DATABASE         Import Netlist not getting completed on specific board
9 u! L1 m* m- r) _" P2 E8 @, z, i1544060 SCM            SCHGEN           Generate Schematics causes Allegro System Architect to crash
3 t( x& N$ R! s+ D, A* O1544633 APD            STREAM_IF        The 'stream out' command causes Allegro Package Designer to crash$ [' M$ L: G- L0 }
1544698 ALLEGRO_EDITOR PLACEMENT        'place replicate' does not add clines and vias to fanouts if fanouts are marked8 v- W6 \$ F5 G* J
1544859 APD            PARTITION        Timing vision menu is missing in APD/SIP partitions.
/ p3 H' n+ {  c* h: n' s1545136 ALLEGRO_EDITOR PLACEMENT        All fanouts are marked as part of one symbol instead of the symbols they attached with' j# S7 u3 V5 F
1545370 APD            OTHER            Pads in .mdd file getting placed on different layers as compared to the design
. U+ R- j4 `, w9 j9 ?! }- p: l6 y& y6 P9 A  i. [
DATE: 02-26-2016   HOTFIX VERSION: 0660 t) k# @0 D: `, l  }
===================================================================================================================================: z; W; K$ g. h; X' ^# B
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE6 |5 R6 g$ h( D. q1 e
===================================================================================================================================
* P2 g# x0 }$ A3 c) R& D. T0 u1523426 ALLEGRO_EDITOR DRC_CONSTR       Dynamic shape not adjusted based on keepout; DRC generated- K( ^* M8 A! _" V" y  b
1526729 SPIF           OTHER            Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes* W% w2 S/ q# w4 a  w
1529209 CONCEPT_HDL    CORE             When adding a component symbol version, the More option does not show all the versions6 R8 @- h: Y' W. `
1530888 ALLEGRO_EDITOR INTERFACES       IPC2581 does not generate production files and fails with a segmentation fault message
" K, @2 k# u# ]. e1532865 CONCEPT_HDL    CHECKPLUS        Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
- Q- i. J6 t( U' \; X- a1536273 CONSTRAINT_MGR CONCEPT_HDL      Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue
- F$ o% ^! y; N3 \$ _7 m7 h( V( ~5 J1538343 APD            OTHER            Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer
+ u' E6 ]; q8 n, P7 [1 i. b; P1539077 ALLEGRO_EDITOR SYMBOL           PCB Editor crashes when choosing Layout > Renumber Pins
, k/ }$ _) F' e' C1539997 ALLEGRO_EDITOR SKILL            PCB Editor crashes when the axlStringRemoveSpaces() command is run) C. @& U5 A8 u+ `0 e' p: [3 n
1541445 APD            DIE_EDITOR       There are two Recent Designs submenus in the APD Symbol Editor; one should be removed! P9 Z. y6 j: W; V$ u- N

( f- R" O6 d' v% g& xDATE: 02-12-2016   HOTFIX VERSION: 065* T2 F1 ~1 n& l
===================================================================================================================================2 j) Z4 I, c; ^( k, ~
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
, Y7 J1 X, n: \9 l' K===================================================================================================================================
! L1 K; p0 S) P2 N0 O9 T1511947 ADW            DSN_MIGRATION    Command line arguments of the 'designmigration' command are not working
5 v  X( n- C7 ^; Q1517388 ALLEGRO_EDITOR SHAPE            DRC error reported as PCB Editor fails to read the void for a via  r- D% N! {8 R6 a* e
1521661 ALLEGRO_EDITOR PLACEMENT        'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit8 C- }. y" a; I+ s' d
1522831 APD            OTHER            axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.
; c0 K5 T2 k$ J" v; J  U  C" Q1 ?! ]3 R1524773 SIG_INTEGRITY  SIMULATION       Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms6 R" k9 T1 \: i1 z5 |
1524875 F2B            PACKAGERXL       Packaging using csnetlister fails, while manual packaging of individual blocks works fine4 @1 S7 a. h$ M( C7 k$ [% p
1527785 SIP_LAYOUT     WIREBOND         SiP Layout stops responding when adding a wire to an existing finger- H5 L* s* T$ A% \
1528479 ADW            LRM              LRM crashes when opened on a lower-level block in a hierarchical design5 D4 h$ w1 j- ]  }. @: b0 [' n
1531425 CONCEPT_HDL    CORE             DE-HDL crashing while trying to add a NetGroup
8 }5 `* ]! M: ^( [; Y# T7 ]' l1532722 ALLEGRO_EDITOR NC               Backdrill NCDrill files not getting created with PA3100 license.
+ F9 {4 h2 G3 y
1 A, U  O( X8 O/ Q5 w% FDATE: 01-29-2016   HOTFIX VERSION: 064! S! {; d' M: Q# a. ?- V* ^3 m9 S
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CCRID   PRODUCT        PRODUCTLEVEL2   TITLE$ E; k( _0 w8 d8 F. V
===================================================================================================================================
  q7 h' ?5 ^' e1510387 FSP            EXTERNAL_PORTS   Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
0 U. M" d  {: W. D. N- i7 ]/ L1514132 ALLEGRO_EDITOR INTERFACES       Element position changes after importing DXF
4 j2 N& b: ?5 t  G: t- R( f0 j$ l1514285 ALLEGRO_EDITOR TECHFILE         Importing .tcf file from Constraint Manager does not import user-defined properties.
/ ]' X( f" a; _; P' m# O$ L4 u8 `1515580 ALLEGRO_EDITOR EDIT_ETCH        Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected
9 ~1 ^" I# k, ?3 A9 K% D; f* X1519040 ALLEGRO_EDITOR DATABASE         Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.
. ?# z5 c9 E1 x6 V! \3 _. N1519910 CONCEPT_HDL    INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default+ @0 M" |- y1 h! Q0 E% ?* Q  W, z  R
1519943 ALLEGRO_EDITOR DATABASE         When user units are changed from 4 to 2, the design seems to disappear from the canvas- w3 y  B- E8 l2 i
1519946 CONCEPT_HDL    CORE             Renaming a net leads to loss of constraints associated with the net& i+ @5 K% p, d. i+ k, E; g1 W# N
1519987 ALLEGRO_EDITOR SCHEM_FTB        In Hotfix 61, constraints are lost on importing a netlist4 s  A7 D; u4 ]: W
1520727 CONCEPT_HDL    CORE             In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
8 K7 F0 M+ p2 _1521174 SIP_LAYOUT     DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor7 F% s5 l, ?; x0 N( ]0 n% j
1522227 SIP_LAYOUT     IC_IO_EDITING    SiP Layout stops responding when trying to add a co-design die (.xda file)
0 O8 N2 Y' v  d$ G5 l2 N1522900 ORBITIO        ALLEGRO_SIP_IF   Padstack shape distortion after translation to OrbitIO from SiP design
# _) k5 j' f$ I% X( i. v1523237 ALLEGRO_EDITOR SKILL            SKILL function axlDBGetExtents() causing PCB Editor to crash
' N" A7 W& E; L; m' c1524641 ALLEGRO_EDITOR DATABASE         PCB Editor stops responding when updating outdated dynamic shapes
; D& A( d5 h7 ]1525432 CONSTRAINT_MGR OTHER            User-defined property not being transferred from DE-HDL to PCB Editor
5 b* M# ~0 L2 H; S) X1525948 F2B            PACKAGERXL       Reference designators assigned by the Packager tool are not correct
8 ^$ ]5 z% }- c2 w0 P# M+ |1527321 ALLEGRO_EDITOR SCHEM_FTB        Unable to create netlist with the 'Open Board in orcad PCB Editor' option in Hotfix 637 t5 A$ G4 D) z" f" q
1528254 CONSTRAINT_MGR CONCEPT_HDL      Import Logic with the 'Overwrite current constraints' option is deleting some attributes
  B2 ]! E, a. r$ i6 C7 y- b% h
1 {/ |$ v& U+ Z6 y; C9 A3 F: d* ~DATE: 01-15-2016   HOTFIX VERSION: 0630 J& \* A' t" K: J- O1 D* m
===================================================================================================================================
2 W9 I2 g6 z' PCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
9 }3 {, w4 i1 s5 W8 p- m===================================================================================================================================; i# n, Q( o5 l9 m0 r/ l) N9 x* ]
1472414 ALLEGRO_EDITOR SCHEM_FTB        netrev changes pin-shape spacing rule in constraint region
1 ^0 b& k& B) |5 p# [1494194 CONCEPT_HDL    CORE             Random display of the 'PHYS_NET_NAME' property in hierarchical designs0 Q5 Z' `5 Z7 S- I- _. |1 U
1500190 ALLEGRO_EDITOR EDIT_ETCH        Snake Router Creates Line-to-Line DRCs
/ c) G: ]2 M1 K" \7 s4 N1501093 SIP_LAYOUT     OTHER            Package design variant shows wirebonds connected to a die which is not part of the variant
5 v, {, t/ J! d+ B1509184 ALLEGRO_EDITOR DATABASE         BB vias in mirror have terminal pads suppressed by artwork  s6 U8 e8 r3 w- t" c
1511397 SIP_LAYOUT     TECHFILE         Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.64 T+ i$ t& Y- r  U' `1 H
1511744 ALLEGRO_EDITOR OTHER            Allegro PCB Editor removes property from component instance
. q5 }# C, E0 C/ ^, z/ n5 {1511761 SIG_INTEGRITY  OTHER            Allegro PCB Editor crashes on running the cns_show command.
* z1 Q" G9 q7 ^, B1511787 ALLEGRO_EDITOR INTERFACES       IPC-2581 not exporting overlapping shapes correctly.* _( A$ A4 H5 j1 {
1512071 ALLEGRO_EDITOR OTHER            The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out( _% [6 C* q7 p* ^4 z: m4 B- {
1513085 CONCEPT_HDL    CORE             NC pins combine with NC_1 and routed as one net in Allegro PCB Editor
3 j; v4 }% O$ P" F# X9 a3 i1514469 CONCEPT_HDL    CORE             Unable to get rid of an underscore from the PHYS_NET_NAME property
1 c: z1 r5 Y6 S: b& {- H( ^1515318 PCB_LIBRARIAN  IMPORT_EXPORT    Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly' p( m7 w9 E  `4 q6 ]% J
1516093 ALLEGRO_EDITOR PADS_IN          Pads library translator does not translate slot orientation
2 D6 n: t1 Z, [' s  z1517351 CONCEPT_HDL    CORE             Genview does not update an existing split symbol
9 W  @5 {' Y3 b6 A% T2 ~. m4 P. c1518032 CONCEPT_HDL    SECTION          How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'4 m8 a+ c5 B* y5 V! d- H& A
1518724 PCB_LIBRARIAN  PTF_EDITOR       PTF Editor is not saving changes
1 _3 s9 q' ~: k1 E$ M7 |1519518 CONCEPT_HDL    OTHER            Genview does not generate split symbols# t) \/ Q8 U$ t; b5 k, a4 ?
1519623 CONCEPT_HDL    CORE             Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas4 ]3 u: w. `; s1 Z- A
1520207 CONCEPT_HDL    CORE             Genview crashes after renaming ports
; C2 D& |. `8 c
0 R4 _: W  c/ `: |DATE: 12-11-2015   HOTFIX VERSION: 062- b9 \+ a+ f5 y9 m, p9 A) v9 J
===================================================================================================================================
2 d5 m/ M$ ]; u2 D0 `CCRID   PRODUCT        PRODUCTLEVEL2   TITLE- E( W) j, z3 [) K
===================================================================================================================================
: X5 t+ Z; M% }0 d* c1 q9 l9 l; ]1012606 ALLEGRO_EDITOR REPORTS          Natural sort option for Report output6 ~# ?/ f$ }5 O7 v
1408218 ALLEGRO_EDITOR MANUFACT         Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
  J4 t4 Y. r8 b" o1 R3 w1440509 ALLEGRO_EDITOR PLOTTING         Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option
$ h2 W/ f& L6 g; o1444144 ALLEGRO_EDITOR DRC_CONSTR       The 'add taper' command generates line to line spacing DRC
6 x+ z0 K9 D4 c: e% j1471275 SCM            UI               Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view" f$ @/ J; m: k& y
1474764 ALLEGRO_EDITOR PLACEMENT        In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked$ U% y4 T1 Z) W. R4 ]
1474894 ALLEGRO_EDITOR PLACEMENT        Place replicate fails to include vias when the module is applied to other circuits.$ C. S1 l" w; g0 P
1485931 ALLEGRO_EDITOR INTERFACES       Errors generated when importing IDF in an existing board file
5 c4 s, k$ f( Q: i1487603 SIP_LAYOUT     WIREBOND         SiP Layout XL - Add multibondwire option to non-standard wirebonding
; i* K2 `5 j7 r. ]1490311 SCM            OTHER            Block Packaging reports duplication when it should not
" A( f& g" r  {9 N( ^, T1491272 ALLEGRO_EDITOR EXTRACT          Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'* C# J2 J' t8 V! N$ f
1491521 F2B            PACKAGERXL       Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message
. }$ I( l/ b* G) @' v" ]1492013 CONCEPT_HDL    CORE             Stale PNN properties not cleared from schematic on packaging design (backannotation)
; d) Q4 {1 _" T6 a; b7 l( L8 r( @1492703 CONCEPT_HDL    OTHER            'Global Property Display' not working for symbol edit
7 f/ u: h! m" X1 N4 _& |1495296 SIG_EXPLORER   OTHER            The T-point sequence in SigXplorer is different from the layout
' E" D' x9 K5 k/ ^, s1 {1495789 ALLEGRO_MFG_OP CORE             DFM checker checks for laser vias ( LVDC, LVDP, LVDT )# |, Q) w! \- S8 E
1496286 ALLEGRO_EDITOR PLOTTING         Export PDF is not exporting hidden, phantom, and dotted line types) _/ x5 U! x  ]1 g2 r
1499051 ALLEGRO_EDITOR PLOTTING         PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'
, x  `7 _5 A9 P& g1 I$ ^2 A1499380 SIP_LAYOUT     DEGASSING        Oblong shape degassing voids are not created correctly; q! v- Q+ `0 W. e. f1 i& E
1499538 ALLEGRO_EDITOR PAD_EDITOR       Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this
7 p" F5 u2 G; S  m$ L1500422 ALLEGRO_EDITOR SKILL            SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
. r) W- K9 M' W- `6 X0 V1500659 FLOWS          PROJMGR          Need the ability to ensure that the standard library is not added to the project libraries list by default
6 {' D; k' G! R: r# k- O- }$ o1500725 F2B            PACKAGERXL       Unable to clear pstprop.dat file conflicts/ N/ a, h8 `) ^# h0 F' v  Y
1501139 ALLEGRO_EDITOR PADS_IN          Pads_in creates pastemask for Through Hole padstacks
/ h+ M' F8 N9 d, l" m1501165 F2B            DESIGNVARI       TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out& a: d! m# q  B6 H
1501774 ALLEGRO_EDITOR OTHER            PDF Publisher: If text is attached to an object, the object is also printed in the PDF3 S7 P- C  Z; @7 T1 y
1501898 F2B            DESIGNVARI       Variant custom variables are visible in the schematic border but are not there in the Variant Details form; q) U" h) s% |% _0 h
1501974 F2B            PACKAGERXL       'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL1 ^& _; Y' o5 y* h2 q
1502782 ALLEGRO_EDITOR SCHEM_FTB        Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings
7 M2 C' h% O0 G1503551 APD            STREAM_IF        In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location2 U+ O1 N4 z7 T& d
1504093 ASI_SI         GUI              View Topology and Waveform buttons overlap when Signal Analysis window is resized9 i2 A7 g: O3 T1 X; H: x! C
1504767 CONSTRAINT_MGR SCHEM_FTB        Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
# o- ]. y6 {  R% c' W6 j! Z1505497 SIP_LAYOUT     LOGIC            Assign net fails to fully connect propagated items; k3 g+ Y$ v$ d. b2 K
1506110 ALLEGRO_EDITOR DRC_CONSTR       No DRC shown when a text on etch layer is overlapped on mechanical pin
2 T; j- i( c% Q6 q1506654 CONCEPT_HDL    INTERFACE_DESIGN Netgroups broken when moving
3 @4 m# V3 l0 E* I! O1506983 ALLEGRO_EDITOR SKILL            axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None
& W- P* t  t  Y) T6 K9 @$ P9 M
" T0 N. G  {  J& B$ aDATE: 11-20-2015   HOTFIX VERSION: 061
% `2 `+ J' ?% m6 }: p! j===================================================================================================================================0 ~1 r+ r& G1 v5 M
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE+ ?' x& B# c4 c3 g
===================================================================================================================================
* K. m6 O3 W8 u  Q( `1306441 APD            OTHER            The Minimum Shape Area option in Layer Compare uses an unspecified value# W$ v- o  a; k+ r5 ]: z
1342644 ADW            COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init8 P( x( J9 R0 P; V7 @" G
1413248 CONCEPT_HDL    CORE             Import from another TDO project makes the block read-only9 E# \# _) E: t; M3 s+ _
1417429 ALLEGRO_EDITOR INTERACTIV       Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
$ t: s, H2 Z9 b' H% E* S0 {) {1417442 ALLEGRO_EDITOR INTERACTIV       Spin via stack and only part of the stack spins+ M+ g: r2 z- b; J0 p" V) I
1451977 CONCEPT_HDL    PDF              Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
# Z1 F& N' R" m3 `1453527 ALLEGRO_EDITOR EDIT_ETCH        Contour route hugs the outer edge of the route keepin
5 k4 f! E/ h0 i( q# |1464948 PCB_LIBRARIAN  VERIFICATION     The errors/warnings do not match between the various tools
  D! k# a: F( e5 e$ v0 I$ N  }1467826 CONCEPT_HDL    PDF              PublishPDF from Console Window creates a long PDF filename
% n8 H# z: r1 [7 A" `1478639 CAPTURE        OTHER            Capture Browse Nets window does not display all nets
- f0 r  r- l! w& w1479177 SIP_LAYOUT     OTHER            Pin pair constraints do not appear to be supported in Sip Layout XL% z/ U, w7 u/ O! N
1479227 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
" f% F' f; o+ R! p1479454 CONCEPT_HDL    OTHER            DE-HDL issue: locked DIFF_PAIR property is editable/ q5 t9 Q  W# B: P
1480293 CAPTURE        PROJECT_MANAGER  Capture hangs when searching for all nets( G  d  W- P, |1 ?# R
1483894 CONCEPT_HDL    CORE             Import Design hangs when pull-down arrow is clicked twice
$ _0 Z) B5 x' ~& N; K$ y1484781 CONCEPT_HDL    CORE             Three different Hierarchical Viewer issues
/ }4 {2 l: b- u, ?1485059 PCB_LIBRARIAN  CORE             Part Developer pin attributes are randomly marked as read-only% V7 E9 f. R8 |) r
1485960 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule is crashing the project# p) H2 ]9 f6 J5 |/ u
1486086 ALLEGRO_EDITOR ARTWORK          Cannot generate artwork.
' R: P+ G# y0 I  _0 X& [! p1486834 CONSTRAINT_MGR OTHER            Restore the Status column in cmDiffUtility
3 ?1 b( y3 C; u6 Z; {  Z) [( k/ \1487085 CONCEPT_HDL    CONSTRAINT_MGR   Import Physical with the Constraints only option reports problems
3 z) b3 F  `5 s+ }1 f& `+ u1487197 ALLEGRO_EDITOR DRC_CONSTR       Drill to Via DRCs are not being reported5 C! _- x; ]( g1 \0 b: X6 o, i
1487265 CONCEPT_HDL    CORE             Replace command in Windows mode shows incorrect behavior
* A! W$ k: ?: y1487733 CONSTRAINT_MGR OTHER            Running Export Physical - It takes over two hours to update the PCB Editor board
! M+ C6 Z0 K( L5 l' s1488758 CONCEPT_HDL    CONSTRAINT_MGR   CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager) T# Y( ~! @: c+ J
1490299 SCM            OTHER            ASA does not update revision properly
7 Z7 L' V$ e# ^" n* J  H+ f" [1490744 ALLEGRO_EDITOR SKILL            axlChangeLine2Cline changes line to cline and places it on the TOP layer& _2 d) |" q4 q
1490924 F2B            PACKAGERXL       Save Design/Export Physical is resetting Via constraints/ F" Y3 \0 }9 N% X. E& E
1491351 ALLEGRO_EDITOR OTHER            Create Detail for bond fingers on a custom layer not working
1 [4 z# b5 x9 t2 J% P/ i6 e1492595 ALLEGRO_EDITOR MANUFACT         Dimension character substitution help is wrong
* V) t6 G* S3 U7 N1492777 ORBITIO        ALLEGRO_SIP_IF   OrbitIO import of customer mcm results in crash
5 w( D, w; B8 E7 |* J$ `$ P1492901 CONCEPT_HDL    CORE             Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
+ f7 `. U. m2 I) E2 Q' m2 i1495621 ALLEGRO_EDITOR INTERFACES       Oval pins are placed with wrong orientation in IPC25818 {% Z* t+ x: @, t# ~8 {
1497597 ALLEGRO_EDITOR DATABASE         Show Element on pin shows wrong drill size
/ J9 F3 i$ ]! B/ l1 _! _8 M1497956 CONCEPT_HDL    CORE             ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
+ A, z; c6 w6 ~: \1498234 ALLEGRO_EDITOR ARTWORK          PCB Editor fails to create artwork and no error is listed in the log file
/ k# ], k/ h4 _1499363 CONCEPT_HDL    CORE             Custom attributes under variant management stopped working in Hotfix60

该用户从未签到

2#
 楼主| 发表于 2016-6-29 12:27 | 只看该作者
截至目前 071 版本,
1 d+ u: |) y# N有關 CAPTURE 最後補丁到 061 版。9 t; Z% _2 y/ R; M8 x+ X
有關 PSPICE  最後補丁到 058 版。  N/ M  J& j0 y7 c( G! B; L
只用上面所說的二項軟件的朋友,不用追補丁到處跑。

该用户从未签到

4#
 楼主| 发表于 2016-8-18 07:41 | 只看该作者
hermes 发表于 2016-8-17 13:05
  X& [5 _3 @6 W; B7 P' t9 P何处下载?

; U, s6 S2 ^: L* `+ ?" \5 J' EHotfix_SPB16.60.073_wint_1of1补丁/ ^. g) s; r0 J/ R3 O+ x
3 P3 \6 O" [/ K" p7 ^) S1 z" }
http://pan.baidu.com/s/1i5jStCx% q% }& c) R' z/ @2 h

该用户从未签到

5#
发表于 2016-8-22 09:13 | 只看该作者
已下载,谢谢!

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6#
 楼主| 发表于 2016-9-2 06:37 | 只看该作者
新增  076-072 版的補丁內容8 L: R% _- f7 V& O0 K' ?& e

2 ^1 @8 B* X) H6 m- \7 ]# h/ _" m( C6 x& p: w
DATE: 08-25-2016   HOTFIX VERSION: 0760 R7 i$ l  l0 k) A/ A& m4 |
===================================================================================================================================
7 H2 r. g9 C4 M* T5 L: ~) rCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
" O- ?3 d* T2 p# Z0 F$ z7 a===================================================================================================================================
' E4 @' H, q4 _1614667 SIG_INTEGRITY  SIMULATION       Different results from Probe in SI Base and SigXp
& a1 a; {0 p- O" x$ c0 D# m1615601 GRE            IFP_INTERACTIVE  Delete Bundle then try to delete plan lines results in fatal error
; z0 g+ x" ^. c. s5 R1616540 SIP_LAYOUT     DRC_CONSTRAINTS  Same net DRC Line-to-Line reappearing after dyn shape update
& Y/ D+ r' Y# V. U
& R+ F2 i8 f/ l. }$ TDATE: 08-12-2016   HOTFIX VERSION: 075  D3 p6 _: m5 D
===================================================================================================================================( x8 |8 x8 @! k4 U$ p1 P; ?$ L
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
' B3 w+ Z8 A& y" |7 y- k===================================================================================================================================
6 e( z$ k+ i+ k. z2 @; t- A! {' Q1461626 CONCEPT_HDL    CREFER           Cross-references shown to the same pin on different block instances though the signal names differ) M! S! [( ~. f7 G
1597000 CONCEPT_HDL    INTERFACE_DESIGN Renaming NG does not work if >1 segments have NG names1 z1 R' v2 S# v. |, k% c, a
1602801 SIG_INTEGRITY  OTHER            Dielectric Warning message when opening SiP tool.
7 a2 k! ]# [9 [3 Z2 M, P1606861 CONCEPT_HDL    CORE             Crash on Linux during Generate View# T2 {% T" V# i7 n" A
1608524 SIP_LAYOUT     MANUFACTURING    The Display Pin Text tool fails in the 16.6.073 version with a parseString error.
/ X' n- p% i+ W6 a  H1609922 CONCEPT_HDL    INFRA            Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only9 c+ K$ ]/ w6 @
1612108 ALLEGRO_EDITOR OTHER            Netlist Import is crashing with the .SAV message.4 Q0 g0 ~2 t% v0 `9 f% G

2 j2 K. \# N- t0 A) w$ \" X; ZDATE: 07-22-2016   HOTFIX VERSION: 074
* a- f& ^* f2 M0 C6 Q% ]===================================================================================================================================1 D' r' q1 g5 l" h* ^8 p8 y" V3 |
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE2 k8 a8 o6 c/ h
===================================================================================================================================
0 a' M4 p, e. |1423889 ALLEGRO_EDITOR EDIT_ETCH        AiDT gets poor routing result
# \( o. |! y  {  z5 D* Y1547356 ALLEGRO_EDITOR EDIT_ETCH        Results variations from ISR S034 to S066
" m" S" m. ?2 i3 z$ r1568912 RF_PCB         BE_IFF_IMPORT    Route keepouts can only be imported once/ d, @7 {- X- s0 ?2 h6 [
1574676 ORBITIO        ALLEGRO_SIP_IF   sip->oio eco doesn't work properly( F6 V! T7 n# F! J. J7 i8 P5 Y
1580744 F2B            PACKAGERXL       ERROR(SPCODD-114): Duplicate physical part name NETSHORT found/ D2 q# a- V, W6 m" B1 r6 d
1582628 ADW            TDA              When one user takes an update of physical object while the other user is still checking in the object, TDO crashes
8 y+ {7 D# u0 d/ @1584719 TDA            CORE             Caching errors coming for a board ref project while doing Block update
: j$ Z& l1 ?5 T$ ]$ A; j1587157 CONCEPT_HDL    CONSTRAINT_MGR   pstprop.net reports conflicts on nets with VOLTAGE properties% R6 ~4 g' t  U) m  r5 u# c
1587498 CONCEPT_HDL    INTERFACE_DESIGN Possibility to tap bus bits removed
, f& \9 u( N5 i1588786 ALLEGRO_EDITOR OTHER            strip_design reports "Design corrupted message") }. g# ~4 F6 H' @' }+ C
1589252 CONCEPT_HDL    CORE             Search options go to page origo not chosen component
  I5 _6 D2 x, C! ]8 \1590538 CONCEPT_HDL    DOC              Open Archive shows unclear behavior' N2 E; M  Q1 p( t) `
1590639 CONCEPT_HDL    OTHER            DEHDL crash when importing design
  u5 K: {5 k( g$ [" a% E1590651 CONCEPT_HDL    INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM+ H8 Y) b( v' k- d& G
1594076 TDA            CORE             TDO is crashing on concurrent checkin when one of the user got blocks which are not modified" G! a+ b) U8 L
1594358 CONSTRAINT_MGR CONCEPT_HDL      Enable hierarchical BOM fails for sub block with working variant view
' S' V$ w4 {4 I2 R! x7 }' r8 W1596780 ALLEGRO_EDITOR SKILL            PCB Editor crashes after doing SRM update and save
! h$ v* S7 \# V. H$ t8 C. C/ A& t8 u) N1597153 F2B            DESIGNVARI       ERROR SPCODD-53 in Variant Editor
1 M2 P5 }8 ]3 G# Z& Z& U( l0 r1597385 F2B            DESIGNVARI       Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI
8 b7 y( o" }' ~7 c$ ~+ x1597413 SIG_EXPLORER   SIMULATION       SigXp crashes when simulating with via that was added to canvas
! B& E0 E- N  |9 h/ m1598629 F2B            PACKAGERXL       Export Physical crashes
4 v8 _7 m3 u, U) @; j& W6 N# r( A1599452 ALLEGRO_EDITOR ARTWORK          Import Artwork, Mirror option does import pins or shapes.
- n& g7 v0 B1 g1 Y1599950 SCM            OTHER            Adding the GND net to parts/pins takes a long time.7 F" {( A7 _, q* C
1600226 RF_PCB         AUTO_PLACE       Fail to auto-place RF group/ d, o$ Z/ e- c5 d* A
1601281 ALLEGRO_EDITOR OTHER            STEP model link gets corrupted with SKILL axlLoadSymbol
1 v3 v- n+ \! }  ~. n1601282 ALLEGRO_EDITOR OTHER            Export Libraries will not export device files when there is a space in the folder name.7 `/ N: D) y1 z; z3 x
1602186 PCB_LIBRARIAN  VERIFICATION     con2con should work with PCB_Library_Manager license in 166 as 166 tools should work with 172 upgraded licenses" `: w/ l6 x% u8 c7 X
1602514 PCB_LIBRARIAN  METADATA         References to some primitives is missing in block metadata causing TDA errors for missing parts after join project( n5 T' D3 c& V! l2 ~( f: Z  F
1602823 SIP_LAYOUT     WIREBOND         SiP Crashed during Add Wire command
3 `. j  c: x; |& G1602955 ALLEGRO_EDITOR SHAPE            Shape no DRC when there is a Route Keepout in base layer.# B$ Q/ A- I2 I# u! Q1 L0 T
1604223 CONCEPT_HDL    CORE             ERROR: SPCOCD-553: Connectivity Server Error$ M# L4 h) c& ^2 {
1605310 TDA            CORE             TDA is crashing sometimes in the Join Project wizard
- Y% C) ?% y6 S9 N/ ~' @9 H+ i+ w$ N0 V" f4 D
DATE: 06-24-2016   HOTFIX VERSION: 073
) s6 w% o, L" ?: w  x0 E- m===================================================================================================================================
1 x( w( |$ }. C  w) b. m9 D0 CCCRID   PRODUCT        PRODUCTLEVEL2   TITLE! }2 [4 @, V  Q$ U- d
===================================================================================================================================; t% L4 P5 q9 x! `
1570032 ALLEGRO_EDITOR GRAPHICS         Issue with 3D View5 z) m$ l; b$ b6 r' r, T( D: h  ?$ E
1582103 ALLEGRO_EDITOR PADS_IN          PADS Library Import creates additional filled shape not present in source data
  C9 E$ v# E5 y4 R' a$ K1590954 ORBITIO        ALLEGRO_SIP_IF   import of brd file fails with "Undefined argument" error
2 \# }0 h% d7 y  L1591223 CONCEPT_HDL    CORE             Variant information does not display on lower level schematic3 W' h8 }  {0 B3 \4 E% v

+ p2 c8 p1 i7 w  n* RDATE: 06-3-2016    HOTFIX VERSION: 0727 h9 n2 M/ L/ M* d
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/ V, |" ]! \) a; K: {" uCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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9 S2 M" d4 B( ?0 O. R7 {1546151 CONCEPT_HDL    CORE             Add port, Genview, move pin on block - the pin name disappears
0 Z$ ?7 m3 G6 Y9 S1566274 RF_PCB         FE_IFF_IMPORT    RF-PCB -> Import IFF crashes in DE-HDL
5 n2 D2 b- s' c* @1573039 ALLEGRO_EDITOR INTERFACES       IDX returns control to the general interface prematurely during an incremental IDX export
( k& ~3 c: W& O; N0 ^# X! a: S1573127 CONCEPT_HDL    COPY_PROJECT     copyproject creates incorrect view_pcb entry! b4 q7 ]2 T: W( w
1577381 CONCEPT_HDL    CORE             ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure
: w+ w+ _& S! }5 E: W$ n: f1580891 SCM            REPORTS          Dsreportgen crashes on different scenarios
; K0 C  s7 J8 H# G  j4 }( n1582863 CONCEPT_HDL    CORE             Generate View creates non existent ports$ U; f7 k2 z9 V  \$ H5 o- h
1584317 CONCEPT_HDL    CORE             When  packager fails, no option to open pxl.log file from design sync window.
2 k, ^3 d; ~$ L' d
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