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DATE: 05-28-2016 HOTFIX VERSION: 071! X# l* \$ e* [8 l" Q4 J
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0 Y4 k4 Q6 B) J( a+ S, H" Q+ {1452838 concept_HDL CORE Apparent discrepancy between Bus names and other nets
! c K3 F% ^+ V, D1 {$ Q: F1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package$ l% R8 z4 ~0 U6 F E$ x' N
1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser/ D8 y' Z5 K% {
1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly+ n0 i( ^% i: L, w$ n' F* X& c
1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.8 g1 ^) C) U: z9 ^- s
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.# D+ x1 a8 A: H
1544675 allegro_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)
3 b0 }$ U$ I* S& [1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set
+ F* }3 j+ c) J5 {* R2 Y7 R1551934 ALLEGRO_EDITOR skill axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
' m7 L$ b0 E3 t; ~1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library
+ B. D! _4 p! [' f+ o% v1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG
. x9 f/ G% e; m+ G# T1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon' V2 d" T. F. Q$ `: y: _! G F9 _
1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets/ L+ r8 n4 l7 f
1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open( w0 G0 i1 b( r* Q& K
1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
* a, Y7 I, ~' r' u1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC
. v. j- B( m, B# _1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins. Q+ `- \: Z% j) o
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas
/ W2 e/ |! w+ r1 @6 f1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions" ], N( Q2 B$ ~1 R
1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete4 r* a3 c2 Y1 b7 I# s" z) u( e
1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.
' m. I. z8 P$ G0 q! q1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct
7 ~: u: U7 c- j. e1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window
3 }0 h' K3 o8 e# g; X! {$ V1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'
' O3 ~% X- d5 v1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed# D& n" U4 v7 H/ n4 Y6 U$ Q
1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...
* i% h8 j& l( m2 Z- W6 ?( `: B1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager
, }2 d; q) B' I* {1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short
5 F' Y: U7 F- K. c# f1 ]: u# L1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property' T# C9 E( ~, C, N: s6 T
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only
+ J& \2 a8 _' b% o0 q/ y0 ?1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display+ g O2 R8 y1 j$ ]
1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET); c* P3 l) J* ]) D& N* ~: S: f
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file
+ L% S+ U3 v r X# ^) `1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings/ d4 Z% ]% B8 v, j" ~( C" p- d
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'" Q& n* [" {2 {
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files
) N% C& t7 Y% q! Q- o$ t" V P& I Z% D6 W5 n/ d5 `5 ^
DATE: 04-22-2016 HOTFIX VERSION: 069. ?1 E1 F5 f2 X2 x C5 W/ W; H' W
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output9 `5 P7 Q0 @1 y
1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode
# o6 G/ @, I6 w% ?$ F- c1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail
: c, x. V6 ~7 r- G' Y* N$ A1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
) E5 ?: E. z( b& y# T+ q# e9 B1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing, ~0 N# o4 d) n9 l
1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute
_1 {7 J8 R, \3 \! k: G+ h1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals
/ M/ ]9 `$ w* V9 Z; h1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork
; u. T/ D% q/ O% H) b! k6 _1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed7 L% ~. O/ M- ?5 j* w2 W
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
' {5 r, V2 F# @# Y4 K2 `+ `1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work
8 O" x5 _6 f: a1 ^2 f, J7 _1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork
5 E( a" q. k/ S; J; i$ s1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message
* c0 S5 ]- I, `& s% H( W$ n/ D2 M1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point
% ^8 J0 b. q4 D0 c* z6 B k1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines, ?$ J1 a3 v& z( ^# }: e! j
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems" r4 x. y, z/ ^: n, @- {
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro
+ j% H( J1 w( k l! L G; l1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups" b; d4 n2 [1 \# z3 h/ p& w
1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons
4 g$ h: N, x& D1 \ x) i1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes- t0 |1 K% p) C( q3 u" u' C" g6 m/ r4 Q
1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted7 _; J7 c5 D: [9 `
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die
( _! g- Y" S- H1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM
: K( g2 M. F/ S! ^# W; _, S% h1 o. b1562537 ALLEGRO_EDITOR mentor Mentor BS to Allegro 16.6 results in Fatal Error
9 o1 i, Y7 {0 F" r6 a1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.
2 v) h) X5 A" k4 `7 ~3 g1 Z9 ~2 ~' `+ h
DATE: 03-23-2016 HOTFIX VERSION: 0683 W! F& e0 N8 R* y, G
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h* B+ t2 H" QCCRID PRODUCT PRODUCTLEVEL2 TITLE1 P0 n4 R3 ~3 p8 N+ |* O
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1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager
) t5 V8 k9 ^/ ^, H1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file. ~5 w9 ]5 K! N A2 I
1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license
3 E$ J( C; {$ X4 h! A3 b1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short+ ^; o, Q7 X( e* i- q4 k! I0 B
1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system2 ]9 }% H/ ]& K; U# ]
1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.
/ F# u$ c8 D0 g. j6 \1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol
, s7 Z4 x& K Z D% o- b2 C4 a8 E9 g1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file# s" R0 o, X) ^
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report
6 N, x/ C3 s, A+ G q1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'
: ~# Z+ l9 ]$ [5 K1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have .% C d- K5 q+ \7 Z
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts
6 c8 F0 |& E, r5 I, ^4 V1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols
3 e/ k/ A' D2 S8 J6 t% Y
) n# C& S5 q1 F1 |" {/ H/ jDATE: 03-11-2016 HOTFIX VERSION: 067$ \* O* Y1 u6 _3 ?; x" R
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CCRID PRODUCT PRODUCTLEVEL2 TITLE; L# ^' T4 D; t( C2 n* J( U7 q
===================================================================================================================================
8 X; J: I5 D9 ^" ~3 C1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group' H+ e' A' m5 B
1484075 ALLEGRO_EDITOR pads_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
8 w8 ^" ~: C- H& |- O7 b3 d7 |$ L1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error
% {) Y7 s& J0 I( |1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'# x6 V- p+ f+ ]+ D! G2 J3 C8 m9 |8 V
1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property
0 Y2 @$ Q5 l2 g; G4 p1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net" m5 U* ?3 }* Q% g" J6 k( t
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file
, S9 A# u/ Y; f9 r. G( x! m& X1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes: _& t( m& t: u$ T" Y: n
1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing* Y9 X5 }/ E4 {3 |
1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager* }# T8 B7 Q' A8 ]4 n
1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters
% @7 z |* l9 a2 ~6 h6 m1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties& B# c; Q7 g7 E2 ^% G2 z
1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer
8 Y7 H! z8 Z' T3 b! Y+ l1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
( m' @' H. e& i5 B' o1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform# p+ @' D6 {2 S/ D. q! X/ B& u
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
% _, ]( b1 ^5 H: c" {1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error
4 N* T0 y1 R' m1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.4 i& t7 a& D; V. \: o' S7 S. Y
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib' { M3 U0 _3 _9 {) {- g
1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines
" @1 C% T! j; c1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols% X; Y! O+ i1 y9 X) J
1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board
2 T4 P+ L7 I' {) h" ? ]8 U1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash4 }! ^1 J+ a8 m: k! M
1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash
0 T! d, f& X7 D+ p. ~0 ?& H+ d# M1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked
/ t7 U: Z; I7 {0 p$ A* @6 Z1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions. z) V, o% d( o; D+ Z) H, r
1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with+ `4 J4 j( w' A1 o+ q. G3 ?
1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design j! W, @3 s& J' D7 C
6 ?) V2 f7 N$ v/ P8 _
DATE: 02-26-2016 HOTFIX VERSION: 066# J& `! `& C; L; n" P
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+ q: W5 T' ?% QCCRID PRODUCT PRODUCTLEVEL2 TITLE- W2 L. j l @3 \' e8 A" x
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1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated2 ^/ q1 D, W: S7 q0 N$ [/ t
1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes
. e, L% Z6 e- u4 Y1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions
2 ~ F( }0 s+ U7 Z% j1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message& k& T/ ]; f9 X* }- k2 [
1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr2 N9 `& g! I* u9 ^
1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue
3 |! ?$ H( C7 t, X x, ~' ^( i1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer
% B- q% U+ ^5 @( k1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins
- Y) t' Q' ^3 _& y7 A v. O1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run
- I! |+ p# u9 |- L3 r) F7 o; G1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed5 z* `, u( u5 _. y5 D
/ }3 G4 @ }( [: I9 O/ I) XDATE: 02-12-2016 HOTFIX VERSION: 0650 e& g0 K8 \6 O$ e
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" P7 e. b; B% hCCRID PRODUCT PRODUCTLEVEL2 TITLE1 p! t" R5 C4 C$ z
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1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working0 ~+ A: q4 b8 j) _( y5 l/ n
1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via6 a" G4 C/ X7 P/ B
1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit
8 A7 Z: h( }% s4 Y9 {1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.
6 `7 g. X# }3 o- }* W# W1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms( n; `% G6 _. h+ m" r
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine
$ X! @2 F2 h6 A2 U) \) j6 b5 F* X1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger
+ J# q p3 J# R1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design
% R% r' I" v# ~' i! o1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup' w- U( g$ o$ C% ^2 _
1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license.
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DATE: 01-29-2016 HOTFIX VERSION: 0648 q V# ^8 L8 W* \
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1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
5 k7 E+ t7 |. K7 J/ M6 H' P1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF
, d* Q" }5 r: Y- Y% r8 W1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.& j$ j9 r2 v+ f& J' |9 M" l
1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected
1 M2 o: n* R8 S" B# ?1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.6 D' u( {! f0 F/ f+ t- Y
1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
+ F! S9 J6 |# Z+ S1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas+ d- B+ D& ?- N8 U# a2 H
1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net
! g: w& X$ i p! A' |, m6 g- O' _1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
% _, p( Q3 }# g- X" M+ B; o0 G5 Q1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
- o3 E e& K( i* {, p1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor7 ]: A- j9 L w: m8 L
1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file)% N$ s9 m7 `3 p% F3 v; R5 R8 n, j
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design% ~* o. A# W0 Q( F" _' @. R+ g6 l- M
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash
5 W, `) n3 P' z+ m5 H- f1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes
0 |, {. s0 E4 J/ H1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor
# [; I. W P: m4 M; |) f, K1 }1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
* l' f' i. v* F1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in orcad PCB Editor' option in Hotfix 63
0 f( Y, |0 F1 \1 O) H, B1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes3 B- _4 }# S$ ~
3 @0 N( w( N3 m. K; d' K8 EDATE: 01-15-2016 HOTFIX VERSION: 0634 c0 `1 ]. L4 y) Y# } o5 G9 H
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! ]9 z5 x/ q. H D. @% }: \9 M& ZCCRID PRODUCT PRODUCTLEVEL2 TITLE
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( @) j8 w) ?( Y% l) g1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region' ]5 E0 l( g8 B2 }4 T/ G9 }
1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs8 \3 u3 m* r" _9 x/ J8 M% A
1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs) t) b& f" p: a% w5 r
1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant
* k$ w& ~; I& Q6 |1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork1 d# d. u/ w9 @+ j/ O- v
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
8 r) `$ z! q+ c q, j1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance
- p7 _5 i; |) y z, h! ^7 i1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.7 [* h3 y% U/ o
1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.. G; A7 [/ ?: u( u: W9 {2 ~
1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out) P+ \# s* h5 u# r
1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor( }$ F4 S0 `, S y
1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property# M$ f) f$ q4 M% D
1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly
, X8 Z/ [; E. z+ G$ l7 n8 z1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation
1 q) s' V4 L" B1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol+ q2 v5 M' B q# V8 b
1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'
$ G9 K2 b, V! A( W) a% ?1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes
1 Y* }, l8 \* K2 t |4 H1519518 CONCEPT_HDL OTHER Genview does not generate split symbols
% |. _; p! L2 G( g1 B0 Z4 C9 `1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas
7 N2 o( C0 e6 e1520207 CONCEPT_HDL CORE Genview crashes after renaming ports
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DATE: 12-11-2015 HOTFIX VERSION: 062
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output
6 R! w' I4 c, [- A/ L1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file! ^: ^: X4 h o7 k
1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option, m' O2 H. u& a! A% o; w
1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC
* a8 ^/ O7 `! ?; n5 r1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view
( b1 R- l# }/ ^8 M1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked. F4 `1 h2 c( o' t& d" V' K
1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.' m* |: V+ b0 R2 a7 B6 G' Z
1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
. L& l/ A9 l; n1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding
9 Y6 Y) T8 X, {& ^: l8 {: v0 j1490311 SCM OTHER Block Packaging reports duplication when it should not
& t1 Z$ i1 Y: s: ~1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'6 M3 X+ f, S( h. c4 t- \" Q
1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message5 F! ]+ s! P/ T6 p1 x7 m$ i. E5 _
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)
/ `! g+ |) e9 x- `7 q1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit
% b. {! V; o* V' @( |/ d) _4 r1 _1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout# I' o5 u$ J* T5 y$ c& [' c
1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )# z+ k$ n. n4 i5 I7 \# r
1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types
5 N! ?) G; v- @1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'
; i+ G3 s, p) v0 m) J, Y. d1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly
j" P7 s2 G$ I! b8 y1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this* D$ d" @1 Z+ p6 @ P
1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
- H% j( y ?% z3 l1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default
3 v1 a+ u T- ]4 d9 i8 K1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts; F& A Z; Z, X- k; R/ l
1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks! `& k- |5 t1 v
1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out
1 x: f, |( Y' R; |8 I! r! J* w1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF
& g& V' Z0 Z- j7 m6 L1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form x/ O* I1 w& t7 Q3 I
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL- p: |% U& L# T( ]/ j
1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings
2 u, I. k1 T4 B1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location7 Y- T5 K3 ]) p/ k- A
1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized
1 L/ p# M7 U4 o' W6 l" Q1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary0 s) D0 c+ t p
1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items( v8 {$ R J' n0 v! ~. X( _
1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin. ?0 m; C; Y% g# w. f
1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving9 _3 e1 n# C7 l4 K
1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None
; t1 l# Q; e7 O
9 T8 u* ?- ~1 gDATE: 11-20-2015 HOTFIX VERSION: 061) w' d" B9 n9 O1 _
===================================================================================================================================
" O8 }- [. b; jCCRID PRODUCT PRODUCTLEVEL2 TITLE
z' q2 {1 c( N- i' \" r* s- ~$ e& D% d===================================================================================================================================# u, r2 B. l7 N& a3 b8 b
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
4 v; |* c* s! v# o+ P8 j5 C1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init: m% Q/ d" ^ U7 `
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only
# w1 K2 d* M ?5 W1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle E# G9 [; w7 {7 t& M. ?
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
/ `. n9 Q% G8 z0 K0 P1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set/ X# B+ A h+ x J& r* V
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin9 z% J4 T& L0 [4 h: l8 M/ z8 z
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
) @* I0 w5 R4 v- Y; E$ j1 u$ Z1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename
$ o5 a% z) d8 z) i- B% d( s# ?0 G1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
6 S3 R3 K" X F' ~" F1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL
6 j3 Y3 H/ T1 `1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy$ f8 Q$ d3 D: Y: I8 f
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable; h' h6 B) g) _! u# k+ N" [
1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets! S3 K* }7 F6 Z- I6 Z% B4 ]
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice( H1 Z- ]( \/ m
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
; o5 @( Z! {2 `( W7 M1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
1 l; h$ a8 j( G5 o5 f8 i. p1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project
" N5 v+ y6 M) }2 r7 k$ P) z1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.5 s# G/ A" \( ?/ V& c# P
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility' C( t3 O6 Z; U+ b
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems2 ]: C) e" p; H5 \5 ~
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported4 J& T/ X" q, f9 o# l
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior7 p* n/ ?& N5 \) O( z1 q
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board* @% Z; o( o0 z+ W
1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
) M5 \% [ h0 l3 y6 n, L1490299 SCM OTHER ASA does not update revision properly
a. F6 }6 @8 U7 q7 i1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer0 i. ^) K, I* t
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
' S7 V T3 R P1 ^. A( G# ~ b/ j1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
% S( Q$ ?+ R. `) W" G( k1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong& v) b9 E5 h/ C; E
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash/ p; J5 z8 i1 N6 X$ p! Z5 p
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
9 ~5 B# y4 C* w9 H& {1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581: X9 k+ y# T9 Y3 v1 f# c0 @
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size
9 b2 z, T5 m! I, p1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
9 @& j0 ~ r( R0 Y! u9 V+ V* `1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file) G4 d) \2 \$ x/ z6 Q
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
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发表于 2016-6-29 12:21
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发表于 2016-8-17 13:05