Synthesiable High Performance SDRAM Contoller

Haiting32451

Synthesiable High PeRFormance SDRAM Contoller

Synthesiable High Performance SDRAM Contoller
/ ^+ k9 t0 P4 a  z8 G; t3 L) a7 xSynchronous DRAMs are available in speed grades above 100 MHz using LVTTL I/Os. The
0 E; z2 p4 e9 A  yVirtex? series of FPGAs and the Spartan?-II family of FPGAs have many features, such as
% D( _3 [$ W# T3 M" vSelectI/O? resource and the Clock Delay Lock Loop, that make it easy to interface to high
8 F( `+ }. r1 q" i2 ^4 `speed Synchronous DRAMs. This application note describes the design and implementation of
a synthesizable, parameterizable, flexible, auto-placed-and-routed synchronous DRAM
. V. Z" k- g. econtroller in the Virtex FPGA family. The design can also be implemented with a Spartan-II
* y; J5 D* |6 _2 Z" w1 `2 X* Wdevice. A 32-bit wide data interface version can run up to 125 MHz when automatically placed
and routed in a Virtex -6 speed grade device. Hand placed versions of the design can run even
- e0 M& |8 C, \, X( v+ hfaster.

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xuzwg

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Hh0203

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