Synthesiable High Performance SDRAM Contoller

Haiting32451

Synthesiable High PeRFormance SDRAM Contoller
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Synthesiable High Performance SDRAM Contoller
; `7 J" N/ K' J) ?: J9 L& `Synchronous DRAMs are available in speed grades above 100 MHz using LVTTL I/Os. The
/ @; q4 M3 g6 z, A% |8 `- v1 ]9 ~Virtex? series of FPGAs and the Spartan?-II family of FPGAs have many features, such as
SelectI/O? resource and the Clock Delay Lock Loop, that make it easy to interface to high
* R$ P: y4 {$ B9 Jspeed Synchronous DRAMs. This application note describes the design and implementation of
3 Z* ?) q' {  ^8 t3 a0 Ca synthesizable, parameterizable, flexible, auto-placed-and-routed synchronous DRAM
controller in the Virtex FPGA family. The design can also be implemented with a Spartan-II
device. A 32-bit wide data interface version can run up to 125 MHz when automatically placed
and routed in a Virtex -6 speed grade device. Hand placed versions of the design can run even
faster.

fish1352

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Hh0203

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