|
|
EDA365欢迎您登录!
您需要 登录 才可以下载或查看,没有帐号?注册
x
SDR新书:Baseband Analog Circuits for Software Defined Radio
) z* W- Q5 Q: l
: t K0 [+ P* J% I7 k7 n% Y, `/ k. a5 }7 X( w& j1 u; _7 ^
Author:
! f; B) o I1 Q0 U
( }0 L9 j& G0 F UVITO GIANNINI 2 [0 Z; _! M3 c4 x! s6 O
JAN CRANINCKX , r7 h2 C r: P" c; @. u8 u- [
ANDREA BASCHIROTTO
% ~. G9 }! x& n& ]0 cIMEC, Wireless Research, Leuven, Belgium 7 Y$ j- n0 z( f
IMEC, Wireless Research, Leuven, Belgium / E3 W* b1 p$ m/ P
University of Salento, Italy2 |3 @" }) G2 w. g b- s& w1 x# G8 F
9 c% K4 `0 h, s3 D, f$ Q
) u% ^+ [4 e8 T; IContents 2 B$ d. A4 x' j; A5 v |7 g
Dedication v
5 m4 N* o1 N/ z4 U+ P7 FPreface xi
' S9 i2 H# x$ f9 zAcknowledgments xv
3 K( C" }) V* g' n8 D1 N1. 4G MOBILE TERMINALS 1
( B+ b; Y% ~! y$ M+ w: [1.1 A Wireless-Centric World 1 - m7 H' P1 @5 K
1.2 The Driving Forces Towards 4G Systems 3
% l, A; Z4 H9 a9 T+ @1.3 Basic Architecture For a 4G Terminal 6
+ M! \# |* h* f7 Y1.4 The Role of Analog Circuits 8 7 F' B( k, K8 S5 s
1.5 Energy-Scalable Radio Front End 9
3 v) L* V- o/ P& g) _7 |% y1.6 Towards Cognitive Radios 11
: z4 k4 b+ Z3 T& C" q7 t$ c2. SOFTWARE DEFINED RADIO FRONT ENDS 13 + ^6 o; t. p" s6 E& T
2.1 The Software Radio Architecture 13
- D/ l# t$ S. S) i- g: p2.2 Candidate Architectures for SDR Front Ends 16
1 P. M8 h' W( i2.2.1 Heterodyne and digital-IF receivers 17
! F% ]" ^ Z8 N2 j5 p2.2.2 Zero-IF receivers 19 ' y! ^6 B0 `2 L! h2 t
2.2.3 Digital low-IF receivers 22
1 D/ {$ W5 @1 R2.2.4 Bandpass sampling receivers 24 ) A# O0 c8 H" P0 T" X1 g
2.2.5 Direct RF sampling receivers 26
7 W" [9 j: R$ T8 O# V2.3 SDR Front End Implementation 27
# s& ], d; D& s$ c+ F# ~2.3.1 LNA and input matching 29 8 t: u5 m" y; S3 r3 O3 d" p
2.3.2 Frequency synthesizer 30 " Y9 W& X" K8 E3 h$ J! e; [
2.3.3 Baseband signal processing 31
+ V1 M5 e& f M$ }2.3.4 Measurements results 31
$ ^, B( E# x/ d( y2.4 Digital Calibration of Analog Imperfections 33
/ s4 o# K% j z- @9 [2.4.1 Quadrature imbalance 34
1 a) t' o3 [$ K: h' Z& u2.4.2 DC offset 36) X6 C5 k. y/ D
viii4 V5 Y7 ^( R; V( m0 V- J! b! ]
Contents 1 L3 C0 B: Z0 g+ A0 t n7 P
2.4.3 Impact of LPF spectral behavior 36
/ X, D( U3 X; \- h2.5 Conclusions 37
% Q8 g3 n' v6 d4 U) ^' j) z3. LINK BUDGET ANALYSIS IN THE SDR ANALOG 3 W' l& X/ R3 _6 e$ A% y2 h0 `; K
BASEBAND SECTION 39 2 ]9 L/ W! {7 k. O" s, D
3.1 Analog Baseband Signal Processing 39 6 t: `) a9 i1 F: d
3.2 Baseband Trade-Offs for Analog to Digital Conversion 40 - m& `0 a- @7 v
3.2.1 Number of poles for the LPF 41
* }! f: m4 Z, H: Q/ i# N/ L3.2.2 ADC dynamic range 42
( K" U" o1 W8 M4 q" z" t# V3.2.3 Baseband power consumption estimation 47 4 n, N+ m; r9 s7 K
3.3 Multistandard Analog Baseband Specs 48
7 m) \$ I" ^. `! B$ f4 n5 }! p3.4 Multimode Low-Pass Filter 49
, |$ x% i D* K: g: S3.4.1 Filter selectivity 50
9 |7 k7 ^; [8 B5 ^3 l3.4.2 Filter noise and linearity 54 * b4 o9 k/ t% n8 N* ?" q1 j( Y
3.4.3 Filter flexibility planning 56
5 ?8 {% ]+ g% V E3.4.4 Cascade of biquadratic sections 59
0 F0 z' G, }' b; l1 m( J6 i5 D+ ]3.5 Automatic Gain Control 62 " F* \: s. Z6 J4 ]
3.6 Conclusions 65
q9 M2 K9 d) r4. FLEXIBLE ANALOG BUILDING BLOCKS 67 / ]! S2 |2 u% o# l
4.1 Challenges in Analog Design for Flexibility 67
$ p8 c( [2 ]' q: b8 q8 x. J5 A' [' ?4.2 A Modular Design Approach 68 T0 \# o& |4 [/ H
4.3 Flexible Operational Amplifiers 70
; U0 s( n }! P2 \5 x4 s; g f/ N4.3.1 Variable current sources 70
5 B& S4 ~" j/ I4.3.2 Arrays of operational amplifiers 71
# ]' Y+ i) O% t' P4.4 A Digital-Controlled Current Follower 75
7 q2 f; u! z( _6 C4.5 Flexible Passive Components 75 * n2 V& h4 v# L, j2 a) p0 ?9 J7 b
4.6 Flexible Transconductors 77
2 B9 f$ w% L6 E1 {1 ]. g, b" }4.7 Flexible Biquadratic Sections 78 . ], h9 z" q- Z0 C/ o& ^& [- o
4.7.1 The Active-Gm-RC biquad 79 1 J: e! b Q1 h
4.8 Conclusions 91 1 D5 x( P1 g1 s
5. IMPLEMENTATIONS OF FLEXIBLE FILTERS FOR SDR # k' i: n$ F2 R; w' o
FRONT END 93
; h+ L; W0 U9 g# V& y1 C5.1 State of the Art for Flexible CT Filters 93 : L$ V8 K1 B& c" W4 d X* Q
5.2 A Reconfigurable UMTS/WLAN Active-Gm-RC LPF 94
" J1 \1 D0 d$ m, O: e0 F7 s5.2.1 Filter architecture 96 " X2 B& E$ A4 v4 G3 C4 g
5.2.2 Automatic RC calibration scheme 97 + e+ t/ Q# \& R. f* W" V' P
5.2.3 Measurements results 102" v3 _- f! N! s) X4 d
Contents. f% N v4 g* Q1 u, ^: f G
ix
7 m" Y! Z7 O, U, s$ T2 q5.3 LPF and VGA for SDR Front End 105
( T# g; |; z5 e- G% @5.3.1 LPF and VGA architectures 107 9 D: c' Z! k5 F
5.3.2 Prototype measurements 111
9 I( N1 U4 } c/ ]1 c6 j5.4 Conclusions 118
0 q2 _; I- ]; T% D1 B' {Acronyms 119 * p: i# [# T+ G! C! |5 D# E
List of Figures 123
" |$ E8 Y9 ^: J1 MList of Tables 129
o4 A$ C& h7 n. ?4 k, b3 [References 131
! _0 }9 F, y) |. B. v/ `Index 139 U+ [ X& d: ^
4 P8 _8 t, y- p+ R7 {: J8 k& t |
|