各位大神，请进来看看，急急急~~~

zhangsong123

              各位大神此设计有什么毛病吗，能麻烦你们帮我指出来吗？
% Y/ B) @7 R5 B2 a9 F- }0 q  设计要求，40秒倒计时，9秒之后3秒一次的SOS警示，我调试之后蜂鸣器不响，怎么回事，跪求大神指教！！！！
/ [) K6 b+ m, g, l$ Gmodule led_rxd(clk,rst_n,SOS_En_Sig,led,led_seg);
, D* d4 j( H+ g! q* ^input clk,rst_n;
1 g3 y' K; M- ^! r( uoutput [7:0]led;
output [5:0]led_seg;
- q6 p$ z. i# J/ Voutput SOS_En_Sig;
parameter seg_num0=8'hc0,
          seg_num1=8'hf9,
& D: X3 f' [" m" W5 l, b    seg_num2=8'ha4,
! X, q* A0 I4 o$ C2 ?    seg_num3=8'hb0,
    seg_num4=8'h99,
+ G( O$ t3 h8 I$ g% S    seg_num5=8'h92,
8 y6 T- A2 n. r    seg_num6=8'h82,
    seg_num7=8'hf8,
    seg_num8=8'h80,
    seg_num9=8'h90;
parameter seg_en0=6'b111110,
' U* K- V1 s- s4 ~" X; j8 Y          seg_en1=6'b111101,
    seg_en2=6'b111011,
+ R9 g- }# D7 [& k9 d% f: N9 i    seg_en3=6'b110111,
* W2 Q$ I% G8 d, q    seg_en4=6'b101111,
- g; G- E" l7 z2 T    seg_en5=6'b011111;
/ j4 V9 G5 y, x. u" treg [26:0]count;
* C; h/ T* \! [) I! e9 a2 @( W" Xreg [3:0] count1;
reg [3:0] count2;
1 G5 l- L8 t  u" b" y: e! `8 ereg [7:0] led_reg;
0 X0 \. r1 E/ Y: C' t# dreg [5:0] led_seg_reg;
, G' i) L1 R: aalways@(posedge clk or negedge rst_n)
if(!rst_n) count<=27'd0;
else if(count==27'd49_999_999) count<=27'd0;
else count<=count+1'b1;
wire clk_div=(count==27'd49_999_999);
always@(posedge clk_div or negedge rst_n)
1 S2 t0 J' Q; y. A" m3 k  Mif(!rst_n)
begin
1 f; }9 {3 t( [& G; Vcount1<=4'd0;
count2<=4'd4;
end
else if((count1==4'd0)&&(count2==4'd0))
. X" r& e! J8 Z5 wbegin
count1<=4'd0;
; {* q( }- v' D' D4 U% k+ ^3 Q" gcount2<=4'd4;
end
else if(count1==4'd0)
6 h) z" n. \/ z; Tbegin
count2<= count2-1'b1;
count1<=4'd9;
5 B: ]* l7 I6 O4 f, send
; k. e/ s, s3 Welse count1<=count1-1'b1;
reg [26:0]count_1ms;//
3 ^% X; `/ U' {+ Balways@(posedge clk or negedge rst_n)
# d2 n3 h+ i: N( |" wif(!rst_n) count_1ms<=27'd0;  
else if(count_1ms==27'd49_999) count_1ms<=27'd0;
else count_1ms<=count_1ms+1'b1;
: O6 I5 g/ y4 `7 p- W. Vwire clk_dis=(count_1ms==27'd49_999);//
//
reg [1:0]state;
: J$ k: H. g6 b1 y* Qalways@(posedge clk_dis or negedge rst_n)
9 R- J% J% I2 h- O8 Mif(!rst_n)
' k2 P  R+ R0 h0 V# ]begin
led_reg<=8'hff;
1 b1 |/ _6 s& y. {; V5 o$ Sled_seg_reg<=6'b111111;
; Q2 Y/ G7 E4 n1 ystate<=2'b00;
end
2 V0 o. [' H$ _/ ^1 H6 Jelse if(state==2'b00)
$ S& V) o. y9 W9 Y) a2 P) p5 g8 ^begin
6 ?- c. O& n$ |1 i  M* K  }0 t, Ystate<=2'b01;
5 X  y9 N/ J# z3 k( y1 vled_seg_reg<=6'b111101;
case(count2)
' o9 U. X; @: F4 U4 E3 D) N4'd0: led_reg<=seg_num0;  
4'd1: led_reg<=seg_num1;  
4'd2:led_reg<=seg_num2;
; u) p/ u# G% g' K* w6 P4'd3: led_reg<=seg_num3;  
4 ?: Z' n0 d9 `) v4'd4: led_reg<=seg_num4;  
* g: W7 X7 P; e& {# e4'd5: led_reg<=seg_num5;  
& M* d2 a: w0 ]5 \4'd6: led_reg<=seg_num6;  
! m) v2 c7 z( p3 B9 z( \- P4'd7: led_reg<=seg_num7;  
/ J2 B5 w( _+ C; O' B4'd8: led_reg<=seg_num8;   
7 b( g1 r3 W, C& g4 ]; k4'd9: led_reg<=seg_num9;  
default: led_reg<=seg_num0;  
8 k5 E) ~$ T2 {& M2 B; G% sendcase
( {9 ~3 u. `7 X5 Hend
else if(state==2'b01)
begin
, T+ o& ^( V& _7 P: n3 Q+ ~state<=2'b00;
led_seg_reg<=6'b111110;
  F' c" R$ F/ F) H" R% gcase(count1)
7 [6 y+ a( j4 m% Z# X3 r7 l  w9 E# k4'd0:led_reg<=seg_num0;
4'd1:led_reg<=seg_num1;
4'd2:led_reg<=seg_num2;
4'd3:led_reg<=seg_num3;
' X! Z' a) ]( W( N4'd4:led_reg<=seg_num4;
# t. Z  e, }5 }4'd5:led_reg<=seg_num5;
4'd6:led_reg<=seg_num6;
4'd7:led_reg<=seg_num7;
, }) z1 o' {  c+ w6 ^  m4'd8:led_reg<=seg_num8;
" f' k; S% F% n7 k, ~8 f4'd9:led_reg<=seg_num9;
default:led_reg<=seg_num0;
* j- X+ ?& p( \+ U# Kendcase
( _' ?- V8 o4 y. a1 J* Qend
reg isEn;
. m( ~6 D0 w+ o2 j+ l2 u1 hreg [27:0]count3;
7 ?0 D8 O/ j# Z7 f, X5 `/ walways@(posedge clk or negedge rst_n)
if(!rst_n)
+ |7 w- P- K& Y+ Cbegin
: W' V$ V3 h, G1 EisEn<=1'b0;
count3<=28'd0;
0 I* M6 k; X3 Mend
else if((count2)&&(count3==28'd149_999_999))
) a* R6 o. b- Obegin
: V( Z0 t* g+ g! v' W/ T; b9 r& _* bisEn<=1'b1;
count3<=1'b0;
- D, d; C3 r" x2 vend
else
7 X4 A0 f. e0 o, r# ?. xbegin
isEn<=1'b0;
) ~. ]6 x  G9 B6 d$ U2 w( U/ Tcount3<=count3+1'b1;
end
assign led=led_reg;
# O' C5 h. P; m" bassign led_seg=led_seg_reg;
assign SOS_En_Sig=isEn;
endmodule