各位大神，请进来看看，急急急~~~

zhangsong123

              各位大神此设计有什么毛病吗，能麻烦你们帮我指出来吗？
  设计要求，40秒倒计时，9秒之后3秒一次的SOS警示，我调试之后蜂鸣器不响，怎么回事，跪求大神指教！！！！
module led_rxd(clk,rst_n,SOS_En_Sig,led,led_seg);
input clk,rst_n;
, I2 x* C  i0 q  h5 {' M! U. O7 poutput [7:0]led;
output [5:0]led_seg;
" x/ q8 P/ e! Y/ }1 ]& ?, P1 F, g; Toutput SOS_En_Sig;
1 ~& _0 H7 z  ^8 Z! {parameter seg_num0=8'hc0,
          seg_num1=8'hf9,
3 b+ p8 x- A6 K% _# D    seg_num2=8'ha4,
    seg_num3=8'hb0,
    seg_num4=8'h99,
    seg_num5=8'h92,
    seg_num6=8'h82,
6 I! b* Q- B6 C* @7 V6 _2 e    seg_num7=8'hf8,
    seg_num8=8'h80,
" \" n8 R- h5 Q3 B    seg_num9=8'h90;
- P/ P1 h5 {  j- T8 Tparameter seg_en0=6'b111110,
" \' e0 q" H0 }4 }0 G$ r7 C          seg_en1=6'b111101,
) Z- ~- y  L9 u( \    seg_en2=6'b111011,
    seg_en3=6'b110111,
* G9 g4 }' m+ K- D9 g$ a% j    seg_en4=6'b101111,
9 j+ E) Y4 u0 V* q9 c: P    seg_en5=6'b011111;
8 a, f; @; {7 mreg [26:0]count;
reg [3:0] count1;
) K/ m) R) ~5 T' R: L# Ireg [3:0] count2;
reg [7:0] led_reg;
& u+ m2 j1 b; H) |' X" Z, Ireg [5:0] led_seg_reg;
8 f, Q( `: z; N1 W' `always@(posedge clk or negedge rst_n)
7 e. m% i/ n/ j1 O0 l( \7 D) Uif(!rst_n) count<=27'd0;
else if(count==27'd49_999_999) count<=27'd0;
6 D$ {( b0 c1 h( N3 \. \) Qelse count<=count+1'b1;
wire clk_div=(count==27'd49_999_999);
always@(posedge clk_div or negedge rst_n)
if(!rst_n)
8 k9 u4 o  T/ Z* J! Hbegin
count1<=4'd0;
count2<=4'd4;
: ~8 q& _% E4 Z; i: m& q) `  Yend
else if((count1==4'd0)&&(count2==4'd0))
: e1 B: B. j! Pbegin
9 H, E/ ~+ o) l+ Ccount1<=4'd0;
count2<=4'd4;
- Q! ?/ \' C% `! p# O/ P" Aend
" x: A8 \8 N5 K8 t1 g, J: belse if(count1==4'd0)
begin
count2<= count2-1'b1;
count1<=4'd9;
1 ^5 {/ E2 |' Q7 hend
& y2 H2 N; C6 Q% X6 e1 E- h6 c( Velse count1<=count1-1'b1;
7 x$ C( Y1 u1 \- S9 [reg [26:0]count_1ms;//
8 B. J8 V# g; V6 Walways@(posedge clk or negedge rst_n)
, h3 F* b/ N) G) z  G* gif(!rst_n) count_1ms<=27'd0;  
" A/ H) ?  W' m  W6 \else if(count_1ms==27'd49_999) count_1ms<=27'd0;
else count_1ms<=count_1ms+1'b1;
wire clk_dis=(count_1ms==27'd49_999);//
5 ^  P8 r, G/ s) T+ N$ X5 P; x//
reg [1:0]state;
. N( u+ W: f, O) halways@(posedge clk_dis or negedge rst_n)
" d$ w7 S8 t. \' X* A+ Y* P! _$ eif(!rst_n)
begin
3 F' g1 B8 B4 H. I$ Zled_reg<=8'hff;
led_seg_reg<=6'b111111;
state<=2'b00;
8 z6 }4 f; j# R1 }3 \" ~end
else if(state==2'b00)
* t- Y' b! x/ q) v7 k$ n7 qbegin
5 r, v8 D$ u' O- l( R! C1 Jstate<=2'b01;
led_seg_reg<=6'b111101;
9 h# L, _# Y7 ~( C0 b" Zcase(count2)
+ B7 x9 l. L7 G  J6 K# K4'd0: led_reg<=seg_num0;  
2 N* Z- ^2 P0 Z1 z3 P) N5 n3 g4'd1: led_reg<=seg_num1;  
4'd2:led_reg<=seg_num2;
. }* \/ q& C: C9 J. p) R6 e& }4'd3: led_reg<=seg_num3;  
* H! H; A8 b6 Q9 L2 U4'd4: led_reg<=seg_num4;  
9 E0 k2 h! R8 C0 j1 I: |$ R" r4'd5: led_reg<=seg_num5;  
, |4 z0 p+ `# `6 D. z  ^; Z0 D4'd6: led_reg<=seg_num6;  
- ]9 X1 o& t0 I2 |8 a" h4'd7: led_reg<=seg_num7;  
4'd8: led_reg<=seg_num8;   
) t' J9 m' g2 C+ T$ Y4'd9: led_reg<=seg_num9;  
default: led_reg<=seg_num0;  
endcase
2 e) v0 i" }& N- c; t7 M% Z) qend
else if(state==2'b01)
begin
state<=2'b00;
led_seg_reg<=6'b111110;
. N) J% F" l1 S# Hcase(count1)
; `! l. ?( h% z) }% [1 X4 h+ n- F4'd0:led_reg<=seg_num0;
4'd1:led_reg<=seg_num1;
4'd2:led_reg<=seg_num2;
) l# F# j5 p6 l" ]/ s; `' a4'd3:led_reg<=seg_num3;
4'd4:led_reg<=seg_num4;
4'd5:led_reg<=seg_num5;
4'd6:led_reg<=seg_num6;
4'd7:led_reg<=seg_num7;
3 I! ?. |- H1 e5 z! @" H4'd8:led_reg<=seg_num8;
7 A% {7 Y. O, Y8 ]  j4'd9:led_reg<=seg_num9;
default:led_reg<=seg_num0;
  m' f- A. t( ]/ o& i; Bendcase
end
reg isEn;
reg [27:0]count3;
. a, |2 b, C- ]0 g3 o  w2 g4 Salways@(posedge clk or negedge rst_n)
if(!rst_n)
. S6 s5 B/ p: a( y3 ?begin
isEn<=1'b0;
$ Y$ S8 j' U% _count3<=28'd0;
end
else if((count2)&&(count3==28'd149_999_999))
5 k( i! }/ p9 p9 |begin
4 `" b- H$ W( Q$ {5 K2 pisEn<=1'b1;
, \3 b& E- D7 J2 L7 d% U( Zcount3<=1'b0;
0 i- F* K- n, z4 w1 u* w9 Lend
6 e- b1 T. z# ?& Yelse
begin
5 C3 Z6 C; {  CisEn<=1'b0;
count3<=count3+1'b1;
end
, J2 d3 W7 N9 J9 r/ q9 d! yassign led=led_reg;
8 U/ U0 S2 z7 L3 {) B) `8 U4 Yassign led_seg=led_seg_reg;
8 e; I6 E" A; D3 T" O8 iassign SOS_En_Sig=isEn;
endmodule
  ~  j7 O' s- h- v/ J2 E  o0 r, {