快要被Altium 的 “has multiple names”弄疯了

SENA

哪位大神过来看看啊，这altium真让人受不鸟了。
最近自己画个图，用层次原理图进行的设计，其中还使用了 harness，结果一编译就出警告“has multiple names”，也不知道哪里出了问题，改了好多地方，包括工程设置，也都不行，上网上查找的方法也不管用。


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[Warning]        TOP.SchDoc        Compiler        Nets Bus Slice CONF_FLASH_A[24..0] has multiple names (Net Label CONF_FLASH_A[24..0],Net Label CONF_FLASH_A[24..0],Port FPGA_CONFIG.CONF_ADDR[24..0],Port FPGA_CONFIG.CONF_ADDR[24..0])        17:49:14        2016/3/9        29
) J; Z: j5 F  ~% v" M  d8 [6 g[Warning]        FPGA_CONFIG.SchDoc        Compiler        Nets Bus Slice CONF_FLASH_A[24..0] has multiple names (Net Label CONF_FLASH_A[24..0],Port FPGA_CONFIG.CONF_ADDR[24..0])        17:49:14        2016/3/9        30
[Warning]        TOP.SchDoc        Compiler        Nets Bus Slice CONF_FLASH_D[15..0] has multiple names (Net Label CONF_FLASH_D[15..0],Net Label CONF_FLASH_D[15..0],Net Label CONF_FLASH_D[15..0],Port FPGA_CONFIG.CONF_DATA[15..0],Port FPGA_CONFIG.CONF_DATA[15..0])        17:49:14        2016/3/9        31
, {" ^( k6 ]3 [5 [' D; k[Warning]        FPGA_CONFIG.SchDoc        Compiler        Nets Bus Slice CONF_FLASH_D[15..0] has multiple names (Net Label CONF_FLASH_D[15..0],Port FPGA_CONFIG.CONF_DATA[15..0])        17:49:14        2016/3/9        32
[Warning]        FPGA_CONFIG.SchDoc        Compiler        Nets Element[0]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A0 (Inferred),Net Label CONF_FLASH_A0,Port FPGA_CONFIG.CONF_ADDR0 (Inferred))        17:49:14        2016/3/9        33
[Warning]        TOP.SchDoc        Compiler        Nets Element[0]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A0,Net Label CONF_FLASH_A0 (Inferred),Net Label CONF_FLASH_A0,Net Label CONF_FLASH_A0 (Inferred),Port FPGA_CONFIG.CONF_ADDR0 (Inferred),Port FPGA_CONFIG.CONF_ADDR0 (Inferred))        17:49:14        2016/3/9        34
" L2 T9 o) _/ u! ]# \3 ^[Warning]        FPGA_CONFIG.SchDoc        Compiler        Nets Element[0]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A0,Net Label CONF_FLASH_A0 (Inferred),Port FPGA_CONFIG.CONF_ADDR0 (Inferred))        17:49:14        2016/3/9        35
4 D% S! r- _* k" ][Warning]        FPGA_CONFIG.SchDoc        Compiler        Nets Element[0]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D0 (Inferred),Net Label CONF_FLASH_D0,Port FPGA_CONFIG.CONF_DATA0 (Inferred))        17:49:14        2016/3/9        36
8 A% ~% J+ a% n" H. y8 z  a[Warning]        TOP.SchDoc        Compiler        Nets Element[0]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D0,Net Label CONF_FLASH_D0 (Inferred),Net Label CONF_FLASH_D0,Net Label CONF_FLASH_D0 (Inferred),Net Label CONF_FLASH_D0 (Inferred),Port FPGA_CONFIG.CONF_DATA0 (Inferred),Port FPGA_CONFIG.CONF_DATA0 (Inferred))        17:49:14        2016/3/9        37
[Warning]        FPGA_CONFIG.SchDoc        Compiler        Nets Element[0]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D0,Net Label CONF_FLASH_D0 (Inferred),Port FPGA_CONFIG.CONF_DATA0 (Inferred))        17:49:14        2016/3/9        38
[Warning]        FPGA_CONFIG.SchDoc        Compiler        Nets Element[1]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A1 (Inferred),Net Label CONF_FLASH_A1,Port FPGA_CONFIG.CONF_ADDR1 (Inferred))        17:49:14        2016/3/9        39
+ ~! g6 t$ Y# V9 [[Warning]        TOP.SchDoc        Compiler        Nets Element[1]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A1,Net Label CONF_FLASH_A1 (Inferred),Net Label CONF_FLASH_A1,Net Label CONF_FLASH_A1 (Inferred),Port FPGA_CONFIG.CONF_ADDR1 (Inferred),Port FPGA_CONFIG.CONF_ADDR1 (Inferred))        17:49:14        2016/3/9        40
8 M. p/ v; x  j- g" A4 X5 P! @/ D" f[Warning]        FPGA_CONFIG.SchDoc        Compiler        Nets Element[1]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A1,Net Label CONF_FLASH_A1 (Inferred),Port FPGA_CONFIG.CONF_ADDR1 (Inferred))        17:49:14        2016/3/9        41
[Warning]        FPGA_CONFIG.SchDoc        Compiler        Nets Element[1]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D1 (Inferred),Net Label CONF_FLASH_D1,Port FPGA_CONFIG.CONF_DATA1 (Inferred))        17:49:14        2016/3/9        42
[Warning]        TOP.SchDoc        Compiler        Nets Element[1]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D1,Net Label CONF_FLASH_D1 (Inferred),Net Label CONF_FLASH_D1,Net Label CONF_FLASH_D1 (Inferred),Net Label CONF_FLASH_D1 (Inferred),Port FPGA_CONFIG.CONF_DATA1 (Inferred),Port FPGA_CONFIG.CONF_DATA1 (Inferred))        17:49:14        2016/3/9        43
1 ]+ P8 ]. Z7 Y( B7 \[Warning]        FPGA_CONFIG.SchDoc        Compiler        Nets Element[1]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D1,Net Label CONF_FLASH_D1 (Inferred),Port FPGA_CONFIG.CONF_DATA1 (Inferred))        17:49:14        2016/3/9        44
9 a2 f4 M9 g% \/ `# |[Warning]        TOP.SchDoc        Compiler        Nets Element[1]: EN has multiple names (Net Label EN1,Net Label EN1,Net Label EN1 (Inferred),Net Label EN1 (Inferred),Port EN_A1)        17:49:14        2016/3/9        45
[Warning]        TOP.SchDoc        Compiler        Nets Element[1]: L_IN has multiple names (Net Label L_IN1,Net Label L_IN1,Net Label L_IN1 (Inferred),Port L_IN_A1)        17:49:14        2016/3/9        46
[Warning]        TOP.SchDoc        Compiler        Nets Element[1]: POWER_OUT has multiple names (Net Label POWER_OUT1,Net Label POWER_OUT1,Net Label POWER_OUT1,Net Label POWER_OUT1 (Inferred),Port POWER_OUT_A1)        17:49:14        2016/3/9        47
[Warning]        TOP.SchDoc        Compiler        Nets Element[1]: R1C has multiple names (Net Label R1C1,Net Label R1C1,Net Label R1C1 (Inferred),Port R1C_A1)        17:49:14        2016/3/9        48
[Warning]        TOP.SchDoc        Compiler        Nets Element[1]: R2C has multiple names (Net Label R2C1,Net Label R2C1,Net Label R2C1 (Inferred),Port R2C_A1)        17:49:14        2016/3/9        49
[Warning]        TOP.SchDoc        Compiler        Nets Element[1]: RFB has multiple names (Net Label RFB1,Net Label RFB1,Net Label RFB1 (Inferred),Port RFB_A1)        17:49:14        2016/3/9        50
6 @4 U& ]' p3 \$ @& A. _[Warning]        TOP.SchDoc        Compiler        Nets Element[1]: SS has multiple names (Net Label SS1,Net Label SS1,Net Label SS1 (Inferred),Net Label SS1 (Inferred),Port SS_A1)        17:49:14        2016/3/9        51
) \8 K! Y! n9 @0 ]4 l# Z[Warning]        FPGA_CONFIG.SchDoc        Compiler        Nets Element[2]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A2 (Inferred),Net Label CONF_FLASH_A2,Port FPGA_CONFIG.CONF_ADDR2 (Inferred))        17:49:14        2016/3/9        52
( d! K- m/ w8 `' d4 g/ n, i[Warning]        TOP.SchDoc        Compiler        Nets Element[2]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A2,Net Label CONF_FLASH_A2 (Inferred),Net Label CONF_FLASH_A2,Net Label CONF_FLASH_A2 (Inferred),Port FPGA_CONFIG.CONF_ADDR2 (Inferred),Port FPGA_CONFIG.CONF_ADDR2 (Inferred))        17:49:14        2016/3/9        53
[Warning]        FPGA_CONFIG.SchDoc        Compiler        Nets Element[2]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A2,Net Label CONF_FLASH_A2 (Inferred),Port FPGA_CONFIG.CONF_ADDR2 (Inferred))        17:49:14        2016/3/9        54
/ S8 A+ ^# E( H+ I+ o[Warning]        FPGA_CONFIG.SchDoc        Compiler        Nets Element[2]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D2 (Inferred),Net Label CONF_FLASH_D2,Port FPGA_CONFIG.CONF_DATA2 (Inferred))        17:49:14        2016/3/9        55
/ o* ]! S- H; B[Warning]        TOP.SchDoc        Compiler        Nets Element[2]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D2,Net Label CONF_FLASH_D2 (Inferred),Net Label CONF_FLASH_D2,Net Label CONF_FLASH_D2 (Inferred),Net Label CONF_FLASH_D2 (Inferred),Port FPGA_CONFIG.CONF_DATA2 (Inferred),Port FPGA_CONFIG.CONF_DATA2 (Inferred))        17:49:14        2016/3/9        56
[Warning]        FPGA_CONFIG.SchDoc        Compiler        Nets Element[2]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D2,Net Label CONF_FLASH_D2 (Inferred),Port FPGA_CONFIG.CONF_DATA2 (Inferred))        17:49:14        2016/3/9        57
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戴草帽的王子666

has multiple net警告的解决办法！
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wanghanq

一堆告错文本不如上传一个完整案例，方便网友参考学习...

xfreestar

CONF_FLASH_A[24..0],FPGA_CONFIG.CONF_ADDR[24..0]
网络标识名称不一样啊！

ttgoer

你没有写harness名字，都是用的默认的harness吧

SENA

找到原因啦。晕死，好像是因为HARNESS 必须得成对应用。我刚开始画原理图的时候，只在sheet_adc中使用了一个，与它配对的那个没放，结果就出错了，后来都给匹配了就好了。altium 还是有一些不太好用的地方。再比如说没有差分总线功能，不能单独修改花焊盘，多通道设计序号不能从0开始等等。希望能越来越完善。

ttgoer

SENA 发表于 2016-3-18 14:54
找到原因啦。晕死，好像是因为HARNESS 必须得成对应用。我刚开始画原理图的时候，只在sheet_adc中使用了 ...

可以修改花焊盘，DESIGN RULE用法没吃透。
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SENA

ttgoer 发表于 2016-4-6 14:25
5 a6 s. s' L$ o# E6 s可以修改花焊盘，DESIGN RULE用法没吃透。

使用rule是批量修改，这个是知道的。但是不能对每一个焊盘都设置一个规则吧，这样也太麻烦了。mentor里面可以手动修改，想改哪个就该哪个，并且是对设置规则覆盖的。

小翼虎

SENA 发表于 2016-6-8 21:45
+ S( e0 n! K( w4 b! ^$ y使用rule是批量修改，这个是知道的。但是不能对每一个焊盘都设置一个规则吧，这样也太麻烦了。mentor里面 ...

可以在CLASSES里面自定义PADCLASSES，再建立规则去定义连接方式。