对这段文字描述感觉有些困惑

mengzhuhao

对这段文字描述感觉有些困惑


8.0 Actual "full_case" design problem
The 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using
any synthesis directives. The resultant design was a decoder built from 3-input and gates and
inverters. No latch is inferred because all outputs are given a default assignment before the case
# T$ ?  a! ^: Q/ b/ u  [statement. For this example, the pre-synthesis and post-synthesis designs and simulations
matched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the
"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
optimized away during synthesis and left as a dangling input. The pre-synthesis simulation
results of modules code4a and code4b matched the post-synthesis simulation results of module
: j; E3 t8 d  g+ J3 w  ^) ?code4a, but did not match the post-synthesis simulation results of module code4b [2].
' f# Z  y. F0 D/ L2 z* k9 m// no full_case
0 @& G: s9 o3 x// Decoder built from four 3-input and gates
// and two inverters
module code4a (y, a, en);
  l. |  F. U" \0 k( R* j! Xoutput [3:0] y;
input [1:0] a;
input en;
reg [3:0] y;
, P: @1 S* }& e+ \8 k; g  Oalways @(a or en) begin
8 x, s) {7 ^* u5 p5 q  `y = 4'h0;
6 i4 A2 H, A1 J% n5 K4 g5 Ucase ({en,a})
( A  }3 ?9 Z' t( l/ h( b3'b1_00: y[a] = 1'b1;
9 O$ c! k: ^0 f$ G) b" N8 ^3'b1_01: y[a] = 1'b1;
3'b1_10: y[a] = 1'b1;
3'b1_11: y[a] = 1'b1;
endcase
end
. ^7 N$ z: N% r, H( {endmodule
5 p3 ]. O% f& Y& O( [% ^- I2 I4 `; AExample 12 - Decoder example with no "full_case" directive
3 l/ g0 F% {" p& n& D0 O+ \Statistics for case statements in always block at line 9 in file
. J2 @: h6 a# k- y0 I3 h'.../code4a.v'
===============================================
| Line | full/ parallel |
===============================================
| 12 | no/auto |
, ]/ m$ m  H' z5 l1 W" n% E===============================================
Figure 19 - Case statement report for Example 12
/ C- Y$ q, X- C+ z' \$ f

0 R1 [5 v# F, l* z' m7 B! M0 _2 J# ]// full_case example
- t/ Z6 t2 l! k3 f0 W// Decoder built from four 2-input nor gates
3 `; b. d9 d0 n% }3 e+ R* J// and two inverters
// The enable input is dangling (has been optimized away)
" q0 }8 e  J2 n: Y: s2 h- lmodule code4b (y, a, en);
output [3:0] y;
0 N" h1 A% N6 D, jinput [1:0] a;
# I* x7 m. ?% O9 g, [  |input en;
reg [3:0] y;
: j/ j5 D0 u# D3 L$ L$ H$ @always @(a or en) begin
y = 4'h0;
case ({en,a}) // synopsys full_case
9 K$ H8 r* _; i3'b1_00: y[a] = 1'b1;
1 v9 e& z4 A: E. t3'b1_01: y[a] = 1'b1;
& g( ]& a6 v% N3'b1_10: y[a] = 1'b1;
  k4 d1 {: w8 s; H) Z; q1 E  }3 j3'b1_11: y[a] = 1'b1;
endcase
end
endmodule
Example 13 - Decoder example with "full_case" directive
Warning: You are using the full_case directive with a case statement in which
not all cases are covered
1 M. l" G0 h' f1 ?1 Z1 d' u) A8 }Statistics for case statements in always block at line 10 in file
- H# }& m# c) \% k7 O' |7 v'.../code4b.v'
6 a! W! |* G/ F7 e- g! R0 L: \===============================================
9 \- }$ U+ F  j% z% k| Line | full/ parallel |
===============================================
| 13 | user/auto |
3 }9 L5 |- n; d) S# y===============================================
; W3 f; f1 H! e$ N9 aFigure 20 - Case statement report for Example 13

谁给解释一下原因呢?
为啥会有差异?