Verilog 使用条件生成语句实现参数化乘法器错误

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module multiplier ( product,a0,a1 );
+ }4 f/ b9 V8 |parameter a0_width=8;
parameter a1_width=8;            
localparam product_width=a0_width+a1_width;
4 }7 R# d6 `; n& J8 G( z" w1 f* m! soutput [ product_width-1:0 ] product;
$ g/ |5 s3 [# {. s  T( Rinput [ a0_width-1:0 ] a0;
input [ a1_width-1:0 ] a1;
generate
    if ( a0_width<8  ||  a1_width<8 )
       cal_multiplier # ( a0_width,a1_width ) m0 ( product,a0,a1 );
2 D! I: U: ~( T9 H: ?2 Z1 H8 t  c    else
       tree_multiplier # ( a0_width,a1_width ) m0 ( product,a0,a1 );
    endgenerate
' v- Y, J( h! t8 V8 I& u; ?; Uendmodule
4 v2 N" q/ i: p) C1 @8 ]( A
: p, |3 ~# o$ f- _Error: Node instance "m0" instantiates undefined entity "tree_multiplier"