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( ^) V' k4 g2 b) {1 F+ WI2C START / STOP Detector Verilog Code
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, o, m; P% j3 R, S }* omodule i2c_start_stop_detector (3 l& F( i/ f: S
input wire clk, // 系統時鐘7 O1 b/ u1 q2 h
input wire rst_n, // 非同步 Reset8 D) o; c6 t1 a4 O
input wire sda, // I2C 資料線1 g! s# v9 _6 V/ ^3 }( b) d: R
input wire scl, // I2C 時鐘線
4 e+ |" }5 i# P! o I! ~! y6 h d output reg start_detected, // Start 條件偵測到
; K7 y) A0 L5 [/ C* p8 J- D. z. U6 J$ N output reg stop_detected // Stop 條件偵測到
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( D6 C& d( b, C$ p: F // 前兩個時鐘週期的 SDA 與 SCL 值) |+ {6 N+ W( Z
reg sda_d1, sda_d2;
7 \7 v9 h8 l8 G8 n reg scl_d1;
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wire sda_rising = (sda_d2 == 1'b0) && (sda_d1 == 1'b1);
% l8 |' D1 X! N1 _$ e wire sda_falling = (sda_d2 == 1'b1) && (sda_d1 == 1'b0);5 I% I% p2 t2 q
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// Sample SDA and SCL
; ^; }) M# v1 N* W P! @ always @(posedge clk or negedge rst_n) begin2 p0 }! q+ y5 g' ?6 Q$ g" ?
if (!rst_n) begin
; o) `. i) S9 T' O0 W* V6 a sda_d1 <= 1'b1;
! r) F- X, z9 ]$ y& D8 e" U sda_d2 <= 1'b1; j4 _5 K6 N* s; D; i# h
scl_d1 <= 1'b1;/ C6 k. m& Z ?0 ~* O5 C: l
end else begin3 @$ m" T: x0 f: }: M- p
sda_d2 <= sda_d1;
- ^6 v) p' c$ s sda_d1 <= sda;
5 w: U1 S2 B1 v( v/ j, Q) }3 x scl_d1 <= scl;
$ j! }$ p3 l+ Y. }9 p# W# D end
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( U8 p; @9 c9 r/ @/ b E // 偵測 Start / Stop 條件
8 \% O- l, g/ h" \ always @(posedge clk or negedge rst_n) begin
0 V' u- z& I; ^ if (!rst_n) begin
! w4 m9 g0 T7 ?% ? start_detected <= 1'b0;
3 J b+ R1 A8 z5 L stop_detected <= 1'b0;1 F/ j+ m9 |- Q/ u
end else begin
9 v9 V! z4 i9 R! A/ \ // I2C START: SDA falling while SCL is high8 w( I6 ^( q/ J8 O" a) e. k- @
start_detected <= sda_falling && (scl_d1 == 1'b1); X# G' O# j5 y7 T U8 v4 D
// I2C STOP: SDA rising while SCL is high5 j& l& A( A8 y
stop_detected <= sda_rising && (scl_d1 == 1'b1);
2 \3 _7 V+ f( c" |- s6 r end
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endmodule
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发表于 2025-6-27 16:39
发表于 2025-6-28 19:47
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