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2 Y5 g! I3 ]# mDATE: 07-25-2014 HOTFIX VERSION: 032
) u, t$ S+ C9 z7 T===================================================================================================================================+ l$ `) }( `/ H& W: O$ h; P
CCRID PRODUCT PRODUCTLEVEL2 TITLE, t9 [/ F5 n+ O% t9 u1 {
===================================================================================================================================, q) z9 n" Z+ V/ D( N' d
381127 SPECCTRA CROSSTALK Specctra xtalk reports aren't correct
% h. e/ W* x8 }+ u- R, W1 w' f5 Y616770 allegro_EDITOR COLOR Remove the APPLY button in the Color Dialog window.3 e' r8 ?7 w0 `. i# R
982944 ALLEGRO_EDITOR COLOR seperate the Etch to the Shape and the the Cline in the visibility window
- D1 H) ~: v) ?( L( L982995 ALLEGRO_EDITOR INTERACTIV Shown infomation for the selected physical symbols
X; _, H( i3 d8 q: l2 t4 R5 @1024832 Pspice PROBE Shows wrong data & header when exporting trace to .txt$ ?) ^5 `( C0 @$ n, u; @
1063258 PSPICE AA_OPT curve fit fails with error same data works in 16.5 Simulation error: out of range of data& p# Y j6 [; `2 P; A; _
1112360 PSPICE AA_OPT Advacne analysis gives runtime error while using Optimizer in attached design
$ h& n* J J! |4 o2 f% `1154323 PCB_LIBRARIAN VERIFICATION Con2con is choosing incorrect Primitive from Chips file and failing FTB Checks* b& w3 w- G x9 l0 `( q
1184690 concept_HDL CORE Weird behavior of genview for split hierarchical blocks
$ ?. L9 z1 f2 N0 R9 L1212577 PSPICE MODELEDITOR IBIS translation fails without any information in log file
) Y2 l) A9 t0 V0 l1213204 ALLEGRO_EDITOR PLACEMENT Place Manually with existing fixed net behaving incorrectly
- M) d1 o& Z `5 m# u9 g6 }1213837 ALLEGRO_EDITOR INTERACTIV When copying a stacked via the temp highlight does not display on the last layer of the stack.
- w6 z0 o; U$ R! l& n; q1216519 SPECCTRA ROUTE Autorouter will not add BB via between uvia within the BGA area6 _* K8 a: o% X% X$ d& U8 b
1220655 PSPICE DEHDL_NETLISTER Support for automatic addition for Power source and Ground Node for Globals in DEHDL PSpice netlisting
0 M( c6 @/ Y _3 x% \. k2 F1223018 CAPTURE OTHER Diff pair Auto Setup not working for the buses.
- m9 h3 K, q W9 c1225689 PSPICE AA_SMOKE Smoke analysis crashes with attached testcase
/ s4 ?/ p1 P g( r1232124 CONCEPT_HDL COMP_BROWSER unable to generate ppt_options.dat file in first go/ F; {$ p( ^6 Y. t( ]
1235059 PCB_LIBRARIAN IMPORT_CSV pin_delays not being imported into PDV
7 b1 @4 B4 W: l# T8 N9 Q1238815 CAPTURE OTHER Capture doesn?t retain more than 191 library in add part/capture.ini under part selector configured libraries$ i: j2 _ X3 N+ V1 u
1239241 ALLEGRO_EDITOR INTERACTIV Via replacement doesn't replace with correct via but right padstack name.
; `6 Q5 c w5 F0 y4 Y; J9 k. v1240201 ALLEGRO_EDITOR EDIT_ETCH RPD DRC unresolved evenif HUD turns Green
! O& }1 Y& a6 J+ z/ }1240314 PSPICE SIMULATOR Getting internal error,oveRFlow for the second run6 S) m! i% q' W* S# S( X5 S; W6 g
1242805 ALLEGRO_EDITOR DRC_CONSTR no_drc_progress_meter variable hangs allegro after running update drc
Z% k& b, d f1 B* ^1243267 ADW TDA URL to TDO-SharePoint should be defined in CPM File' @5 O9 M' ]! \; T8 Q4 J
1244857 ADW TDA Policy File Variables not working correctly in policy file+ Z6 j1 X5 p; z* I# f1 y7 }
1245779 CONCEPT_HDL CONSTRAINT_MGR Obsolete objects in DEHDL CM: y& h5 i* c6 M% W9 e. }, j5 P$ \' \
1246811 CIS EXPLORER Option to keep the part type tree in CIS explorer expanded on every invoke
7 t# y; U6 j# o8 D+ b1246964 PSPICE PROBE Simulation Crashes in 16.6 but running successfully in 16.55 m! x0 \" Z3 y! u+ G1 V0 ]8 x
1248782 CONCEPT_HDL CORE Display winning physical bus names (occurrence mode) in the the lower block of an Hierarchical design
% d2 q+ h2 |3 I' I( U3 \1249238 CONCEPT_HDL CORE Uprev from 16.3 splatters text around sch page
4 E B+ q, K9 G) W( R- I2 M1249692 ALLEGRO_EDITOR GRAPHICS 3D Viewer is wrong when resizing its window.* w0 x7 q6 p- p" b0 Z
1249850 ALLEGRO_EDITOR SHAPE With shape_rki_autoclip Route Keepin to Shape DRC is created
& F" [; I/ }# Q, T1250683 ALLEGRO_EDITOR INTERACTIV devpath corrupts if edited from user preferences.' F# C/ t& q) Q* J" v5 e1 R( h+ J. z
1252059 ALLEGRO_EDITOR INTERACTIV Preference Editor is unable to delete a previous path entry for library paths0 P' ?, `2 S$ S' U; z P$ |& G, O
1253563 SIP_LAYOUT DEGASSING Not getting degassing voids when close to shape in center of design( P/ p0 m3 n2 q+ j9 K* L& H
1254319 ALLEGRO_EDITOR GRAPHICS ENH: Functionality to change the 3D Model color for more realistic view n1 F& d: ]$ `
1254562 ALLEGRO_EDITOR DATABASE Unable to delete a subclass that exist only on classes Package Keepout, Package Keepin and Route Keepin.& l# A, h. }- r& l% X. z, R
1255169 CONCEPT_HDL OTHER ADW (BPc) Packager should report the specific corrupt directive in the .cpm file
# N5 B6 [8 {+ E. i7 [1255573 ALLEGRO_EDITOR DRC_CONSTR Need soldermask DRC checks when same net via and smd pad overlaps8 o. B, p. ~+ B+ @( c1 V
1257950 CONSTRAINT_MGR SCHEM_FTB Changing xnet name on Allegro CM.9 @8 |. f. E" U2 h& J. v7 `$ U$ G
1258165 F2B DESIGNVARI changing visibility of Probe_number in variant schematic changes it to $Porbe_number
/ U3 G& l C( _8 x. C& {! j1258274 PCB_LIBRARIAN VERIFICATION con2con crash with no notification or error message* o2 v. B s; b3 V" n. C0 T/ G y
1258860 CAPTURE PROJECT_MANAGER Bug: Text Editor (File> New> VHDL File) filters characters from Text
{2 y5 R6 w; Z' C% h- K3 X4 h# K1258872 CONCEPT_HDL CORE Objects are copied (instead of moved) when moved from sheet to sheet6 L1 d6 l$ ?* j8 _; U z9 D
1259284 CONCEPT_HDL PDF HDL_POWER ( global) net does not get transferred to the published pdf
, p* m- ~, W3 v$ |8 R; O. D1259375 CONCEPT_HDL CORE Help link to cdnUsers.org needs to be changed
" e0 t* Z; A( G/ p6 b1259860 ALLEGRO_EDITOR INTERACTIV Edit > Mirror does not display asymmetrical pad correctly when the footprint is attached to cursor.
/ a% T4 [1 a0 U% ^% S1260002 ALLEGRO_EDITOR INTERACTIV Alt sym hard is not obeyed when using Edit > Move > Mirror8 p9 i9 J+ x6 @; J, F
1260006 ALLEGRO_EDITOR PLACEMENT funckey r iange 90 rotation issue
8 D- h9 r1 M: E- U# z* j1260667 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes when running AICC command on few Diff Pair traces.
- V6 } o0 d" m5 J' {1260763 CONCEPT_HDL CORE Export Physical fails with $TEMP entry in Setup-Tools
+ C- s9 F# {, a: k1260847 SIP_LAYOUT SYMB_EDIT_APPMOD Border texts seen as triangles.+ ^4 y2 z9 x- M" s
1260948 ALLEGRO_EDITOR SHAPE Dynamic ground shape is shorting to via of a different net at layer 4 & 5 in this design
7 o8 L) Y8 Z' n) O$ T* [; Z1262011 ALLEGRO_EDITOR PLACEMENT Key Properties on Component Instance/ Definition on available to use with Quickplace by Property$ ?0 ^& D+ p, w' Y$ Y" b
1262322 ALLEGRO_EDITOR PADS_IN Pads_in can not translate route keepout which specified for the all layers.3 W r1 b. C' v- X
1262626 CONCEPT_HDL CORE PROBE NUMBER attributes lost from the nets after upreving the design* d* q0 d* z; _6 ~0 l! }( O
1263592 PCB_LIBRARIAN VERIFICATION Unable to check in Schematic Model due to pc.db file- u. [$ {7 ^: ]. x8 A0 E. z( Q
1263685 ALLEGRO_EDITOR INTERACTIV Editing Photo Width value from non zero to zero allegro gives warning- Value must be greater or greater to zero
" u/ P& g" f; e; C* g1263704 ALLEGRO_EDITOR EDIT_ETCH Bug - AiTR wrongly deletes blind vias and do reroutes.
* x4 }4 ]0 D* U% t& l$ D" P5 p1265120 ALLEGRO_EDITOR SHAPE Require voids in dynamic shapes to use pad value
8 X4 f+ S" T! `5 R/ c1265275 ALLEGRO_EDITOR DRC_TIMING_CHK When XNETS are dissolved by removing the Models all Physical and Spacing NetClass associations are lost
; B U! Z. @3 _* t; L1265633 PSPICE SIMULATOR Bias point result is different in consecutive simulation run of the attached project; d4 B$ y. U; j. w( n
1266349 ALLEGRO_EDITOR PLACEMENT Rotating symbol while placement show wrong angle of rotation than the placed angle when Angle is set in Design Parameter, x$ c% E7 |* O9 W5 c _' e8 p
1267541 PSPICE PROBE pspice.exe does not exit when run from command line
! i: V9 L% O J1267707 ALLEGRO_EDITOR PLACEMENT Mirror Command - preselect/postselect bug with general edit mode& o- ^" e" x* y1 ~
1268299 PSPICE STABILITY Pspice crash on attached design
! J4 b S7 V) w0 N1270879 ALLEGRO_EDITOR COLOR Color view save creates .color file using older extension+ X4 @& T$ E3 C! f) K+ Q
1271295 SIP_LAYOUT DIE_STACK_EDITOR Die stack editor support needed for large variant combination designs.# C5 Q8 n2 y6 G7 l
1271385 CONCEPT_HDL CORE Locked property can still be added
; z5 c; g J% r1 z" g2 J5 R0 R1271853 APD OTHER When using the beta "shape to cline" command, add improved messages and partial completion of individual segs in error.
* }! v2 ~3 D, I* S( i' a1272197 CONCEPT_HDL CORE concepthdl_menu.txt contains invalid Variants menu
1 b- J d3 _# R2 n- L* [1272318 CAPTURE GEN_BOM BOM_IGNORE not working for Capture BOM on hierarchical designs.0 E6 T& t0 M: T! r6 ]% x
1272743 ALLEGRO_EDITOR PADS_IN PADS Library Translator does not open the Options dialog window.
# K: `# Y% Q7 @3 }, X& c: g1273517 F2B PACKAGERXL Netrev error - ERROR(40) Object not found in database
. V' s' B9 [9 R p5 r/ U. E1274000 ALLEGRO_EDITOR DATABASE PCB layer can't be removed
( I# O2 T+ b9 r4 p' ]. @5 E8 T1274530 ALLEGRO_EDITOR INTERACTIV Add Circle radius value changes next time using this command
7 B6 k# Q9 @. p! D2 e, X1274697 PSPICE AA_MC pspiceaa crashes when running Advanced analysis monte carlo for the attached design
6 v& c4 M( J9 F& X" q1275154 CONCEPT_HDL CORE Hierarchical Blocks lose ref designators when moved to another page
& I H* N7 H+ b" g T0 }1275724 GRE CORE AiDT delete another clines
" k' ?3 M( I2 A: t) _8 Y: \1275831 ALLEGRO_EDITOR DRC_CONSTR Waived DRCs return when using multi-thread DRC check
* F8 e3 O, {6 _' g1275834 CONCEPT_HDL CORE ERROR (SPCOCD-569) on global bus; W6 l- Q$ S9 M H' k' L
1276334 ALLEGRO_EDITOR PADS_IN PADS Library Import problem with outlines7 M9 l6 i6 I, Z; Q6 {) E) e+ b; w
1277062 ALLEGRO_EDITOR PLACEMENT Swapping parts from top to bottom Orientation changes0 b9 w6 F4 j7 i+ p) S) j
1278746 ALLEGRO_EDITOR DRC_CONSTR Package to package DRC allows place_bound_top in 0 spacing has drc in 16.6 version.' s/ ?; N) X" w1 c8 }0 d
1278804 CONCEPT_HDL COPY_PROJECT Copy project crashes: C& S3 F2 z6 }; z& C1 b. }/ e; c
1279362 ALLEGRO_EDITOR INTERACTIV User skill file makes Allegro Icons gone away" n2 h3 r' R }7 P' p* U7 N' K2 F
1279619 ALLEGRO_EDITOR DRC_CONSTR Netgroup in a Netclass doesn't inherit Spacing Cset
5 ~' y( a7 @& j1279815 CONCEPT_HDL CORE Text > Change and RMB Editor does not allow multiple text edits
/ |2 V9 Z6 D8 J6 |0 z2 ^1279876 ALLEGRO_EDITOR DATABASE Using the Curved option in Fillets results in a pad to shape DRC
; ^* i( I# [* v1280435 F2B BOM BOMHDL with variant repeats the PART_NUMBER value1 E3 F$ ^4 t# t5 M- f+ S/ \ s
1281669 CONCEPT_HDL COMP_BROWSER Match Any radio button in Component Browser didn't work.4 `; J: m8 P$ P9 e
1282001 ALLEGRO_EDITOR DRC_CONSTR Updating the DRCs on this design cause the DRC count to change on every update
! @2 Q0 `/ s9 {; I0 v- ?; x" m" `1282480 SIP_LAYOUT WIREBOND Info on the Wire Count property needs to be updated indicating that it is a User Defined Property7 B" ~. b* R( ?9 P* E5 o8 H
1283952 ALLEGRO_EDITOR PLOTTING Published pdf does not show dotted or phantom lines
, w' b7 a, N! D) f1 Q& _/ Q- t& ^1283957 ALLEGRO_EDITOR INTERACTIV Replace padstack in "Single Via Replace Mode" is changing netname of the vias with the latest hotfix of Allegro 16.6. N7 I- R ?7 B/ _# _% E+ U
1285588 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase control has wrong analysis result when add rectangle test bead in Clines.) U& W4 C* E' Y3 ]
1286743 ALLEGRO_EDITOR SHAPE Getting copper islands in the design after running the Delete Plating Bar command$ B+ ?: c" z8 T) K8 }) A
1287215 ALLEGRO_VIEWER OTHER Allegro viewer plus does not support constraint regions f: x* g: {1 q: U% v C
1288808 APD LOGIC Derive Assignment stalls out or won?t finish and appears to run out of database room.
0 e5 |' ^* u( e- I! }4 S6 n+ ^7 L, e1289251 ALLEGRO_EDITOR SCHEM_FTB Pin escapes (clines and vias) not inheriting new net name from a pin with a new net name.
2 h" z5 W2 k" Z1289293 F2B DESIGNVARI Warning 04: Cannot merge the variant properties on variant instance C119 component with same canonical path not present! F$ |* J3 L+ b; T
1289809 SCM VERILOG_IMPORT User not able to import a verilog netlist into SCM
7 g7 m" A p' Q, |9 K, q0 v" ~2 t0 `1290696 CONCEPT_HDL CORE Copying a net name repeatedly causes it to go off grid" o! x& g0 [+ _
1291162 CONCEPT_HDL CREFER crefer crashes when selecting generate cross refernece for all nets selected) z/ V8 J5 I7 J* M
1291285 SIP_LAYOUT IMPORT_DATA Replacing a Die with the Die Text in Wizard causes some Clines to Shift, creating new DRCs.
}8 j7 z$ u) u2 [) D1 M/ ]' q8 d1291658 ALLEGRO_EDITOR INTERACTIV Cannot add Frectangle to Group
0 h) I8 y8 u$ h+ d. F& A. Z! Q! L1292180 ALLEGRO_EDITOR SKILL Allegro Crash while performing query contents of "Maximum_Cavity_Size" with the skill command 'axlDBGetPropDictEntry'
2 ~) |% Q* o0 ]& A1 Q1292210 CONCEPT_HDL CORE DEHDL crash if design was opened with -nonetlistuprev option.- t8 S8 T4 V; k
1292278 SIP_LAYOUT WIREBOND When creating Wirebonds by Importing a Wirebond File, (wbt) the wirebonds are not on the correct Die layer
]* B2 l# O& a4 s1292282 SIP_LAYOUT INTERACTIVE Getting Multiple GUIs when the Wirebond Import is open and we select outside the command GUI.4 E& e ^# y" u9 n' {8 _& Z
1293381 SIP_LAYOUT IMPORT_DATA Import SPD2 error
3 ^* F$ |) A4 L; ?; h1293889 CONCEPT_HDL PAGE_MGMT page name regression result deleted by netassembler3 o7 O/ j, Y8 N7 I2 { b
1294124 ALLEGRO_EDITOR INTERACTIV Samsung Mobile division wants to disappear the grids in the display window when zoom-out function executes in the allegr
5 c+ [1 z6 U3 l1294749 ALLEGRO_EDITOR ARTWORK Null pad is flagged as an error that break Thales automatic tape out
9 G, j- n# l0 y3 n7 X3 t1294777 ALLEGRO_EDITOR SYMBOL Mechanical symbols missed on STEP result$ K3 X9 @% u3 r6 I) F' G1 }, V( l) Y. O
/ V# S) i) Y& M/ H4 EDATE: 06-20-2014 HOTFIX VERSION: 031( B( b( A8 \/ b4 i: |- Q% A
===================================================================================================================================+ e2 ]0 p' L& m' V' Y
CCRID PRODUCT PRODUCTLEVEL2 TITLE
0 i. |3 [) _ j& E1 L; I===================================================================================================================================: C+ @% W) L* I3 U' j( ?+ f" Y- c
726553 FSP CAPTURE_SCHEMATI Method to select bus bit?s order while generating Capture design from FSP.
q( ~, x2 o/ H" B ]1257631 FSP DE-HDL_SCHEMATIC Schematic Generation selects incorrect symbol version
. _; J+ P9 I7 D/ C/ q1273456 ALLEGRO_EDITOR PLACEMENT Place module instance causes Allegro to crash
2 R) ~/ Z8 S# B: Q( @1277099 ALLEGRO_EDITOR INTERACTIV Clines and pins are disconnected even though they are at the same x, y coordinate.
2 ?: W# J* d; C- F" b* ~! I1280913 ALLEGRO_EDITOR EDIT_ETCH Add Connect should be able to be made by go straight even though the cursor is not exist on straight line4 V) _. i& i& S! S) r* p
1282491 ADW PURGE ADW PURGE is removing Page Name data in DEHDL
6 g. I$ L! r( k& B; f0 Y. g5 i1283045 ALLEGRO_EDITOR DATABASE Ecset not getting downreved.! `2 R `" z7 c* Z
1283138 SIP_LAYOUT IC_IO_EDITING symed app mode chooses wrong text block sizes for I/O driver inst names1 v q5 E8 o1 N( q( {" s
1283227 PDN_ANALYSIS PCB_STATICIRDROP Enhancement request to add 32 bit files for IRdrop! e+ {, j7 N0 k! X
1284656 CONCEPT_HDL CREFER Crefer fails on large design
# e" J+ Z8 s9 l2 r! m+ T" ]1285814 CONCEPT_HDL CORE DEHDL crash on opening the Design* D" V2 ~( [1 Z1 n6 d( ]! j9 g2 o
1285967 ALLEGRO_EDITOR EDIT_ETCH Slide via in circle pad
( g: c; s" c' Q' Y* v1 l% R% R- c# ^
! K4 x3 y! ~! f, t3 ]DATE: 06-12-2014 HOTFIX VERSION: 030% J: E* B6 t" g
===================================================================================================================================
$ G2 O6 v; w$ ^CCRID PRODUCT PRODUCTLEVEL2 TITLE
" O* L1 e: G9 X) r0 S' Y===================================================================================================================================
' j9 J. u' p/ |982961 ALLEGRO_EDITOR PLACEMENT Show the Rats when one selects physical symbols to place them
, D1 a; B U" Z1138680 FSP POWER_MAPPING Ability to assign decoupling capacitors in spreadsheet like application9 { n: p6 X; U8 y$ g( y8 _
1243410 SIG_EXPLORER EXTRACTTOP Circuit topology extract failed in case of CLASS
) o/ l; e( O# t2 [. l9 \1262977 ALLEGRO_EDITOR TECHFILE When importing a certain tech file into an empty .brd Allegro crashes., t; ], Q3 i5 b* y4 h6 R# z; A! ?9 N
1267558 ALLEGRO_EDITOR INTERFACES Arc part of symbol pin missing in 3D view of step model
8 |& w1 @4 _( }% \3 T7 q1268252 ALLEGRO_EDITOR GRAPHICS step place bound issue(3D View)1 y; ]5 \$ o7 |8 J) b- \
1270450 ALLEGRO_EDITOR INTERACTIV footprint add line on line crash
8 ]* l* S2 d, @1 @1270962 CONCEPT_HDL PDF PDF Publisher command line does not print pdf file if double back slash is present6 H/ R! {8 D" [0 C, [6 V
1270964 ALLEGRO_EDITOR mentor Mentor translation crashes with no errors in log file, Q5 ^& e! g) ^: a# K
1270999 MODEL_INTEGRIT TRANSLATION ibis2signoise Issue/ Z( t* a3 e. {: l
1271543 ALLEGRO_EDITOR PAD_EDITOR Library import reporting missing padstacks
$ g# h9 O( `$ V6 o3 _! \1272099 ALLEGRO_EDITOR GRAPHICS Plotting does not fill shapes
1 u4 [) a& a( f8 z% }7 O- x( ^* T1272406 ALLEGRO_EDITOR DRC_TIMING_CHK SKILL command 'axlDBTextBlockFindName' returns 1 when nil is expected" i* [" Y( H8 f9 {" ~8 U! {
1272748 ALLEGRO_EDITOR GRAPHICS 3D viewer crashes on this specific testcase: N, ? s; m* q$ @* | n
1272793 ALLEGRO_EDITOR GRAPHICS 3D view doesnot displays hole with offset correctly1 v9 W3 d9 o! c2 V# {- {
1272863 ALLEGRO_EDITOR INTERFACES Ability to find the origin of STEP File in order to place it exactly where it needs to be on footprint during mapping.2 R+ o6 k" l( i/ S. U" D
1273264 ADW COMPONENT_BROWSE hyperlinks not recognized in the component browser2 f2 Q' P! r/ J- Y8 p/ u, g
1273304 CONCEPT_HDL PDF Publish PDF from commandline does not work if there are spaces in the Path8 @' W6 E2 Q4 [! x% g: ~5 z) p
1274661 CONCEPT_HDL CORE I can't copy a property from one component to another
% x* c: r8 C3 Z/ D B. c3 s+ E1275237 ALLEGRO_EDITOR DATABASE Allegro Crash on running DBDOCTOR for a board
& {+ k7 d! a B, ]0 h1275345 CONCEPT_HDL CREFER The Xref information page number values are incorrect E7 q! q8 I/ |7 ]* v
1275748 APD IMPORT_DATA WireBond starts away from the Die Pin after importing Die using Die Text In Wizard. q$ A$ w7 o* M, V& _
1276270 CONCEPT_HDL CORE DEHDL crash by Zoom In > Ctrl+A > Move
8 {4 B0 u# O, A: `1277735 SIP_LAYOUT IMPORT_DATA sip layout spd2 translator issues with offset die and mirroring$ x \: v3 [+ \/ i1 Y
1279258 CONSTRAINT_MGR OTHER Import logic stops with error9 T% q3 z0 x0 u. }" ]# `/ c
1279694 ALLEGRO_EDITOR SKILL axlCNSSpacingMin('via nil) crashes Allegro PCB Editor9 I F! }4 U. L3 l$ [/ Y+ `
% T: L1 c' z3 A1 L$ w& PDATE: 05-23-2014 HOTFIX VERSION: 029
" o# t* G' o4 G; ?2 ^) z |===================================================================================================================================
: K* L1 y. J; jCCRID PRODUCT PRODUCTLEVEL2 TITLE+ U' X$ }" f6 Y9 v* N
=================================================================================================================================== G, T0 |7 G, H
1209461 FSP DE-HDL_SCHEMATIC Hierarchical Block Size not automatically adjusting to text needs
) a; h/ ?. j% f* ~+ z# |3 K/ R; ~1217832 SIG_EXPLORER SIMULATION S-param generated by SigXP doesn't match with HSPICE/ADS.
8 [+ q( U% ?9 w+ d9 L1263575 CONCEPT_HDL CORE Copy-Pate makes Components Off-Grid
8 M1 c; N. l# f' s, K* y1267602 SPIF OTHER Route Automatic hangs. ?, R: g* _" m
1268022 FSP PROCESS FSP is not respecting the use banks for attached design.
3 Q# i8 D& k$ ?# |1268587 ALLEGRO_EDITOR INTERFACES Enh. Preserve relation between hole and padstack in IPC-2581$ z7 O! z! s0 ?: \( ^
1268918 SIP_LAYOUT DIE_ABSTRACT_IF SiP - DIE export from co-design object to XDA results in missing data
' _& D7 v/ G, p. j) s. s8 h2 h) Y1269232 CONCEPT_HDL INFRA While pspice uprev the design crashes
6 O j. V9 t4 P. G1269825 SIG_INTEGRITY SIGNOISE PCB SI hangs when running crosstalk simulations5 X8 A1 X+ y* \ p5 B4 G- w
1270963 ALLEGRO_EDITOR GRAPHICS Add Circle lint font hidden/Phantom has resolution problem
: H0 F# p% N7 Y- Z$ e1270990 ALLEGRO_EDITOR GRAPHICS Allegro response is slow when added circle) V/ r$ B, x- e3 s* ~& u, u% B. b
1271655 ALLEGRO_EDITOR MANUFACT Dimension option causes a generic crash, reproducible in any design8 o1 O# `' m' w. x9 N: m# z! |& C0 ?- t: S
1272495 ALLEGRO_EDITOR MANUFACT Filtered Part numbers in IPC-2581 still pass actual part number for references onutide of BOMItem2 S$ V$ K( b, @8 P. e" N0 g1 ?
1272839 ALLEGRO_EDITOR MANUFACT Kindly explain the drill legend behavior when padstack rotation is 45 degrees and mirrored ?, t5 N# K: b$ H* g( k
1274518 ALLEGRO_EDITOR ARTWORK Artwork does not create void correctly.
! h! M) S' C1 i& A- {2 L# H3 A9 L
DATE: 05-10-2014 HOTFIX VERSION: 028
: b" Y0 P# ?9 T/ a" p$ c===================================================================================================================================* D9 v3 R2 Y: V
CCRID PRODUCT PRODUCTLEVEL2 TITLE O' z5 a# d- ~8 t
===================================================================================================================================
# C! Y" |8 Q) L, |1 q& {! z# X1199256 ALLEGRO_EDITOR INTERACTIV DFA bubble does not appear when moving a symbol to within another symbols dfa bounds on specific symbols
+ ^' O' x& f) B: d& ?: {1 z1220196 ALLEGRO_EDITOR OTHER create xsection chart results in ERROR(SPMHA1-73): Text line is outside of the extents.
' G" s+ {# ] N- o- a+ b1259520 ALLEGRO_EDITOR EDIT_ETCH Allegro will crash when adding connections to a differential pair.
0 g. b3 V7 C8 V. K* J) d1260446 ALLEGRO_EDITOR VALOR Creating odb output the xhatch shapes where arcs are will become inverted. Difference in the geoms.out extraction?- t) H$ O2 `" X6 K
1261313 ALLEGRO_EDITOR INTERFACES Step mapping does not show all Available Packages+ Z5 O/ A4 h J& l X
1261356 CONCEPT_HDL CREFER crefer is crashing with generate for all nets option
* b. K( a+ @/ _, \, \1261514 ALLEGRO_EDITOR ARTWORK Exporting raster artwork with overlaping voids fails.' q9 H" U g( `. x$ D* E( v, j$ `
1261735 ALLEGRO_EDITOR ARTWORK Presence of Smaller shapes inside bigger shapes is crashing artwork generation.3 N6 {! a. l# J4 X# h6 y2 y( i* d
1262019 ALLEGRO_EDITOR INTERFACES Artwork control form hangs if we close PDF publisher gui
7 ]. b5 D l1 ?, t3 v/ H; u% j4 I) o1262246 CONSTRAINT_MGR ANALYSIS Constraint manager shows ALL PASS when Adding members to a NetClass and adding parallelism rule, h0 p. g3 v+ }' |* n7 s, P: V! H
1262560 APD WIREBOND bondwire can't connect to GND ring directly) H# v& [+ X& I% y( \5 w1 i
1263275 CONSTRAINT_MGR OTHER Import of constraint file hangs in this design" W( @0 _' v, |7 O% D) n
1263358 SIP_LAYOUT OTHER SiP Layout - Void adjacent Layer enhancement to merge voiding for PADS without changing shape params
- z' p6 F0 \( e8 u q @8 V3 ^1264109 ADW LRM LRM error - WARNING(SPDWREV-7): Unable to read the design2 w# p0 e6 m: ]1 [' b
1265580 APD MANUFACTURING Icp_soldermask_allow_pins cannot create correct solder mask when the pin rotate.; e( j- n" h- A
1266391 APD LOGIC SPB16.6 Derive assignment : want to select 1 DRC marker only.
5 R" \. X" N9 X4 o1266687 ALLEGRO_EDITOR SKILL The SKILL p
7 ?- a K( R. ~1267267 SIP_LAYOUT WIZARDS Attempting to create a die using the die text in wizard but the tool is not creating the correct die outline
. u" e ~% K0 M" P/ m1267308 SIP_LAYOUT OTHER When updating a BGA with the Symbol Spreadsheet tool it will start, update a few pins then stop.. e; N9 G/ L' i; F9 ~
1267639 ALLEGRO_EDITOR PARTITION Allegro crashes when partition is created and opened from a location that contains "!" in its path.5 l" P8 q" V& S& ^, a3 z4 A3 A
1267704 SIP_LAYOUT STREAM_IF Cannot import stream file, the tool starts scanning the file and never stops.4 l! {! J$ y: p
1267907 CONCEPT_HDL CORE Ctrl+RMB Context Menu Option doesn't work.
; Q( |+ y0 w7 j- r: a8 Y3 e5 @6 w
3 ~% Q& p( {, s& x: Y. yDATE: 04-25-2014 HOTFIX VERSION: 027
+ j( s3 f/ A0 ]+ M5 }- T9 V1 E% i9 b===================================================================================================================================9 I c1 ^! k$ Z1 k, Z
CCRID PRODUCT PRODUCTLEVEL2 TITLE
( h. F8 q" E: d' y6 y===================================================================================================================================
+ \* K. s; _/ h$ x, R/ W308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM- N7 u# g! N d% c3 i: Q( B
481674 ALLEGRO_EDITOR PADS_IN No board file saved from PADS_in! L! x/ }. G( M0 e
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.0 G5 Y1 X! b$ ~3 J, } E' d
1012783 FSP OTHER Need Undo Command in FSP
( I0 R4 j) m$ e1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.
6 T1 z; X$ z8 c; {$ O1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
?, P! Q. h+ X) y2 g3 V6 q1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.0 ^ m( U4 q" k* W* @
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups: s3 f) t" B8 x. J
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
! S* P% t5 m. e, \- F; q0 L5 m1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
2 C2 [- ]- |1 b/ V1 c* J3 D S; P1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
, w/ h1 |3 G" |5 T! D: s/ ~1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
. N: R! H* Q* M1 L! g; Z1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.% t. Z6 a7 `, K% `# H) `) P+ s3 y7 o
1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings: D& J6 [( T! V- p! }; p
1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
/ ? T9 r* R: D4 |, d1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
9 k5 y" _% L: p# g, D" H7 h1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
; | C" O, [+ H& p4 F7 h: I9 ?1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
9 n9 `- z I6 U% I1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime
8 @' Y" e2 S5 g; a1208478 PSPICE PROBE Attached project gives overflow error with marching ON.- O |# ^( K% P5 A3 r
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol
* [! |- c( `- F3 Q% a8 g; `0 G1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed, n6 r3 U1 B, E3 e3 h
1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape& Q- v& D+ W5 J0 a8 `8 p9 O! H
1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers5 P# A; ]+ k" e% x$ k; L" ]
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?/ H* x" J! ^! H7 ^1 j% v
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.
' N' H, K. B8 B; o, s# N1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values
8 S- S+ V' ?& h6 n1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging
% g' A9 h* M g2 I! r& a1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
6 P) r+ M8 T+ Z; A8 ?1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added2 N7 h2 c K" ]. F/ X' C
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.% F0 N8 e3 F# t G
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
( T- V3 t% @, e. |# y3 A( C) L Q1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux+ L1 ?. o4 u* f; R3 D
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
, j/ ~* N" z4 H! \3 B$ ]: z: j% s1221182 ADW TDA Team Design with SAMBA
' U- {) @' H0 [' G! v/ O x& f1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair- @. P# ~$ T* A* z
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
9 \) s; @" H1 v' W4 a! M; \+ o2 Q1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?0 N! t$ L: i$ ]. Z4 l# g# D" |
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
7 x0 g. C" i" K8 E9 K& L0 W' K1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms- _( z! d; m" f b/ i$ ^0 {
1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
+ U! Y: G7 [' `: o+ Q4 F; y+ Y1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor
1 G: k) ?+ ~# b. g0 A1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines., m2 h& b. w+ v9 v X
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
8 r/ P6 {, ?9 g( b1 P1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin" H; q6 J/ G0 M' L8 w1 c9 s9 y
1225494 CAPTURE DRC Different DRC results for Entire design and selection; c9 b* S. G7 H
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property' Y/ ~0 F2 k9 G: i: O5 a
1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
8 m% X6 z, Y; z1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
% m$ Q+ W/ X8 @( j6 I1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts� function is inconvenient for Global Signal
8 ^2 H- Z8 f4 o v1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
) L, ]6 L8 v7 R Z2 ]+ u, S0 \1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
. h h! W) E; M6 U- J1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
' D, Z- e' w# U! ]1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration
5 @& d* u/ Q& W) v( E! g" C1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part
6 s# \: O0 q2 x& F' ?1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case G; H# z; }% c
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins( b0 f# @, Y" r T, c
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
1 I" o, \7 F' ~$ n" }! w p1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.+ c+ T% r) H/ B0 W+ X% @8 U- |
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
6 c# a$ k$ E: {0 ~7 Q1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
4 B) k2 C; e7 [- w/ u* `9 A1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
c' A' M* K3 d# z, ~2 u( y6 M1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
8 P+ v; x: h, h2 H/ m4 @1230432 CONCEPT_HDL CORE No Description information in BOM. C( {; c% E/ d6 }
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes: p7 @3 k; f* {) a5 j
1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files
: ~1 c4 c }( |/ l5 c* ~1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands) d4 W6 X T% _2 o
1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets
6 e$ {9 f5 e; h) M/ O1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
& Z& g N" ]7 j0 d1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode; @1 Q$ J$ Q% s
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical0 T; j3 o& c2 y# w! T
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode' ^% D$ A9 b! s
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files% {8 M) s9 O; G9 \$ @1 c1 S' x! h
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy* @: ^" ^& h' S( `' c! {
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved4 w/ c' v2 u; f& z
1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect- K' R9 t7 a! u8 U8 x4 n
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
* ?8 ?8 y( r% K1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
% g8 c; g0 x1 P4 D7 {1236161 CONCEPT_HDL CORE Import Design shows the current project pages' b# m6 |3 S- s- _( R4 ]
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.
9 q7 _# O3 Y5 ?" P* Y0 M4 c1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion: i; {( {( k2 Z p. e; @
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file% t$ `) V1 z3 [7 J) p
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape( U$ ~9 z$ c% D. ]0 |0 i: g' _
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming
# V4 a% g) W7 d' @& @5 n1236781 F2B PACKAGERXL Export Physical produces empty files3 M$ c0 [7 N) E
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run. H1 s$ b# F* ?
1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib� command5 P$ q$ j# E# K1 D! @" ^5 b
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
* Q* Q4 i; f; H, u2 }6 S1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager., J d# ?, |0 x, o
1238852 CAPTURE GENERAL signal list not updated for buses: Z4 V& F L2 t# N6 t' S4 `
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes
5 g6 R5 ~1 X A. E* r1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
! `( a U K4 {; O* l6 g1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE
/ }7 [3 V1 [2 ?& x: d, N/ @1239763 PSPICE PROBE Cannot modify text label if right y axis is active- Q9 H, }! N, h
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images. a# c' C4 J0 n/ l" q' p& m
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.4 I( Z R3 q! i# M# D& r
1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing c2 K7 s( a( [
1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file3 m) z) _' Q- R V# X0 T
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable! w8 S" b2 H% F0 C5 a
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy
6 `/ Y- g j: d9 [ U+ I+ f1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
0 T$ B7 H8 k$ B! C; Y$ _/ S2 D" ]& n1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working
+ e0 b( u3 d( H8 R$ Y1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
! n6 ]- A* ^, V' ^+ D8 I$ b+ t1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
% U: R- A( a/ s7 K7 u7 q1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
$ W4 d5 N& Q* l8 P( j1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side( c3 w; {( F, y$ o
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer% c% ^4 U8 O# j0 |
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results) u" }6 ^6 v( A: o& O" O7 [- M
1243609 CONCEPT_HDL CORE autoprop for occurrence properties P; X% n. s- \$ Y! x
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI$ Y9 [6 }, V. s7 V
1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.7 Q' [9 z( g e7 c4 H1 `
1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring% `* H+ c& h9 k' n; M' Y$ }- x
1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder; {# y; x: s- d! u/ \% b* V ]
1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is. U. ~" f8 x) X2 T
1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design& Q4 I% p+ U N
1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?
/ A5 ?/ ]$ o. r9 `( r; s1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character, A5 Q! s1 @4 h4 r# h" s/ j+ m7 Q
1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters8 E$ M( p- Z; \+ C
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown ]" D( E, i/ {: ?6 t3 ^4 k
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number" H+ `5 V2 N" a; ?! f8 o
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
' i, D8 J2 |7 s2 `% N9 L1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained
5 O$ i2 X0 B" a7 G/ ?1247462 CONCEPT_HDL CORE Text issue while moving with bounding box
# K; M+ G- `) i) y" h1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered. q/ h, j% k7 W$ I& P/ R
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components+ x: t; y5 @; J* d- I4 ]: p: c- J
1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts
+ i9 a7 _; B# _1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
6 }$ a! i7 G( ?# L2 e# \, m1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
7 l/ Y% q' y( F2 k7 Q6 N+ e+ l. w1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly7 V' Y0 V0 T; E. ?3 B
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
# @: H( B9 t5 p1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
) [& z/ Z$ S6 }5 T1253424 SCM SCHGEN Export Schematics Crashes System Architect* ~- _" `2 E0 C4 Q; s
1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled
( i7 J9 k# I; q5 N7 M1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing* A2 S) d1 d- s8 x! ^
1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router, B0 _6 T1 [- J y5 N
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error1 L% g% b, q7 c4 Z
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.: f, I W' {. v) q1 n+ B8 q, l
1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation$ I3 s8 [* Y: p! ?8 D. \
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects
7 q: k7 A, k+ l G/ e" d1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
& C, Q# [( e0 F2 ]2 [: i( N0 [! }1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
# Y# w! v! t) V( c8 m1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
K+ e$ @5 p. W* A; i5 z1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool/ L( ]$ X, K) d( T5 n0 `/ C
1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design
U" \7 s' F) G( c. K4 } V1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library
& s. f Q5 L! z, W' o! q# ?1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long1 {1 n- e7 P Y8 M
1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash
$ z/ J" h8 Z$ [% P$ T1 |2 ^1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time, f) V5 z; j+ e# I
1258029 APD WIREBOND The bondwire lost after import the wire information
. E8 _1 p" I( H' G$ F# v% p1258979 APD NC NC Drill: There is difference of number of drills.* a7 z% N( v9 G
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement( C/ O/ z: a$ q$ w) [
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
; o, F% d# n: Z8 c( f1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"' H K% q1 n" I7 R2 k6 Y: M
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines
; J: V1 O# m) M, A; n1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void5 O7 r6 |! L$ [* o& T/ ^9 \5 B
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss# A+ H% }. T0 Y7 s, T
' a8 \: |) M3 ?5 w
DATE: 03-28-2014 HOTFIX VERSION: 0261 K' z; ~8 ]& N& E9 G U1 z
===================================================================================================================================8 Y1 D6 |# Z+ Y6 K5 u
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 q w8 L: a- t===================================================================================================================================$ x% @/ e. G4 m( A) Q
1190942 CONCEPT_HDL CORE Cannot copy locked .xcon files
: T, ?8 O$ ]; r k! |1226085 F2B PACKAGERXL Winning net NC shorted with loosing net due to PACK_SHORT4 G$ E$ e" U4 h/ Y$ L
1244894 SCM SYSTEM_OBJECT Get packaging error when adding a pullup/pulldown resistor
: w- Y/ F, W5 w2 x- n/ v% J( @" Z" X1247432 CONSTRAINT_MGR OTHER PCB Editor crash
' k5 _1 ~; p! k% _ Y! v0 @1248560 F2B DESIGNVARI Variant Editor > Help about for S024 says unreleased ?
6 P% L) k. n8 B. z* ?- J; [/ l9 k1248712 SIP_LAYOUT WIREBOND Changing the charecteristics of a Bond Finger causes it to shift position+ d n2 Q' U( x0 d1 C8 S% `
1248839 ALLEGRO_EDITOR OTHER 16.6 S023/024 crashes on Logic Change Parts command.
" Z: W* s% H& p, {$ W- m+ P: j1249000 SIP_LAYOUT DIE_EDITOR unexpected shift of instances/pins by co-design die editor' ^. ~& t) o5 \4 s3 P$ R
1249186 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 ignores property UNUSED_PADS_IGNORE
( p l6 ^8 n( k* e. l7 o1249272 SIP_LAYOUT IMPORT_DATA film resistor pins/pads are created on the wrong layer. Always synthesized on top cond layer regardless of config file/ X F' u7 F5 g% }! a# [" h- I
1249792 ALLEGRO_EDITOR INTERACTIV Cannot place rectangular shape as per included width and height.- |/ c9 Y- G: U3 X) y0 y
1249801 ALLEGRO_EDITOR INTERFACES Bug - Arcs in IPC2581 export are corrupted- Q3 G8 v: f3 i q* q7 t3 q
1251006 ALLEGRO_EDITOR INTERFACES IDX does not recognize PKG_PIN_ONE property
3 y+ B3 X8 r% a/ `+ a& t+ V1252142 ALLEGRO_EDITOR INTERFACES Remove inappropriate Conductivity specs from the dielectric layers from the IPC-2581 output, {" e, k3 t) |6 a1 w: V# l6 q9 I% f
1253047 ALLEGRO_EDITOR SCRIPTS Bug: SAV file when creating symbol! y' n3 Q* y: _4 b) }& D4 ~
J4 {* Q+ U( U1 bDATE: 03-13-2014 HOTFIX VERSION: 0255 \8 H! n8 X4 I5 V* q
===================================================================================================================================4 u5 A& G3 C& O
CCRID PRODUCT PRODUCTLEVEL2 TITLE
* |: m }! U5 V===================================================================================================================================
# y/ n) C/ {2 ?, u9 @$ j1194646 CONCEPT_HDL GLOBALCHANGE Global Update > Global Component Change does not work+ J* l4 p: g9 v* S, M1 h! E3 q
1227843 SIG_EXPLORER EXTRACTTOP Cannot extract the topology correctly.) C2 Y$ d/ A; k: f
1231510 ALLEGRO_EDITOR INTERFACES IDX exchanges with CREO 5.0 issues* Q8 y1 |. \, |9 N: M3 y& t
1233030 SIG_INTEGRITY GEOMETRY_EXTRACT Net Parasitic of ground Connection
; D- J$ M3 d7 v+ F# l9 V' D6 [* K8 q* f1236961 SIP_LAYOUT OTHER Moving component using Place Manual -H causes mirror_geometry.
6 H( X/ o# ^ y5 a1241456 ALLEGRO_EDITOR EDIT_ETCH When creating Die pins or changing their attributes an oval is placed on the pin
0 I9 ^ |5 m1 Y; a# m ^1242461 SIP_LAYOUT OTHER SiP Layout - DIE is being mirrored when placing
: F/ a2 {( {5 Z( c: j5 q, A1242682 CONCEPT_HDL PDF PDF Pubisher crash DEHDL on design
4 K. b* x; l$ `5 ^8 D( o! b8 y1242685 SIG_INTEGRITY SIGNOISE Incorrect net name was displayed/output if the net include consecutive underscore.
, _* s2 ~2 a) Q6 ^8 U1243357 ALLEGRO_EDITOR INTERFACES Ability to add any new name
& R/ @ n0 `" I+ K/ @1243758 ADW COMPONENT_BROWSE I don't see an option to switch between database and cache mode2 |, J. E+ ]- n7 U1 w( z/ \: O1 `& E
1244325 ALLEGRO_EDITOR INTERFACES Merge all the BOMItems with same part number into one single entry in IPC2581B.4 ?# u; l/ ?7 X! v6 g* G
1245363 CONCEPT_HDL CORE Design Entry HDL program crashes upon save
3 }9 v! d- W/ @3 {2 t4 ]! r. G5 I1245790 ALLEGRO_EDITOR PADS_IN Bug: PADS Translation with 16.6s023 gives parse error+ ]) P; Z1 U. b4 t3 ~0 Q' X
1246343 ALLEGRO_EDITOR SKILL axlAirGap command is broken in s0226 @! Z8 ^ F% X5 @3 t- V
1246419 CONSTRAINT_MGR OTHER Netrev fails with SPMHGE-268 on existing design
( v2 h8 x! N. J1246878 CONCEPT_HDL CORE Changing Symbol in Variant Editor makes schematic page crash" U" E: i- r4 `$ S# _: C6 {
1246884 ALLEGRO_EDITOR GRAPHICS Infinite cursor disappears from the canvas after step package mapping GUI is closed.0 Z% G) ~0 ^0 E
1247016 ALLEGRO_EDITOR INTERFACES STEP Model of connector cannot be zoomed sufficiently after mapping it to symbol dra file.1 c5 Y6 |; L. Z3 ^9 _
1247107 ALLEGRO_EDITOR INTERFACES Incorrect Spelling in IPC-2581 EntryFillDesc field5 q0 a; t% r; e. t4 A2 ^- n
1247177 SIP_LAYOUT WIREBOND Bondfingers not aligning to wire when tack point on the other wire end is moved from center2 F4 H& R, N: |. T& n, j3 `, Y
1247400 ALLEGRO_EDITOR INTERFACES option to Export optimized PDF in color
7 w) _3 N# f, N* n+ n# v+ [) d: k% n8 }1 a! [& N
DATE: 02-28-2014 HOTFIX VERSION: 024
3 |5 b4 ?. X5 l+ F' r* G% i===================================================================================================================================
# L% \! S0 L% [- H) m" oCCRID PRODUCT PRODUCTLEVEL2 TITLE
7 O. W5 s! z8 Y9 i/ R1 x===================================================================================================================================2 o: u: @2 y* W+ r/ ?* q
1207753 CONCEPT_HDL OTHER The Variant Name with a dash is represented by #2d; u# w L, H7 X- {( S2 [& a* L
1234991 ADW TDA Team Design does not remove deleted page files from zip files
9 A& `; |8 F% n# s1235919 CONCEPT_HDL PDF DNI crosses are not printed on the correct components/ Q; Z- L( g5 A8 L" |2 W" L
1238007 ALLEGRO_EDITOR PARTITION Import partition removes properties from RKO that were on the exported partition; v' u8 C: b& s; u2 }- {4 D
1238140 CONCEPT_HDL CORE Design Entry HDL Crashing
, q7 g, d: T, G% ^) |% n1238195 ALLEGRO_EDITOR DATABASE Via's losing net idenity after being mofifed or replaced.4 {2 ]3 w1 E8 O9 U! e2 |4 }
1238478 ALLEGRO_EDITOR ARTWORK IPC-2581 negative artwork layers does not recognize shape bounding box value
+ _. c6 |$ {6 k) {' F5 b. T/ M1238483 ALLEGRO_EDITOR ARTWORK IPC-2581 not drawing negative artwork correctly with traces in voids. X9 T' p" f- ^1 N
1239070 SIP_LAYOUT WIREBOND When importing wirebond data onto a Die rotated 90 degrees the WB data is placed in the wrong locations
; c' a, L) o1 w4 i1239433 SIP_LAYOUT WIREBOND Need the Wirebonds to lock to the die aftter importing wirebond data5 P! o4 |7 x# I) W9 Y
1239952 ALLEGRO_EDITOR SYMBOL Allegro crashes with a component rotation of 45 or 135.2 o% F& q3 a# y8 t8 O
1240205 SIP_LAYOUT DIE_EDITOR Crash occurs when trying to "oops" for a moved driver in co-design die editor in SiP% y! y/ \: a# a2 C4 ^9 D
1240288 ALLEGRO_EDITOR INTERFACES Why are some of the mechanical holes not showing up in Step output of thi design, while others are ?; I: A) e5 O( X+ c
1240305 ALLEGRO_EDITOR INTERFACES STEP Export gives some errors which are not documented
% K9 O1 i% m6 e3 U ^1240425 ALLEGRO_EDITOR DATABASE Export ODB is not working on 16.6 HF 22
2 G% [. t" F8 [4 L1240879 ALLEGRO_EDITOR NC NC ROUTE file is not correct using hot fix 22 of v166. ^% V( c! @# q8 T% h
1241904 ALLEGRO_EDITOR INTERFACES IDX baseline import displays false DRC with Package_height Offset until DRC update is run.
6 X6 i. Y m7 [+ t- r! P( @! n- z% _ M1242266 ALLEGRO_EDITOR INTERFACES IPC2581 crash on HF22 and HF23# J2 D9 X' h1 G, a1 N; L
1242433 ALLEGRO_EDITOR INTERFACES ipc-2581B incorrect LayerRef values in BOTTOM side RefDes elements6 [2 D* z: G8 b: D
1242988 ALLEGRO_EDITOR SKILL Allegro crashes on skill command axlDesignFlip
2 w: u4 d7 t& A% h9 a1243845 FSP FPGA_SUPPORT FSP design created in 16.6 s018 will not open in 16.6 s021
]: Q9 l; n* R6 {9 R. ~5 t
% H& [1 n/ n& `4 D7 ^, bDATE: 02-14-2014 HOTFIX VERSION: 023" T( [6 @0 w# v4 F' ^! x' u
===================================================================================================================================
' \- E! B" F$ G* ]) p8 K6 [. i* ZCCRID PRODUCT PRODUCTLEVEL2 TITLE
4 i( C' o4 X/ }! n" |! n===================================================================================================================================
% _1 Y" \! a: e% k1 G& _1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.. W# |" f H" h
1202715 SPIF OTHER Objects loose module group attribute after Specctra
7 m) D7 Y' w7 B; F; U) l1203443 ADW LRM LRM takes a long time to launch for the first time
7 y) t g" e3 t- S6 ~ r# H1207204 CONCEPT_HDL CORE schematic tool crashed during save all
7 z& A* r$ s# Y1 Z O; F1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter- X' B& x' D+ o
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA
- {" ?1 W& c, ~' G1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side& f/ w; c' V! {+ B
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
+ m4 I2 x5 U5 N" D; m) ?1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.
5 n- r/ {0 o; I7 Z1229234 FLOWS PROJMGR Can't open the part table file from Project Setup+ d) q) c+ w5 [2 L$ r# T
1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
) W2 b% _0 Y Y( ]$ v5 N1 l1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7. l9 v' W5 X! A& V6 `
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's; f+ e. K+ @, h N2 |" a) h
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
6 |: r. o0 G- ^, ]% s9 M7 h1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes! `( C+ @2 q& Z) e7 |
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form
; q1 ^6 U+ J1 P$ | Y9 d+ v% D1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
6 ~' P S4 t! C% p5 c1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
3 B B6 |) A, f% r0 \1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
3 a1 V( L7 Y+ M/ o, l7 ^! j1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.) i! r6 P) b5 f5 \1 U; D8 Z
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
2 K: i4 A% D" f3 t9 c+ s+ w2 U1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues$ V- H% y& v; B& t
1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File
( M. s i4 l# g `$ o8 Y7 G1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat4 C) Q8 k3 H# `! B. P
9 U, z @$ C p4 c: C& W
DATE: 02-7-2014 HOTFIX VERSION: 0227 C# l! P9 E/ D/ K" R1 J
===================================================================================================================================' ^7 F! ?+ d- i0 A# C3 Y; K2 S
CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 [$ Q ] ^8 m, Y4 x===================================================================================================================================0 o2 Z8 \+ _: j9 O) a
192358 ALLEGRO_EDITOR PADS_IN Pad_in does not translate some copper shapes7 M5 Y- B* ` l u$ {3 U
222141 ALLEGRO_EDITOR PADS_IN PADS_IN: Extra shapes are created when importing PADS design6 n( r& ^/ \& h* y8 [4 F
274314 ALLEGRO_EDITOR PADS_IN PAD_in boundary defined for flooded area be translated DYN
3 M5 }7 H( U8 Q, L413919 ALLEGRO_EDITOR PADS_IN pads_in cannot import width of refdes.1 J9 D# c* K% i9 L/ c0 A, _
609053 ALLEGRO_EDITOR PADS_IN "Mils to oversize" of "pads in" did not work correctly for MM data.% r4 k1 ~6 Y! r0 {& q4 {
666214 CONCEPT_HDL OTHER Option to increase Line thickness in publishpdf utility* \6 Q+ ^1 w/ f+ y! R3 u: V7 V+ U% P5 G
738482 ALLEGRO_EDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphics card; v; i6 x# l4 u5 T4 z, k9 r- w# m
982950 CONCEPT_HDL OTHER change the mouse button for the stroke to have same function with in pcb editor
! c4 I% ?0 i, R p1020886 SIP_LAYOUT LEFDEF_IF a quicker way to promote die pins (by importing macro_pin list)
2 M1 I( B1 m u7 W! Z1032678 CIS VIEW_DATABASE_PA View Database Part gives incorrect result in complex design with variants.
( x, o8 [& K3 E5 E) Y( \$ `1033864 ALLEGRO_EDITOR PADS_IN pads_in doesnot translates teardrops present in design
! f7 g; ~2 l; Z/ G- j1054862 CONCEPT_HDL OTHER Option to increase Line thickness in publishpdf utility' t% w0 w* R$ v2 V
1055252 FSP PROCESS Add a synthesis option to target a group to contiguous or consecutive banks
) x i9 b! Z- T5 y+ j1100772 CONSTRAINT_MGR OTHER In Constraint Manager > DRC > Spacing the Show Element DRC totals are wrong.7 }0 X- b$ X) W& U
1135020 CIS DESIGN_VARIANT Variant list is showing wrong results for hierarchical designs" ?- ?. I) e3 N. t
1138951 SIP_LAYOUT DIE_ABSTRACT_IF Fix die abstract r/w to properly support pinnumbers on ports
9 c( q+ h) V! }1 ]+ v' F6 z1140042 CONSTRAINT_MGR OTHER Diff_Pair lengths and analysis are lost after closing and opening Constraint Manager.9 ]4 P- q9 k7 H$ x0 g$ X
1143662 ALLEGRO_EDITOR INTERACTIV Enhancement Request for RMB - Snap Pick to options increased to include Pin edge
+ T$ S8 P7 ?8 A: W1147961 PSPICE SIMULATOR Simulation produces no output data; z: w: a* G/ F0 M' v/ E- ^! ]
1150874 ALLEGRO_EDITOR PADS_IN Dimensions in PADS are not translated correctly during pads_in translation
$ ]+ ? k0 D3 x8 x2 V1154184 CONSTRAINT_MGR CONCEPT_HDL Difference in the way topology is extracted in 16.3 versus 16.62 ] K0 i, g. ?4 S& l- W5 C% z
1154770 CAPTURE PROPERTY_EDITOR Variant Name property doesn't show value in Variant View mode& O3 @6 d! Z" d3 l0 C; B
1158350 CONCEPT_HDL CORE Need a warning Message while importing a 16.3 sub-design in a 16.6 Design
2 N* H% r! V$ U: |1162347 ALLEGRO_EDITOR EDIT_ETCH Enh- Allow new option in Move command such that it allows stretching etch using only 45/90 degree segments directly
5 Y8 P: O0 u. R q( N: T' `1165553 ALLEGRO_EDITOR INTERACTIV Subclass list invoked from the status window does not represent correct colors.5 s; ^5 V; {8 n! o
1168079 FSP MODEL_EDITOR Clicking OK or Save As in rules editor allows user to overwrite the master with no warning
. ]6 ?4 f+ l1 k7 s1172043 SCM OTHER : in pin name causes SCM to crash
8 [+ G2 \0 E) E2 a! n; t9 }! s1172207 CAPTURE STABILITY Capture crash while adding new part from Spreadsheet; v3 X: C* u/ U8 ?1 c& q7 S' Y
1172743 ADW TDA Allowed character set for the check-in comments is too limited
7 Q" O9 C& Q0 a4 Y: P1174099 SIP_LAYOUT WIREBOND Option to reconnect wire based on 縫in name� in the Wire Bond Replace
|8 _) [3 F" y, }: }/ M. H8 N1177672 APD IMPORT_DATA Netlist-in wizard didn縯 provide detail information about what columns have been ignored by import process* a7 _2 I0 }) x7 C) }+ P
1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATION property can not be set to invisible r% W7 I; o* U
1177820 CONSTRAINT_MGR INTERACTIV Done the Allegro command when attempting to launch CM
$ M1 N9 W8 z6 h1178586 ALLEGRO_EDITOR EDIT_SHAPE Number of digits displayed after the decimal point of Shape Creation function does not match the Accuracy of BRD7 ]$ }1 X- _2 P1 z' Y0 L. a
1179688 PSPICE STABILITY pspice crash for particular HOME variable vlaue
4 B0 q+ b+ t8 H( S6 g1179827 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to Symbol export - enable field to add Keywords for data fields to excell cells
1 L1 |/ E6 a2 ^+ z1179879 SIP_LAYOUT STREAM_IF Data file corrupt when exporting Stream data from SiP database. e& Y! N5 i* M$ b
1180164 F2B BOM BOM csv data format converts to excel formats
g* D% J$ V3 C$ ]! Z) X9 P1180477 ALLEGRO_EDITOR INTERFACES IPC-356 output is listing a duplicate location in the comment section
, D( P: [1 M# {1180932 SIP_LAYOUT OTHER SiP Layout - Symbol to Spreadsheet add option for writing to existing spreadsheet( y$ V1 \# v2 m% [
1181377 ALLEGRO_EDITOR INTERACTIV Pick Releative does not work correctly with RMB-Move Vertex/ m% T3 U0 s3 [7 f4 ~1 A
1181516 ALLEGRO_EDITOR DRC_CONSTR Getting a "Thru Pin to Route Keepout Spacing" when there should not be one.$ l* P: P" \: K8 K
1181739 GRE CORE Running Plan > Spatial crashes GRE
1 j |' x6 i/ E, g6 X- L1181935 ALLEGRO_EDITOR DATABASE Enh. Property that allows internal C-C DRC errors
9 P8 @) j2 f# [9 I! I1182185 SIP_LAYOUT OTHER SiP Layout - Import symbol spreadsheet - suppress Family for the font in the XML spreadsheet
" X# M3 W, U2 s* j* i0 K1182566 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to symbol - Enhance ability of spreadsheet exchange to allow for a portion of a full pin map( e$ H$ e7 M, f+ a0 f
1182599 CONSTRAINT_MGR DATABASE CM Prop Delay Actuals do not update after Z Axis option is turned ON or OFF and Analyze is run.- Z2 j; z# q: f' m
1182892 CAPTURE SCHEMATIC_EDITOR Pspice marker rotation before placement, ?" j# U2 g" b3 d3 H$ n
1183682 ALLEGRO_EDITOR DRC_CONSTR Implement Nodrc_Sym_Pin_Soldermask & Nodrc_Sym_Pin_Pastemask to symbol level& I" n/ `9 `7 {" p
1185445 SIP_LAYOUT DIE_ABSTRACT_IF Die abstract export needs to be able to select xda file type when browsing
+ w: m& S9 p6 x q1185932 ALLEGRO_EDITOR SHAPE Soldermask in solder mask void DRC
9 [/ i/ O0 Q: Y$ Y1185946 CONCEPT_HDL CORE Ericsson perfomance testing report 5 sept 2013
' i. N8 w0 q2 l; r4 \1187213 FLOWS PROJMGR Unable to lock the directive: backannotate_forward8 n. r4 u H" ~* s
1187444 ALLEGRO_EDITOR DRC_CONSTR With this design Database check prompts error "SPMHGE-47: Error in call to batch DRC"2 S1 K L/ \7 j0 X
1187597 ALLEGRO_EDITOR DRC_CONSTR No Package to Package Spacing DRC error, when symbol overlap sideways at 45 degree.
( J' c6 [6 L6 S! O8 C6 h5 J9 _4 J" w- o u1187723 FSP PROCESS Synthesis can fail depending on component placement
- n. K1 x9 }& k4 U7 \0 m1188164 SIP_LAYOUT OTHER SiP Layout - Spreadsheet interfaces Import Export and Add Component - include Keyword for NET_GROUP
7 l+ B6 Z% Y" T+ q1188245 CONCEPT_HDL CORE INFO(SPCOCN-2055): You cannot run the CHANGE command in a read only schematic
0 _3 I: z( @ o1190927 CONCEPT_HDL CORE Check sheet does not report shorted signal/power nets if power symbol is connected to a pin
5 _6 w2 h; R; v& r. r& S r! r1191497 ALLEGRO_EDITOR INTERACTIV ENH: Adding names to the text block parameters numbers
, d4 I6 d/ q/ K9 U5 T1192005 SIP_LAYOUT IMPORT_DATA Import SPD2 is missing 1 smart metal shape from file$ ~9 j! k( l9 Y0 y8 g- N# U
1192204 ALLEGRO_EDITOR EXTRACT Need ability to extract vias that are labeled as microvia
7 \4 J( c. |# ^) S. _- n. y+ @2 W1193063 ALLEGRO_EDITOR MANUFACT TestPrep log displays "Pin is not accessible from bottom". The component is through hole.
8 [) f! U. B/ I- }- y* e1193418 ALLEGRO_EDITOR GRAPHICS 3D Viewer can`t export image in both SPB166S015 and SPB165S047
) L! Z; V: G$ ]5 i) c1194305 SIP_LAYOUT EXPORT_DATA export package overlay creates file with no package info
) i4 ~& c. i/ L- s. r0 l1194418 APD IMPORT_DATA issue when do File->import->netlist-in wizard
* p1 `# d; k! E" A$ V8 N- c1195279 F2B PACKAGERXL Ptf files are not being read when packaging with Cache5 T9 Q. U0 O' e O
1195374 ALLEGRO_EDITOR INTERACTIV Modules are not showing up in Tools > Module reports9 b2 @( `7 c" j! o7 i6 I
1196603 SIP_LAYOUT EXPORT_DATA Change form for "Write Package Overlay..." to better support longer lists of routing layers! y/ e2 z# h5 _/ I! k" v
1197302 CONSTRAINT_MGR UI_FORMS Inconsistancy in selection of object for Spacing Constraint Worksheet
% k2 l/ Z5 g) {8 l* X0 e1197399 CAPTURE OTHER Draw toolbar disappears when using Print Preview' X S' H* `: o$ |, D" y4 f" e
1197543 ADW TDA TDO does not correctly show deleted pages6 g8 L9 C7 D5 y* K: h' V
1198033 CONCEPT_HDL CORE Signals do not get highlighted when Show Physical Net Name is option enabled+ s7 R" U5 F2 z) E- ~* T( l! p
1198468 ALLEGRO_EDITOR GRAPHICS 3D_step model does not show the correct view in 3D_Viewer when symbols have multiple place_bounds.& A# |) a w) v- E( z
1198617 CIS GEN_BOM Mech parts are showing with Part reference in CIS BOM& n) U3 M2 q8 q2 ^3 r
1199764 ALLEGRO_EDITOR SHAPE Allegro crashes when trying to delete small island on POWER layer.1 v6 o/ ^1 ?- ?( l
1200232 ALLEGRO_EDITOR INTERACTIV Moving all items including board outline which is made of lines does not move the board outline in General Edit Mode.% Y1 B* n7 E6 H" R- t" y
1200748 ALLEGRO_EDITOR INTERACTIV Additional pin edge vertex object to snap pick+ F; Z: V- S" c E+ \( d
1201056 ALLEGRO_EDITOR DATABASE Unsupported functionality strip design creates a .SAV file- M- r4 Z) r" {! T. \8 {: k) u7 ?$ M
1201638 CIS PART_MANAGER Part retains previous linking inside the subgroup
_5 |+ e& U/ @0 E( E" P1201834 ALLEGRO_EDITOR PLOTTING Bug: Import Logo command changes resulting imported object
C1 r/ s4 _+ A. a1202406 SIP_LAYOUT OTHER enable the dynamic display of component pin names for co-design dies in Sip Layout2 O) e8 B. c" @
1202431 CONCEPT_HDL PDF The publishpdf -variant option should have a "no graphics" option9 g, R" ^( t8 m0 u, o
1202717 ALLEGRO_EDITOR DATABASE About Warning(SPMHA1-108):Illegal line segment ... end points.0 {/ {# k% X' I+ j+ ], b
1203459 CONSTRAINT_MGR INTERACTIV Object Report has no mechanism to output information for a specific design.
5 P" @* u! a% \1204544 F2B DESIGNVARI Variant Editor does not warn on save if no write permissions are on the file! N% `5 J* o, [0 u, p
1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDL syntax
* H+ S" \; S) A! [1 ~1205952 ALLEGRO_EDITOR GRAPHICS Step Model for Mechanical Part is visible in 3D viewer only when Etch Top Subclass is enabled
5 L B7 q; _6 G# P2 L5 }! W1206103 SIP_LAYOUT IC_IO_EDITING add port name property to pins, and add Skill access I/O driver cell data
: x$ Q2 R" t0 x$ F) E; @, [1206546 CAPTURE ANNOTATE User assigned refdes are resetting when 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�/ c5 S X0 m# `2 b( Q3 f
1206561 ALLEGRO_EDITOR GRAPHICS Not all mechanical symbols made with Step files are displayed in the 3D View$ y" f0 }) V3 k
1207125 SIG_INTEGRITY ASSIGN_TOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus
, ?/ P8 ^; O! C' Q# @1207386 CAPTURE GENERATE_PART Altera pin file not generating the part properly
0 z! u- [& Q. A8 `1207629 CAPTURE TCL_INTERFACE Bug: GetMACAddresses tcl command not working
+ O9 s; B9 a/ }, e1207994 CAPTURE TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pins with black color
5 ]8 ^ x6 n3 Q1208017 F2B DESIGNVARI sch name is not same when updating Schematic View while backannotating Variant
7 z5 w/ G: K( i3 X$ P1209363 ALLEGRO_EDITOR INTERFACES When placing pins using the polar command the tool returns 4500.00 for 45 degrees.
6 G9 y/ z& p! n# h" F( q. x2 K0 p1209769 CONCEPT_HDL CORE Top DCF gate information missing
i5 F+ c K# o4 u2 l5 _1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box1 j1 [7 Y$ A# }, K' |
1210442 CONCEPT_HDL INFRA Save design gives ERROR(SPCOCN-1995): Non synchronized constraint property found in schematic page
. _ G3 P; J; N: K1210685 ASI_PI GUI User can't edit padstack in PowerDC-lite5 J4 P* U/ M; ?& ~" K1 L
1210744 SIG_INTEGRITY SIGWAVE SigWave: FFT Mode Display unit seems not to be correct
" S1 b7 A6 |& c2 O( a7 s1210829 CAPTURE NETLIST_VERILOG Shorted port is missing from verilog file) W) n& l7 g5 V6 Y0 [$ b
1210850 CONCEPT_HDL CORE DE-HDL backannotation crashing after instantiating specific cell from Ericsson BPc Library3 Q3 T8 V5 _0 Y( b, y
1211620 ADW COMPONENT_BROWSE Component Browser Performance
0 s1 C, s4 L* _$ G1212102 ALLEGRO_EDITOR INTERACTIV Shape edit boundary adds arc mirrored to the highlighted preview.0 ]& i* d! o, ^8 j* {
1213294 CONCEPT_HDL SECTION DE-HDL windows mode multiple section fails to section first contactor pin from column of individual pins
- n, i8 v# `1 ?$ S: Z% {- G1213402 APD DATABASE The old "ix 0 0" fix is now causing the features to lose nets entirely.4 U ^* p7 H% Z' F; t$ O7 ~0 S
1213694 ALLEGRO_EDITOR PARTITION Via connected to Dummy Net pin in Partition gets connected to shape on the board after importing partition+ |' j$ {8 q( Y* [
1214247 CONSTRAINT_MGR UI_FORMS Selecting the "All" folder in Spacing Constraints in CM does not automatically select the first column for editing
9 w% P8 J: b" P$ p( N# R0 k9 y3 k1214320 SIG_INTEGRITY SIGNOISE signoise command with -L and -k option7 N; c7 \; }" y. o: i% {
1214433 CONCEPT_HDL CORE Genview does not update sym_1 with ports added to the schematic
/ I/ u: m9 d, Y4 O/ R1214909 ALLEGRO_EDITOR NC NC Drill Legend show extra rows for drills
8 Q/ u7 b8 T1 F' C& C1214916 SIP_LAYOUT OTHER package design integrity check for via-pin alignment with fix enabled hangs
k# h3 D+ }% w+ h' k* R1215954 SIG_INTEGRITY SIMULATION Cycle.msm does not exist error when simulating extracted net2 v; x+ i% \/ \5 }
1216328 CAPTURE STABILITY Capture crash+ \; X- ~8 f1 H! ]5 o
1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.049# t7 O4 Z3 f4 r& U/ v g
1217450 F2B BOM ERROR 233: Output file path does not exist
; m) K# I$ g) b" K1217612 ALLEGRO_EDITOR INTERACTIV Replace padstack will not replace padstacks that have multiple alphabetic characters in the pin name - AB21-AB37
& Z e, y3 ]4 M1217823 ALLEGRO_EDITOR INTERACTIV Compose shape fails with SPMHIS-473% R+ z4 s% B, s9 X: J5 z$ q
1217887 ALLEGRO_EDITOR INTERFACES An undo option to be made available in the STEP Package Mapping window9 V [; f( q# E; I/ S' ]
1218665 ALLEGRO_EDITOR INTERFACES In step viewer, the bottom side parts are placed above the pcb board surface
1 S. I: t% m* b9 K1219053 PSPICE PROBE PSpice crash with the attached Design
' m2 a9 S: w. b7 d% u1219067 ALLEGRO_EDITOR EDIT_ETCH dynamic fillets behavior is unstable
, i9 L8 V; X' {/ d1219095 ALLEGRO_EDITOR MANUFACT Design Cross section chart is tapered for two layer board% i( y2 Z& M6 O) J
1219126 ALLEGRO_EDITOR SKILL Skill issue with axlRefreshSymbol()
& T: T6 O% I v6 `. R/ I3 G* K1220701 ALLEGRO_EDITOR INTERACTIV View > Windows > Worldview (showhide view command) fails with command not found
' |" P$ i4 Z4 |* I/ s1221057 ALLEGRO_EDITOR REPORTS Units in Cross section report for spacing is not synced with the design
3 ]& `2 H1 `4 R+ Z& V1221139 ALLEGRO_EDITOR EDIT_ETCH Delay tune is not tuning differential pair* P" R% W6 h7 R" Y" r5 h& Y+ j4 \
1221157 SIP_LAYOUT IMPORT_DATA import spd2/na2 file is not importing data correctly into sip# D6 g* o. l s: d
1221163 SIG_INTEGRITY GEOMETRY_EXTRACT Simulation aborts with severe convergence issue when coupled vias is enabled.
9 T7 J* s: W* C! M0 `7 d1221416 ALLEGRO_EDITOR DATABASE strip design for function type
+ x+ l! _+ G+ a. ]4 T& V1221931 ALLEGRO_EDITOR DATABASE Fatal software error when embedding component
7 y/ i M+ T- H2 f! }1222105 CONCEPT_HDL CORE Moving Pins around the edge of a Block causes the text of the pin to change its text size.
- R7 O! R; Q7 `1222124 APD DATABASE Same Net DRC's exhibiting inconsistent behavior.
% J0 x$ Z- C" \$ ?5 f! T0 `- U9 D1222272 SIG_EXPLORER EXTRACTTOP Cannot extract net or open SigXplorer after selecting a netgroup- H& {7 \5 ?) p/ I6 G$ n( ^4 L7 i! o
1222329 ALLEGRO_EDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top
% E1 n) R5 U0 `" O7 t1223183 SIP_LAYOUT BGA_GENERATOR Getting an incorrect error message when using the BGA generator with a long BGA name.
{5 b, P6 Y6 B; n1 B) U1223662 ALLEGRO_EDITOR REFRESH Allegro crashes when trying to refresh symbol
# |# \; L2 a i1223932 CONCEPT_HDL CORE DEHDL block desend does not find 1st page if its not page1! Y1 R8 \3 g. c7 C, |) }
1223940 CONSTRAINT_MGR UI_FORMS Unable to change CLOCK name in Setup/Hold Worksheet under Timing in CM.+ }; V3 Y' b5 d0 d% Q) v
1224127 SIG_INTEGRITY IRDROP Is the old static IRDrop in 16.6 officially supported?
; D- y; U8 l+ B" R, t1225492 PCB_LIBRARIAN CORE PDV expand vector pins resizes symbol outline to maximum height again! H n% p9 X3 E; c
1225546 CONSTRAINT_MGR ECS_APPLY nets where the referenced ECS maps correctly in constraints manager for front end but not in back end6 g4 ~+ C' m- L0 f
1226405 ALLEGRO_EDITOR INTERFACES File > Export > IDF ask for filter config file eventhough it is created in same session and stored in parent folder
; |& T# {# _9 Y/ y1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDN Analysis with XL and GXL0 u; e7 p/ g; y
1228721 SIP_LAYOUT OTHER File Export Netlist Spreadsheet enhance sort to be a natural method per Jedec according to customer \ z, ?8 o$ `2 H- b
7 y+ q6 x% V, M8 [9 wDATE: 12-20-2013 HOTFIX VERSION: 021! B( r) \2 |% A$ |6 Q$ u
===================================================================================================================================
9 l6 j# b/ P, z3 ?# U" [' dCCRID PRODUCT PRODUCTLEVEL2 TITLE
8 Z) Y) P$ l, i7 ^& d$ A, }1 [===================================================================================================================================0 v! a, t- t, ]; Y W
1214932 ALLEGRO_EDITOR OTHER Allegro will crash when performing show dimension on linear dimensions.
/ U% H, y5 H* v, L1215045 ALLEGRO_EDITOR SKILL Successive file open / ipc calls crashes Allegro 16.6 F2 a2 T; w/ L
1215115 ALLEGRO_EDITOR NC drawing name doesn't display in the ncdrill.log file/ l, R( }6 Z7 P) ^1 x: h) F
1216028 SIP_LAYOUT PLACEMENT Design will not update embedded component symbols.
2 v7 U( S9 R. V+ G1 u1 ?1218451 ALLEGRO_EDITOR DRC_CONSTR Route Keepout to Pin DRC created even after adding Void in RKO shape. v; t+ q: \/ ]# Q; }
1218636 ALLEGRO_EDITOR SCHEM_FTB netin process will rotate embedded symbols( E: j6 L! k1 _- K2 y9 d/ s
1218706 CONSTRAINT_MGR CONCEPT_HDL NCC associations get deleted from FE CM, }5 `5 d" H' [+ J. {+ y
; X5 c" Q) x6 Q( XDATE: 12-4-2013 HOTFIX VERSION: 020
7 t% f& O7 N' m' L H. c1 l6 b===================================================================================================================================& z% h) M( P) {( x2 D5 |
CCRID PRODUCT PRODUCTLEVEL2 TITLE5 D L9 E3 P, `, \8 U# q
===================================================================================================================================
L" Z- A) g0 Q+ i1116426 F2B PACKAGERXL Packaging in 16.6 increased by 3 folds compared to 16.3$ J0 V- A$ o7 K0 c1 Y3 }; o
1190095 CONCEPT_HDL CORE In Windows mode select the part and click on version placed selected version +1.
; s% g/ Y) L9 @/ a& [1199410 CONSTRAINT_MGR CONCEPT_HDL Constraint Differences Report window hangs in 16.6-s016
+ r2 O& j) ?0 S$ u( W9 i1199425 CONSTRAINT_MGR CONCEPT_HDL Import Physical fails (the cmfeeback.exe has stopped working) in 16.6-s016/ P, o/ ?* r9 T. [, m# C
1199700 PSPICE NETLISTER Netlist fails on addition of netgroup' p. A, }2 w5 w; r. o9 @
1200936 CONCEPT_HDL PDF publishpdf fails if UNC paths are provided from the command line M! ]2 F3 k0 P, \5 I
1202391 CONSTRAINT_MGR OTHER Getting 'An Invalid argument was encountered' when generating Net Class-Class report in CM
+ Z" C( ^) A& k% c w1 j2 m1202587 CONCEPT_HDL CREFER Crefer schematic reports cannot be deleted on Linux.9 \4 I& C7 ]+ N1 [: Y( m6 N! |
1203143 GRE CORE GRE crashes on running Plan > Spatial
$ o3 Z: c- A9 n; R. `. m8 p1206019 ALLEGRO_EDITOR INTERACTIV Allegro needs to be restrated to read steppath with 16.6 S017
* u0 h) [+ x2 x8 d& v1207050 ALLEGRO_EDITOR INTERACTIV Refresh Padstack fails on Warning( u& p1 f* ~4 ?. d) p2 F/ [
1207178 CONCEPT_HDL CORE Aqua color on wire does not matches icon color: ~: u+ v. w; {8 R4 k( o1 \, N
1208152 F2B DESIGNASSC ERROR: Dictionary File: cmdict.l could not be found% s7 _5 \; [5 f; L9 P# P
1208276 APD STREAM_IF Stream in fails to import what Allegro exported& _' C8 z3 n' S: @; [
1208345 ALLEGRO_EDITOR SKILL Why axlChangeLayer not working for shapes on this attached skill file?; H" K+ L- v& U7 |# l2 y
1208351 ALLEGRO_EDITOR SKILL axlFilmCreate do not define the IPC2581 domain correctly.; l1 W; N+ }$ u
1208467 PCB_LIBRARIAN VERIFICATION con2con mangles cell data after checking cell having syntax errors on part_table
/ l0 E! }7 i i* X! {1208579 SIG_INTEGRITY GEOMETRY_EXTRACT Incorrect traces are extracted when void area is less than anl_min_void_area setting u4 n9 t; s& R4 N" d/ l" o
1209347 ALLEGRO_EDITOR PARTITION Import partition that has diametral dimensions will crash Allegro
4 f* Q/ o }$ t( _( v1209897 ALLEGRO_EDITOR PADS_IN Pads_in will not translate design. P2 g/ a" l @/ s
1209902 PCB_LIBRARIAN CORE PDV crashes reading part" b. Z* ]* R/ E5 @: T0 ?
1210183 PSPICE SIMULATOR SimSrvr crash with ORPROBE-3211 RPC Server unavailable Message: R; W1 V1 a% [! Z" y$ a% g* \
1210408 ALLEGRO_EDITOR EDIT_ETCH AiBT hangs when doing interactive breakout on bundles using latest hotfix.4 V$ W8 S) b1 S0 f+ o! \$ \; l
1210443 ALLEGRO_EDITOR INTERFACES Allegro Design Publisher does not create fully searchable PDF for some of the text that are present or certain layers
; u9 h- h8 |# r9 C0 ~- C' g( r& R1210876 CONCEPT_HDL ARCHIVER Archiver wrongfully deletes directories.# f; u+ {" o, v
1211839 CONSTRAINT_MGR DATABASE Topology can't be extracted correctly.
9 c6 E3 f5 @, g/ o1212709 ALLEGRO_EDITOR DATABASE No connect can`t be detected in SPB165S048' o& K) K* w/ O5 @# _/ N
1213752 CONSTRAINT_MGR OTHER "Show Constraint Difference Report" option at File > Import > Logic does not retain the last setting1 @4 h2 `4 Z& F& N0 H6 l9 P9 z
& |# z1 u: H1 ~1 @/ lDATE: 11-15-2013 HOTFIX VERSION: 019( N. a [1 [9 u9 Q3 B1 D# O
===================================================================================================================================5 R' I0 K& P( l4 c: a: O5 l- x
CCRID PRODUCT PRODUCTLEVEL2 TITLE
' X2 J# ^, K- Z( c p# B& H===================================================================================================================================* }' a, Q/ L" D7 e [/ q/ d0 p2 I
1176155 CONCEPT_HDL CORE Graphics remnants with 16.6 QIR 3
$ |( F- [/ a- c1178272 CONCEPT_HDL OTHER Verilog netlist does not include split blocks correctly7 y( s2 @; i# c- I9 Q5 z
1190782 FSP FPGA_SUPPORT Support for Altera > 5SGXEA9N2F45 device.+ W0 q) {, ]9 x5 d
1194140 ADW LRM SYNC_PROPERTIES is not resolving issues a based sync_properties settings
* e" [: C7 s1 t9 }3 {% f1195744 APD EDIT_ETCH Diff_Pair routing fails on certain Uvias in the pair.
9 I: T6 X( Z1 v1196704 ALLEGRO_EDITOR INTERFACES ENH: During ipc2581 export checkboxes corresponding to 縈iscellaneous Image Layers� should automatically get selected' u! y* T' O: v _& h: m# D
1198340 ALLEGRO_EDITOR OTHER Multiple -product option on the Allegro command line does not access the second -product! W- N' P8 j. g' H& C
1198596 ALLEGRO_EDITOR INTERFACES When copper thickness is increased for the outer layers, step Viewer does not show correct component position.$ ?! K' S5 R* d! V
1199673 PCB_LIBRARIAN OTHER Component Browser fails to load footrpints if they are set with UNC path
' {! y7 n2 ~6 T3 i5 Q1199889 ALLEGRO_EDITOR DATABASE Allegro crashing with latest hotfix.
! w4 D6 J) t7 K- G3 K, z( J1200303 ALLEGRO_EDITOR GRAPHICS 3D Viewer does not update after changing STEP model mapping
6 w% b" B0 Y) u/ s4 K# N8 l1200449 ALLEGRO_EDITOR REPORTS Allegro crashes when generating Net Loop Report.1 a# q1 k4 j( J& P8 @* r! S" L
1200915 ALLEGRO_EDITOR DATABASE Reducing accuracy of this specific design crashes Allegro
4 X T4 A! A5 q/ ]5 T3 J1201011 ADW COMPONENT_BROWSE Component Browser crashes in DB mode
2 v ^# o+ |7 \! m& w+ l1201376 ALLEGRO_EDITOR INTERFACES Allegro hangs when trying to map a specific STEP model to a package drawing.
( \( H/ Q( ^0 C& c; X: ]& r. j1201897 SIP_LAYOUT IMPORT_DATA BGA Pin Colors not matching the Colors defined in the Symbol Spreadsheet after updating.% c& O+ N* U2 d- q$ j4 }
1202709 ALLEGRO_EDITOR INTERFACES STEP File generated from Allegro is not overwritten when the variable "set ads_textrevs
% P" ^/ e7 c7 G& K& t1202820 ALLEGRO_EDITOR INTERFACES Different xml generation for same step model on S106 and S017% l- _9 o9 {1 n K5 O0 H
1202842 ALLEGRO_EDITOR INTERFACES Step model invisible for one pin dra in allegro 16.6 symbol editor4 A3 V" H8 Q( \( f3 C! F! O: J/ O
1202983 ALLEGRO_EDITOR SHAPE Shape voiding creates DRC with Route Keepout5 C: r- { Q( v; b8 C( l
1203125 ALLEGRO_EDITOR OTHER Exporting STEP file with External copper enabled does not show all copper when viewed with Solid Edge or Inventor
; Z3 O4 v4 P$ S+ d( R3 h/ a1203236 ALLEGRO_EDITOR INTERFACES IPC2581 output with crosshatched shape is not correct
5 W5 N6 x5 v2 H* N1203995 CONCEPT_HDL CHECKPLUS CheckPlus rule, local_signal_no_offpage_body, getting an incorrect failure.+ u f M: p! X$ K R' f' Q* v
1204629 ALLEGRO_EDITOR SKILL axlUIDataBrowse crashes the editor or returns error
9 a- j+ R2 s7 B2 S( k" G1 a1204640 SIP_LAYOUT DIE_EDITOR Concurrent co-design update fails7 I1 Z C* X0 ^0 P0 v' o x( ]$ P
1204881 SIP_LAYOUT BGA_GENERATOR Pin numbers are messed up after deleting a pin at a staggered bga
; I% ` u' ^5 l1204885 CONCEPT_HDL CONSTRAINT_MGR Cant assign discrete models after the wrong model was removed.8 T9 F; i5 b% O# ]' _
1205374 ALLEGRO_EDITOR OTHER pdf out command creates incorrect drill Symbol Characters placement in pdf file when setting film mirrored.+ G. \0 k( _5 `" D. @* G
1205729 SIP_LAYOUT DIE_EDITOR update of codesign db fails on exit from die editor, q1 A1 x; M2 X. u5 ]
1205801 ALLEGRO_EDITOR OTHER Tool crash when do export IPF.
$ D+ f/ d5 s7 z" S7 O: F1205881 CONSTRAINT_MGR OTHER In CMGR , Objects > Create crashes Allegro
) I# P% H+ x: o% ]
2 e" `0 X W4 i& w0 t( zDATE: 10-25-2013 HOTFIX VERSION: 018
* V9 N/ i9 k6 \, |4 x6 A5 P===================================================================================================================================- [- W* J9 L+ N2 u
CCRID PRODUCT PRODUCTLEVEL2 TITLE
# ?$ F/ j( T* I===================================================================================================================================
& I9 E* _4 Y3 _* _1118303 CONCEPT_HDL CONSTRAINT_MGR can not prdefine default units in HDL2 g% R0 ^1 L# k3 K U$ V4 o
1174901 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl4 I: M2 ?* a6 p3 K* [" B
1176990 CONCEPT_HDL OTHER DEHDL BOM tool doesn縯 see similar names.' c W3 n5 M' C
1179665 GRE CORE Plan Topological Crashes after around 8 hours of routing.
# j" I6 F, w4 A) _9 n( }1188193 CONCEPT_HDL CHECKPLUS CheckPlus not recognizing PIN as a base object.
% V: K2 J' L9 O4 t, ~9 t7 P" R7 D1189100 SCM OTHER Replace part in SCM using ADW as library fails: [- J% R4 r) Y
1189507 SCM SCHGEN ERROR(SPCOCN-2009): Package error after second schgen run with Preserve mode.% R+ i. U) b! G6 n
1192391 CONSTRAINT_MGR CONCEPT_HDL Restore from definition deletes local objects in other blocks
% j/ }8 U1 E+ h" q1194597 FSP OTHER Pin definition problem6 T; i8 v f! ^0 G' [/ w( [* s4 U
1195202 SIP_LAYOUT LEFDEF_IF Cannot add .lef files in IC Library Manager. Getting warning message WARNING(SPMHLD-52)+ g8 }# k8 ~% e" H* g" E
1195309 GRE CORE GRE crashing during Plan Spatial.
- P8 e8 y$ W4 W* \1197262 ALLEGRO_EDITOR MANUFACT Angular Dimension created in symbol is placed w.r.t. board origin and angle is blank
1 i8 @1 E9 d4 a$ l2 Q2 D8 I1198521 CONCEPT_HDL OTHER cadence DEHDL issue - Note for Hotfix_SPB16.60.016_wint_1of1
! Y7 u0 I8 D$ D* A8 J# a7 n4 i+ \1199219 ALLEGRO_EDITOR INTERFACES Question on STEP Model export which uses PLACE_BOUND layer for any symbols that do not have STEP model mapped
% O8 E# T0 w7 Z, F; B& Y1199235 ALLEGRO_EDITOR SCHEM_FTB capture's behavior is redundant while creating pcb editor netlist
0 f5 p: U7 r' v! c& h9 i) w/ y; }8 h1199323 GRE IFP_INTERACTIVE Crash when importing logic& [4 E! A: S. J4 l
1199368 SIP_LAYOUT DIE_EDITOR Refresh of die abstract in die editor with this design takes over two hours
$ D% x. U) D* q: z. Q7 {3 T1199760 ALLEGRO_EDITOR DATABASE Allegr won't display Soldermask Top layer0 y& t$ P- ?0 x4 q
: {; q8 E: V( q ~9 T: [/ T
DATE: 10-10-2013 HOTFIX VERSION: 0171 b6 R9 z: {4 h9 S+ H3 e
===================================================================================================================================) G; b% j" n( O# A1 f* p
CCRID PRODUCT PRODUCTLEVEL2 TITLE
2 f3 G' G& M( c0 X4 y0 v* {2 e8 G===================================================================================================================================7 n; w R+ C. J. h* ~: T
735992 ADW LIB_FLOW Create Test Schematic does not use the correct package type
0 A9 t2 W' {( D) ]" N1121403 FSP PROCESS "Assign to Pin" not getting obeyed by Synthesis. t8 o, d y( e( N) Z/ \* g. @ m
1141844 RF_PCB DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing
8 r0 C8 w$ ^ k+ N/ _7 W) F1169269 ALLEGRO_EDITOR DRAFTING Dimension placed on package symbol moves to different place when it is placed on brd file.
; `" a% y0 M3 V+ b Y1170488 ALLEGRO_EDITOR MANUFACT Dimension text(on .psm) move to different position, when it is placed on .brd.! L& v9 w& O7 l K
1173345 CIS CRYSTAL_REPORTS Crystal Report - Display Parameter dialog for export option5 b7 x3 S3 c/ ~
1181759 SCM LVS SCM Crash when doing update all that executing import physical command.
6 O2 G% J `2 ?/ k/ R% V4 _7 o1182499 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks (all pins and via) drill.' E, p! L( _4 B- l8 L5 U9 m
1184682 CONCEPT_HDL CONSTRAINT_MGR Net Constraint not transferring to layout from schematic2 f: ]$ y9 w9 q, t6 u/ j/ l H
1185524 F2B PACKAGERXL Enhancement User would like notification of pack_short in pxl.log$ J Z3 p0 K( | l
1185902 ALLEGRO_EDITOR SHAPE Update shapes dont clear some diffpairs in HF15: a6 @' k. [4 ]: i+ A6 l0 l
1186152 ADW LRM Part Status for Deleted Part in LRM is distinguished with other part status" v4 k; p) z; Z: K! b( j# g: g
1186387 ALLEGRO_EDITOR OTHER DXF cannot catch offset value in s047 hotfix.4 m( e. b2 x7 K( J" V
1186805 ALLEGRO_EDITOR OTHER Exported STEP file missing multiple components placed on board; t+ n( b. t+ I1 T
1186818 ALLEGRO_EDITOR COLOR Custom color not retained during dehilight, j" q- Q( M: o ?2 L
1187196 CONCEPT_HDL CORE TOC not populating (page 1)
. Q) u5 | d; \/ M- q2 x; ?4 {1187667 F2B PACKAGERXL Existing hard LOCATION property in drawing was left unchanged
4 Z9 X: N/ W% Y4 k- [0 p1188264 ALLEGRO_EDITOR MODULES Some fillets not regenerated in module created from a board file.7 q* W5 `, s6 J* _6 l+ d
1190144 ALLEGRO_EDITOR OTHER Fillet shape is not genrated around cline
7 U% P! ?7 d) V+ d1190210 F2B BOM The bomhdl.exe fails - MFC Application has Stopped Working
! T @9 m4 @8 [0 N8 T+ d1190618 ALLEGRO_EDITOR GRAPHICS Enhancement for Visible grid
( S2 @' ~& ~2 G1190813 ALLEGRO_EDITOR INTERFACES 3rd party netlist file in TEL format fails syntax check but imports successfully( @' ]. j8 [% ^4 S j
1190895 ALLEGRO_EDITOR EDIT_ETCH Route delay meter displays violation when sliding diff pair
$ C, f3 ~4 b* P2 a2 Z' V) I- o1190908 F2B OTHER DE-HDL aborts if dummy net is being cross-probed from PCB Editor
6 B4 a9 Q! m Z3 g6 `1190990 CONCEPT_HDL CORE Mismatch in .csa and .csb files
5 t: a$ X6 L$ ?. W2 V' g5 P! e1191008 CONCEPT_HDL CORE Remove Binary File feature doesn't work2 H2 b# A; Y6 }* q( q/ G% F
1191514 SCM PACKAGER Packaging error PKG-100
/ D% d8 W" f |( p2 W1191517 ALLEGRO_EDITOR DRAFTING Metric +tolerance when using dual dimensions is not displayed correctly
" T2 X( q, K* f- U9 p) P0 k1192561 ALLEGRO_EDITOR GRAPHICS Padstack with offset is not showing correctly in the 3D Viewer. J" c7 t% R' W; E" C2 b' W
1192916 ALLEGRO_EDITOR EDIT_ETCH Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.
* s' [! \6 ^8 ]1 u8 t/ P4 i1194197 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks.
' Q- L) ^1 w/ K- n4 h1194239 PSPICE DEHDL Associate Model does not launch from DE-HDL
! l' W4 W; H* n- g' P: _1194736 PSPICE SIMULATOR Design causes RPC failure when run consectively
; k, ] T+ Z) y W7 L; R1195139 ALLEGRO_EDITOR PLACEMENT Components disappears from board file once they moved f5 ~! U; a/ T6 N/ F0 s
C) L3 w: d5 O/ N4 v# Q3 y" @& kDATE: 09-27-2013 HOTFIX VERSION: 016' J; D1 ?- m3 i7 ]% Z2 p9 e6 s& b
===================================================================================================================================
0 n, s# S3 ~, rCCRID PRODUCT PRODUCTLEVEL2 TITLE
/ `7 z H: O- M# k% T4 k# k, h===================================================================================================================================4 f9 u7 `5 J; \% w; r3 s$ q, }8 M
548538 CAPTURE NETLIST_ALLEGRO Enhancement:Include mechanical parts in Allegro netlist
3 L2 l, m! E0 x$ L1076579 CAPTURE GENERAL Display value only if value exists2 c5 O' z8 L3 _: l/ L
1083904 FSP GUI Need Filter in Change FPGA dialog to select desire FPGA from the long list.
8 J7 g& ^. t% m* ]1089313 ALLEGRO_EDITOR INTERFACES Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility0 Y- s2 G+ G8 \' E. ?! {
1095728 ALLEGRO_EDITOR EDIT_ETCH Slide to grab adjacent elements when extend selection is enabled
1 X: c8 p6 I" |/ Y( m' b1102698 SIG_INTEGRITY ASSIGN_TOPOLOGY ECset will map on single ended nets but fails when the two nets are define as a diff pair.
$ e, Q- U6 |. I6 q1104071 SIG_INTEGRITY REPORTS Shape Parasitic value changes for bottom shape for changes in top shape
% L5 @' V" S$ d3 N' M- p0 B p1117731 FSP POWER_MAPPING Ability to sort in Power Regulator forms
: q, F/ o/ _( P$ Y4 I/ Y* j1121539 FSP CONFIG_SETTINGS Cannot configure special FPGA pins (temperature diodes)
% l: W& b+ Q: V$ ?1 D5 b1 K1122721 FSP MODEL_EDITOR Partial copy-paste overwrites the complete cell in XML Editor" W4 U7 t" v* c
1123238 FSP TERMINATIONS Report functionality for terminations defined in the complete design.
' \7 `. T/ l* S' p( T1 ~' P: ?6 e. G4 D* [1123364 FSP GUI Clicking on column header should sort the column.
: r: {( _/ X$ x# N1123403 FSP EXTERNAL_PORTS Improper checkbox selection for 緿o Not Connect� or 縀xternal Port� column
2 ~' d8 A& r3 K# N& s* n1125611 CONCEPT_HDL OTHER display unconnected pin in schematic pdf.% e3 L4 ]& K" v3 ]- d
1129871 ALLEGRO_EDITOR INTERACTIV Wire Profile Editor can't read mcmmat.dat in working directory.
. E( N1 v% N4 ?0 ^1133688 ALLEGRO_EDITOR GRAPHICS Enhancement request to enable 3D Viewer to show STEP model from .dra file.
" q; ?+ y& g0 a- |7 x1141747 ALLEGRO_EDITOR GRAPHICS 3D view dooesnot displays height if step_unsupported_prototype variable set
+ E; ~) N( Q: x1142215 SIG_INTEGRITY SIMULATION PULSE_PARAM set on DiffPair wasn't used for designlink simulation.3 B7 U+ @( T1 Y' Y b; P* {2 f; `, l
1142798 ALLEGRO_EDITOR INTERFACES Step file output is incorrect in step viewer when composed of arcs and line.. J( @5 x- t4 c9 W
1142894 FSP GUI Ability to RMB on a header and select `Hide Column�$ I, u- u3 h2 c/ [6 p
1142940 FSP EXTERNAL_PORTS Issue with checking/unchecking "Do not connect" and "External port" cells$ L; s: E- p- }/ X, ?- W
1142949 CONCEPT_HDL SKILL Usage of "Preferences > License Settings� in FSP/ r: w) t; _: R6 e, V2 L3 R
1143091 SIP_LAYOUT SYMB_EDIT_APPMOD symed: When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract( B+ A9 _/ F- N% N3 C
1144371 CONCEPT_HDL COMP_BROWSER Component Browser search results are inaccurate
# L* }1 X# `5 }& B' d5 k1145033 ALLEGRO_EDITOR PLACEMENT When aligning components with options in Placement mode displays no busy indicator
# \2 Q- C% I4 K5 R) H1145286 CONCEPT_HDL CORE Directive required for switching off the console
. v8 S* u w% c% \, @1145800 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl.
3 W7 i! u* }& |. A& z, Z1147899 ALLEGRO_EDITOR SHAPE Autovoid two overlapping shapes that share the same net
2 Z. m! u# V# T3 U1149996 ALLEGRO_EDITOR EDIT_ETCH Routing does not follow the ratsnest 'pin to pin'.
& B# Q1 G( P/ U' W' t+ |1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.
( e+ j8 H( J( Y0 e% I1152577 ALLEGRO_EDITOR DATABASE slide removes cline seg: N5 T- v( P: O5 u0 C4 z
1152751 CONCEPT_HDL CORE Option to double-click and copy the Netname
% f: G3 Z& X4 _( k1153220 ALLEGRO_EDITOR INTERFACES ENH: option to supress header/footer during PDF Export3 e! I ~% b& q+ {- C
1153625 ALLEGRO_EDITOR INTERFACES If Symbol has place bound bottom, the step model shows incorrect placement.
! U& ^7 d* d1 Z; j" B }8 s6 P1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form
7 y4 L0 q4 x% G% x* D9 r a1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties.
8 u4 O2 n7 }5 |7 g% {1 Y; p1155161 CONCEPT_HDL CORE Add Signal name: Suggestion box overlaps with the typed signal name that is typed" G" M# X3 v5 E0 o$ g) E; R
1155922 CONCEPT_HDL OTHER How can I use the batch mode for PDF Publisher and print a variant overlay?8 E g ]4 G. C" q3 X+ J* ~4 t
1156858 ALLEGRO_EDITOR PADS_IN PADS Translator: Missing drill on square PTH padstack
7 G- ^0 h9 O5 Q# D7 w1157362 APD 3D_VIEWER Need a way to color multiple nets in 3D viewer from APD/SiP.* c* n7 ?6 r9 \) }: m( l
1158130 CONSTRAINT_MGR ANALYSIS Constraint Manager do not display the Cumulative Result in Reflection Simulation1 Z* u9 r0 S6 N! g5 F5 }9 u
1158210 ALLEGRO_EDITOR SHAPE SIP Layout happens crash while users move the shape with route keep-out) ]0 p3 f5 w6 p4 h3 h
1158452 SIG_INTEGRITY GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle! T/ R l6 |) A! c6 r' G
1158827 ALLEGRO_EDITOR EDIT_ETCH Slide a via in pad automatically add cline back to via to pin.3 D9 P( v' f1 V. n
1158871 PCB_LIBRARIAN IMPORT_CSV PIN TEXT is not automatically added when importing the .csv file
* |! _8 ~2 B; A/ a- ] S: y1159738 ALLEGRO_EDITOR INTERACTIV Selecting the Cancel button in the Text Edit command does not cancel the text.
% F/ @3 a7 E& `# b% {6 q1159878 SIG_EXPLORER OTHER Ecset mapping dont follow topology template( S; [ \& W7 v) z
1159971 ALLEGRO_EDITOR MANUFACT Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file+ ?1 U* }% T& R6 e. M5 S* a
1160017 SIP_LAYOUT DIE_ABSTRACT_IF Add text to clarify shrink operation- ]- N1 P: _% K0 X0 T% D6 f5 J
1160507 APD EDIT_ETCH Script not playing back what was recorded when sliding lines {# F. @3 c4 b/ V
1161261 ADW TDO-SHAREPOINT Schema for TDO-SP fails on Japanese OS" K2 ~& G* p# G7 G7 `* |* N
1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
9 p3 I% ~& e. j8 T! r1 l0 s1161636 ALLEGRO_EDITOR DRAFTING need new function for PDFout : hatching shape9 M9 E$ P4 U. h5 l6 L
1161777 ALLEGRO_EDITOR OTHER default line width for PDF output. w1 P, d6 C9 D& B: \$ V
1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
3 d2 L- b& F+ k6 ?' X1162562 CAPTURE STABILITY Capture crash on second attempt of pspice netlist creation in 16.61 l b- o/ N" S: X5 W
1162629 FSP PROCESS "Load Process Option" under Run does not work properly
) Y/ V; N* E6 z) b4 t, M1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE1 {1 f) G5 L# _2 t1 f
1163149 ALLEGRO_EDITOR DATABASE Autosilk creates Illegal arc to corrupt database
) ~* b, x, E8 |) |1163439 ALLEGRO_EDITOR COLOR Duplicate Views Listed in Visibility Tab.; S; L j; Q" C! i
1163521 CONCEPT_HDL COMP_BROWSER System Architect crahes on replace7 y9 J! ?5 S" o& m
1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin% N2 e. O# h2 t# s7 e2 K3 j
1163902 APD EXPORT_DATA Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?: R- S& [ ?. l9 V0 h# e
1164337 CONCEPT_HDL CORE Cannot delete attribute filter value in PDF > General > Attribute Filter list) d2 J9 z: ]4 P
1164365 ALLEGRO_EDITOR INTERACTIV Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol3 f% f4 ]. D- }
1164769 APD VIA_STRUCTURE The replace via structure command does not accept a single canvas pick.- W$ }1 n4 ~1 \. v
1165026 ASI_SI GUI EMS3D exist in Via Model Setup of SI base.5 u, q: {9 y, H! Z* V5 N* B3 v8 Y
1165561 CAPTURE DRC File > Check and Save clears waived DRCs
( ^% l0 u# M0 S2 u* a2 I* I" Z1165631 CAPTURE STABILITY Capture crash in the hierarchy tab of Project Manager window: t: V+ R9 i" w: B
1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)
' _6 ` N* c2 Y/ b5 k1165911 FSP PROCESS Editing group name in protocol causes incorrect Process option checked% T, J& I6 k8 a+ ]6 R2 Y& w& ?8 _
1166026 ALLEGRO_EDITOR DATABASE Running DB Doctor removes net name from vias/ q7 y, e; G2 _! l$ z# I
1166034 SIP_LAYOUT OTHER SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle l; ^4 C) C! k9 B
1166074 GRE CORE GRE crashes during planning phases
. M; @4 G. P2 ?* `4 V) U1166319 ALLEGRO_EDITOR PLACEMENT Swap not succeed
, Y) A4 d: `: |; z2 T E1166484 SIP_LAYOUT WIREBOND Bondfinger "Align With Wire" problem during move
% _0 T I1 [7 d: _# _4 g1166530 ALLEGRO_EDITOR INTERACTIV Bug: Mirror in Placement Edit resets the options tab for Edit > Move
. y- C8 j# B# U1 t/ ]' l1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue' ]5 d; G( ]5 ^/ X' M
1167847 CAPTURE PROPERTY_EDITOR Implementation name length greater than 31 character causes capture crash
4 n3 p1 ~' Q% ?" Q7 n5 m$ a1167887 F2B OTHER Improve message on symbol to schematic generation# T; N, m% @3 }/ u4 l' p
1168369 F2B DESIGNVARI Variant don縯 appear in increasing order while Annotate.0 ]$ T. [. t' r, K0 j
1168629 APD OTHER Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD% H% T! D8 `5 K7 ~$ V: O K
1168678 ALLEGRO_EDITOR NC Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.
. d! E& }1 W1 I, a; l1168798 ALLEGRO_EDITOR INTERACTIV Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk
" H! f7 ~6 G) l4 |; ~, T) H S; \1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check
. ^- u" ]: M. L b5 e2 U0 E1168864 ALLEGRO_EDITOR CREATE_SYM Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty
& H' G9 \9 `+ J$ |: G6 z* X0 x1169213 PSPICE SIMULATOR Parametric sweep is giving incorrect reuslts
* Z5 N$ Q8 q+ V" c5 B1169436 FSP FPGA_SUPPORT Add support for Cyclone V CSX and CST parts
. a; g6 ^3 w8 v" f( `3 I) h. R1170108 ALLEGRO_EDITOR INTERACTIV Enhancement to preserve Rat T location for Topology assigned schedule
8 f0 G, a' l; c3 j1 ~6 C; E+ S1170313 SIP_LAYOUT LOGIC scm adding additional pin names and unassigned property to codesign die chips file
9 l9 J8 A% n' j* T% [3 h6 r# y; `1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window.
- ]( t5 F$ O0 z5 ~1171747 ALLEGRO_EDITOR PLACEMENT Allegro crashes when doing a gate swap between components
9 t5 B$ |% t0 u1172183 ALLEGRO_EDITOR INTERACTIV Alignment modules fails on equal spacing
+ ]7 }" d) j4 N8 k; A* S, j! I1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via
. P0 t' h5 I( O& U' t' ~: G1 e+ J1174067 ALLEGRO_EDITOR DRC_CONSTR Soldermask to shape drc does not show if the layer is a PLANE.
& b( X0 j: I4 a G9 U1174338 ALLEGRO_EDITOR PLACEMENT preview has rotated pads
/ u, A7 K# Q5 _! y' n' I( |: k6 B5 y1175307 CONSTRAINT_MGR ANALYSIS CMGR fails to report RPD DRC for accuracy 4 - mm5 q4 H( r6 f) Y1 w6 @5 s) ~4 E
1175537 ALLEGRO_EDITOR REPORTS net loop report crashes Allegro. Design specific+ H5 x: u T5 i% k) R9 g% |2 h
1176126 ALLEGRO_EDITOR INTERFACES 3D viewer doesnot change models units dynamically( A' G7 y. e" T, N7 {6 D$ E
1176281 CONCEPT_HDL CORE Option to Auto-hide excluded modules
, A* p, v. a4 v9 T0 o+ E1176413 ALLEGRO_EDITOR MANUFACT Q - testprep parameter settings is not retained, what could be the cause..' G. \ ~5 i$ E
1176791 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl
8 e( K6 q% R, \/ D: m7 J" f2 t1178052 ALLEGRO_EDITOR SHAPE SIP crashes during shape degassing.3 S# ~8 `1 d& H! j- x) ` ]& y' k
1178158 ALLEGRO_EDITOR INTERFACES Export step file creates step file of same height
' _; s5 H. E9 w: f3 _. n1178201 ALLEGRO_EDITOR GRAPHICS Large oval pads rendered as oblong hexagons in the 3D viewer
( T7 h; D, C& @1178671 ALLEGRO_EDITOR GRAPHICS 3D Viewer in package symbol editor not displaying correct place bound shapes.
( g k( w5 P, U Y4 y8 J! P1178725 ALLEGRO_EDITOR OTHER With fillets present, rat lines do not point to the closest endpoint.
4 z+ s g: |! Y k( {" w% O1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.- }% A. z. ^* q. }
1179093 ALLEGRO_EDITOR SHAPE Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.
3 I! G% u0 C1 b6 `6 q4 [' n1179109 ALLEGRO_EDITOR OTHER DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version! Z- d- L6 U& e3 m ]
1179571 ALLEGRO_EDITOR ARTWORK Artwork crash and artwork log report Aparture missing
" I/ Z8 ?/ t+ s1179636 SPECCTRA ROUTE Route Automatic will not start if NET_SHORT are attached to a mec-pin
: q) F$ V) j- V4 z% D1179659 SIP_LAYOUT DIE_EDITOR die edit on co-design die losing c4 bumps/ u) t* m* A" E" W( L
1180306 ALLEGRO_EDITOR ARTWORK When trying to create Artwork the tool crashes with no error messages just a little X box2 N* Q; n3 Q, U/ @; V, a
1180573 ALLEGRO_EDITOR ARTWORK If one layer has warning, all artwork films are "created with warning".
& ~+ c" m- z( q6 j' v1180960 SIP_LAYOUT PLACEMENT swap function is not swapping logical paths in sip layout!
, J, i, C& ^" P$ ]* n$ n) f1182534 ALLEGRO_EDITOR SKILL axlLayerPrioritySet() not working with v166 s013 and up
$ F4 x6 l! ^+ o; w1182560 ALLEGRO_EDITOR PLOTTING Creating plot 2nd time casues Allegro to crash9 O$ `: u6 x3 b, s5 i
1182616 ALLEGRO_EDITOR PLACEMENT Application crashes when attempting to place a high pin count BGA' K# Y4 w2 a5 @* O# z
1183752 CONCEPT_HDL CORE Unable to modify location properties within a read-only hierarchical block) X& H4 x, p5 X/ f t
1183774 SIP_LAYOUT DIE_EDITOR Die Refresh hangs) M H0 I. q/ ]3 D% w3 A8 j8 B. j
1184178 CONCEPT_HDL CONSTRAINT_MGR Ecset xnet members lost from electrical class when restore from definition of subblocks
" I5 J. G. j- [8 B1184787 ALLEGRO_EDITOR EDIT_ETCH Allegro SPB166 s 015 crashes during normal add connect function.
1 `) q3 r8 [, N' L/ b9 O9 z5 y
# r; y m4 r- v) u) d2 f3 G, MDATE: 08-22-2013 HOTFIX VERSION: 015
/ z) P5 I1 Q) Z8 Y! y7 B; c4 I===================================================================================================================================* b* ]' b* r# E1 ^2 }& D/ M
CCRID PRODUCT PRODUCTLEVEL2 TITLE3 v1 J' W( y! S3 ^ A* C" ^2 H& `
===================================================================================================================================
, ~3 Q" \7 ^8 ~2 f9 e1156102 PCB_LIBRARIAN CORE PDV severe performance degradation on Linux platform makes PDV counter productive after some time7 g* M$ N/ w( V# s0 }
1165756 CONCEPT_HDL CORE DE HDL 16.6 adding ASCII character to properties s5 W. f0 l6 ?
1169896 ADW LRM Library Revision Manager makes updates but the interface never returns to the user: E; G1 [5 f2 i3 |( c
1170635 SIP_LAYOUT WIZARDS BGA PIN NAME doesn't sync with PIN Number7 [; ~: K* A8 l- @) M J# `
1171061 ALLEGRO_EDITOR PLACEMENT Place Replicate Apply cannot place module. Q# R9 ^0 N) Z# k1 P4 d5 ]& X
1171415 CONCEPT_HDL CORE Mismatch in the interface ports in design bw_hybrid for block a38410_scsp/ m1 r' z5 l+ O8 R4 A; g5 x
1171598 APD WIREBOND Cannot load xml over 65 profiles defined in file.
1 r8 C. k% B/ t; B2 ?6 y7 u1171713 ADW LRM Blank lines appear in the LRM - RM-Clicking causes LRM to crash
; Q9 D3 l, E' l7 j7 q1172576 SIP_LAYOUT IMPORT_DATA AIF import fails with Error: symbol is missing refdes
% J5 H* t! D* w1172938 ALLEGRO_EDITOR PLOTTING Export IPF probrem# v; x( l; {8 [
1173190 ALLEGRO_EDITOR ARTWORK Not able to Add/ Replace film_setup.txt file in Artwork control file.
; p& K4 D6 [1 Q; `3 u- o4 v1 v1173750 ALLEGRO_EDITOR REPORTS SIP tool crash when clicking report "Net Loop Report"
5 b% c( g5 g8 M5 A' f1175582 ALLEGRO_EDITOR SKILL axlDBCreateFilmRec error undifined function/ \* e5 _4 \* H" G3 p, Z
2 f4 }! u0 Y& lDATE: 08-9-2013 HOTFIX VERSION: 014( b! s5 v8 v1 A2 s2 s$ S& f3 N- }
===================================================================================================================================
7 @/ n5 V2 R; d% w# e+ \& I0 B" PCCRID PRODUCT PRODUCTLEVEL2 TITLE/ O- _$ N$ U* f' c8 p
===================================================================================================================================
& P9 l* K5 O+ C( M) |: ]1155569 APD MODULES P1_U1 and P1_U3 Die pins are missing after Place Module." e+ r9 ]0 K/ A# Q1 H0 y6 `( a" Q
1158528 CONCEPT_HDL OTHER Dual Monitor issue: Retain Hard Packaging option is missing and attribute test distorted
. Y* Z( O' x8 f8 d! \6 {; b: `1160968 ALLEGRO_EDITOR SKILL Text Subclass change difference in Edit > Change and axlChangeLayer Skill command
; R9 N! R0 A* H0 U' `* R6 ?- A1161986 SIG_INTEGRITY SIMULATION Flatline waveform seen when via model is set to detailed closed form or analytical solution) f( r9 c$ T, s; U
1162323 SIP_LAYOUT DIE_EDITOR Die Editor is incorrectly leaving an unassigned function pin in the die during refresh from die abstract
- |/ `! U4 R- o0 F0 D1162752 ALLEGRO_EDITOR SKILL axlDBChangeText doesnt recognize ?layer as a valid argument as documented/ _% q/ U/ ~' E$ k0 \8 I
1165002 GRE CORE GRE Crashes during Plan Spatial giving "Memory Allocation Failure" Error.
6 d' }& y; p1 X, X1 ~/ X# d1 o7 R) [1165469 CONCEPT_HDL CORE Import Design loses design library name' X: _! t8 h2 S5 r y- S7 i
1165708 ALLEGRO_EDITOR TESTPREP Test point router failing when attempting to insert new TP via's5 m% z6 Q4 O& n0 ~- g
1165801 CONCEPT_HDL PDF Pin texts of spun symbol overlap in publish PDF.
1 W0 B! M& I* T' F3 Q2 M1166020 SIP_LAYOUT WIREBOND Bondpads created with shapes do not follow the orthogonal pattern when adding wirebonds.
% ^: v H8 W3 W3 Q& R$ O9 o( x7 ~1166371 ALLEGRO_EDITOR DATABASE File locked for writing in 16.5 cannot be unlocked in 16.6. I% b/ ~2 N" C u$ w
1166482 ALLEGRO_EDITOR INTERFACES Step orientation for y-rotated component is not exported correctly.. I# [2 G6 J3 ]7 }( d) |) O
1167519 ALLEGRO_EDITOR DATABASE Uprev dbdoctor does not log warnings about renaming properties.$ U! u1 A6 m3 C' v
1167588 SIP_LAYOUT DIE_ABSTRACT_IF do not create a new pad stack for each I/O pad
! A# q1 _) K" ]; R! R1168496 ALLEGRO_EDITOR SCHEM_FTB Export Physical Crashes when netreving the board; p- D& r3 X. F- l
1169510 SIP_LAYOUT WIZARDS Netlist in Wizard is crashing with this text file where the Net Name for one of the assignments is blank, meaning dummy
$ n- K. r/ c* l1 O% ~5 x4 s3 t1169593 CONCEPT_HDL PDF Published PDF file's hyperlinks do not work fine when user click 1D10 or 2A10.
+ _2 \. \1 a, M' C: g# V3 C1169984 F2B PACKAGERXL Error Mapping cset when packaging but not in CM Audit" N% d: G) M1 t- g* H
1171008 SIP_LAYOUT OTHER SiP Layout - Beta feature Void Adjacent Layer Shapes - changes or modifies "priority" of other/all shapes
+ d1 P. @3 {/ d1 M. D1171411 ALLEGRO_EDITOR OTHER Enh - Break in Step 3D view in latest hotfix v16.6s0133 @. H6 n9 ]2 u9 T9 Z9 U" Q
& u) M; T6 l. }% n
DATE: 07-26-2013 HOTFIX VERSION: 013' E! r+ m5 U# C- O5 f. X0 K
===================================================================================================================================
* n% C% X `4 P" c1 F$ U. eCCRID PRODUCT PRODUCTLEVEL2 TITLE' @! @3 c' Y. y. \6 B% C
===================================================================================================================================1 A3 l7 O" ~! c# l% c) O& F
111368 CAPTURE CORRUPT_DESIGN Capture - will not produce allegro netlist with 10.0 D# R4 `/ o" w' v& v* u
134439 PD-COMPILE USERDATA caCell terminals should be top-level terminals- S/ w2 y$ K# S( X+ I1 \
186074 CIS EXPLORER refresh symbols from lib requires you to close CIS0 L3 b; y( m8 @% R; `
583221 CAPTURE SCHEMATIC_EDITOR Option to have the Schematic Page Name as a Property in the Titleblock" X0 ?. X# Q( R7 s0 N
591140 CONCEPT_HDL OTHER Scale overall output size in PublishPDF from command line5 E4 a% a6 @/ X7 F% O: S* Y
801901 CONCEPT_HDL CORE Concept Menus use the same key "R" for the Wire and RF-PCB menus
. @* Q$ `: F+ R9 r0 k813614 APD DRC_CONSTRAINTS With Fillets present the "cline to shape" spacing is wrong.
; d* e/ `1 h# K+ ~; p" @881796 ALLEGRO_EDITOR GRAPHICS Enhancement request for Panning with Middle Mouse Button
9 V$ A" e1 c; ?# C7 ~0 i3 L! V887191 CONCEPT_HDL CORE Cannot add/edit the locked property+ b$ t* ?; Z5 h, i) E/ J# m
911292 CONCEPT_HDL CORE Property command on editing symbol attaches property to ORIGIN immediately9 O( G! T9 W6 g: s- N1 Q( x
987766 APD SHAPE Void all command gets result as no voids being generated on specific env.
, W* m3 a. N% P6 o1001395 SIP_LAYOUT ASSY_RULE_CHECK Shape Minimum void check reports lots of DRCs which are not necessary to check out.
, D3 `1 w0 `7 l2 R1030696 ALLEGRO_EDITOR INTERACTIV Enh - Allow another behavior of PAN movement using middle mouse in Allegro
8 P0 F; F7 _+ |: H1043856 ADW TDA Diff between TDO and DE-HDL Hierarchy Viewer is confusing to the user% g* w8 l; Z; f" @0 q' W L0 w F
1046440 ADW PCBCACHE ADW: ImportSheet is not caching libraries under flatlib/model_sym when the source design is not an ADW project
9 |% J! z& i# a( E8 L! R1077552 F2B PACKAGERXL Diff Pairs get removed when packing with backannotation turned on1 X$ X7 V6 q" U+ X
1079538 F2B PACKAGERXL Ability to block all 縮ingle noded nets� to the board while packaging.& q) T0 Q' \; c
1086362 ALLEGRO_EDITOR SHAPE Enhancement request to autovoid a via if shape cannot cover the center of the via.. g5 T+ S& x; j1 _3 a- \4 D; X4 z
1087958 PSPICE MODELEDITOR Is there any limitation for pin name definition?
1 o1 e: t7 H3 D* U1087967 CIS UPDATE_PART_STAT Update part status window shows incorrect differences
" r% }$ _$ p; d2 M& N& |8 K. z6 Z9 ]' f1090693 ADW LRM LRM auto_load_instances does not gray out Load instances Button7 G- c+ ^) B0 M6 M/ U' Z0 x6 x
1097246 CONCEPT_HDL CORE ConceptHDL - assign hotkeys to alpha-numerical keys3 M! P+ ^. M' {
1099773 CONCEPT_HDL CORE DE HDL goes into recursive loop if a custom text locked at site level is deleted from Tools > Option
9 j9 F s0 V$ _8 ?% O5 y/ U1100945 SCM SCHGEN SCM generated DE-HDL has $PN placement issue
" z' `1 a# a+ w7 b! T# t" G3 [1100951 PSPICE SIMULATOR Increasing the resolution of fourier transform results in out file! t* }3 m& z; O3 K( f
1103117 RF_PCB FE_IFF_IMPORT Enh- Allow the Allegro_Discrete_Library_to_ADS_Library_Translator to output in its original unit
. a+ N/ \6 G3 h" L) D. R1105473 PSPICE PROBE Getting error messages while running bias point analysis.
" N! ^4 V+ E) I8 b1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.& {; X& |/ i! r3 Y o
1106298 ALLEGRO_EDITOR INTERACTIV Copy Shape uses last menu pick location as origin and not the Symbol Origin as specified in Options.
) d* |. E+ x- l( O1106626 CONCEPT_HDL CORE Concept HDL crashes when saving pages# k- b- J8 C3 z5 V' l! F
1107086 ALLEGRO_EDITOR INTERACTIV manual void with arc's goes in wrong direction during arc creation
: L9 I3 e6 a* M5 b' K% ]1107172 CONCEPT_HDL OTHER Project Manager Packager does not report errors on missing symbol$ O' K+ B4 N, a6 f3 B
1108193 CONCEPT_HDL CORE Using the left/right keys do not move the cursor within the text you're editing' a8 E! z, z2 I4 B. ]
1108603 PCB_LIBRARIAN VERIFICATION PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm
; i( s9 b+ {* p" {4 w/ A$ f1109024 CIS OTHER orcad performance issue from Asus.
; R/ ?4 N3 o3 L+ e7 R4 Z0 y6 R1109109 CAPTURE NETLIST_ALLEGRO B1: Netlist missing pins when Pack_short property pins connected
' v! F) X* d0 q9 R5 r1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerber lines for fillet.
5 }* n* C/ {1 n' v# T( O1109647 SIP_LAYOUT DEGASSING Shape degassing command enhancement - control over what layers are counted in even/odd layer sets.' m, u6 n% W1 s
1109926 CONCEPT_HDL CORE viewing a design disables console window5 b3 e& N$ P2 Z
1110194 SIP_LAYOUT WIREBOND If OpenGL settings for display of dynamic net names is enabled, should be visible while push/shove wirebonds.* d. \8 c6 `' C: s
1112357 SIP_LAYOUT WIREBOND wirebond command crashes the application* c" l5 z% P9 T3 l2 {5 r
1112395 CONCEPT_HDL CORE 縗BASE\G� for global signal is not obeyed after upreving the design to 1650.7 w5 ?1 m% R7 y5 a* W- o0 \: t) @" V
1112658 CAPTURE PROPERTY_EDITOR Changing Part 縂raphic� value from property Editor Changes Occ refdes values to instance
8 _) c# z8 e- O1 U& ~5 r1 w0 m% u, ^* o( g1112662 CAPTURE PROJECT_MANAGER Capture crashes after moving the library file and then doing Edit> Cut9 K0 {. X1 P$ D& Y1 ]
1113177 PCB_LIBRARIAN CORE Pin Shapes are not getting imported properly. C" F, s+ r( P
1113380 ALLEGRO_EDITOR INTERACTIV Change layer to - option for package type .dra is not available in 16.6 release
! m8 C: e! h; v0 Y5 u1113656 SIP_LAYOUT WIREBOND Enable Change characteristic to work without unfixing its Tack point.
$ }: S$ F8 P1 Y- E/ R5 Q }5 R1113838 SIP_LAYOUT DIE_ABSTRACT_IF probe pins defined in XDA die abstract file are added with wrong location
. ~3 X1 b% n, _. ?1113991 CAPTURE GENERAL Save Project As is not working if destination is a linux machine) i8 `, y+ a' ~) T5 D6 M3 ]4 l1 L
1114073 APD DRC_CONSTRAINTS Shape voiding differently if there are Fillets present in the design.
+ T7 R* c5 B& l1114241 CAPTURE SCHEMATIC_EDITOR Port not retaining assigned color, when moved on the schematic
! g( K. a* m+ D2 A1114442 PSPICE PROBE Getting Internal error - Overflow Convert with marching waveform on' I5 X: J6 A) _; [* v
1114630 CONCEPT_HDL ARCHIVER Archcore fails because the project directory on Linux has a space in the name/ e$ A0 f9 b' T/ \) s4 M
1114689 CONCEPT_HDL CORE Unknown project directive : text_editor# j, g' Z3 M2 R( T" }: }
1114928 F2B PACKAGERXL 縀rror (SPCODD - 5) while Export Physical even after change pin from A<0> to A$ E4 h' {1 s( D. x! t5 u6 j( h- U+ S: a
1116886 CONCEPT_HDL CORE Crefer hyperlinks do not work fine when user use double digits partitions for page Border.
# E! v) D) B" N! z* Y1118088 ALLEGRO_EDITOR EDIT_ETCH Should Plan accurate and Optimize be removed in 16.6?
& `0 Y7 ~) q7 k% {1118734 APD EDIT_ETCH Multiline routing with Clines on Null Net cannot route in downward direction
" I. i4 d4 w8 p" W1118756 ALLEGRO_EDITOR SHAPE Shape clearance parameter oversize values getting applied to Keepouts
9 f. S- L* I$ U9 H; |3 w: Q1119606 CONCEPT_HDL MARKERS Filtering two or more words in Filter dialog box
+ @5 G& D1 ?/ I- c7 E/ `- D ^2 V1119707 CONCEPT_HDL CORE Genview does not use site colors when gen sch from block symbol
' ~+ [+ z# P' ^& F( m1119711 F2B DESIGNSYNC Design Differences show Net Differences wrongly4 h8 g0 g B! e) B
1120659 CAPTURE PROJECT_MANAGER "Save project as" does not support some of Nordic characters. X8 F- }/ v9 [( c
1120660 CONCEPT_HDL CORE Save hierarchy saves pages for deleted blocks.6 d/ n2 A6 s) w3 M! F# F8 f
1120817 SIP_LAYOUT SYMB_EDIT_APPMOD Rotate Pads commands not working while in the Symbol Edit App. mode& p& D) o W# a3 @1 n2 C
1120985 PSPICE MODELEDITOR Unable to import attached IBIS model; y( {3 m* \3 n' W0 A) @8 x
1121171 CONCEPT_HDL CREFER PNN and correct property values not annotated on the Cref flat schematic
, b; J* y4 i3 T5 |% r% x. i7 h1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.2 a' w5 u; _2 {: s+ M
1121382 ALLEGRO_EDITOR INTERACTIV Undo command is limited to two for this design
( l, s' _6 K/ K6 R1121540 F2B PACKAGERXL pxl.chg keeps deleting and adding changes on subsequent packager runs$ G( n- d. p H+ X5 i4 W
1121558 ALLEGRO_EDITOR MODULES Unrouted net and unrouted connection when module is placed of completely routed board file.
' n0 F/ a$ j6 g2 L, |- ?& F1121585 ALLEGRO_EDITOR OTHER Drill Hole to Shape Same Net Spacing with Dynamic Shapes shows wrong result.& t) Q9 c8 [$ C1 e" w) r
1121651 CAPTURE SCHEMATIC_EDITOR "PCB editor select" menu option is missing
) r/ {2 j: j6 p( X+ h4 ~( U1122136 SIP_LAYOUT PLACEMENT Moving a component results in the components outline going to bottom side of the design.. N6 j h1 `) F1 f2 O' H3 _" h6 S$ s
1122340 CAPTURE NETLIST_ALLEGRO Cross probe of net within a bus makes Capture to hang.
+ c% i. }3 |) J$ [1122489 CONCEPT_HDL OTHER Save _Hierarchy causing baseline to brd files0 k( g5 ~- g& ^6 Q& w5 ? `9 M
1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically( I0 g0 p5 U5 W4 N1 F& r6 p
1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one
3 W8 L% G" r9 U8 O5 a& _9 ?1123150 CONCEPT_HDL CORE property on y axis in symbol view was moved by visibility change to None.
R6 w( B* G; i X! w9 p1123176 ALLEGRO_EDITOR UI_FORMS Negative values for pop-up location is not retained with multiple monitors (more than 2)# _7 b6 B/ j* g5 }; H7 z7 q
1123815 ALLEGRO_EDITOR GRAPHICS Embedded netname changes to a different netname: b. w" v. B2 ]" C) ?# U
1124369 ALLEGRO_EDITOR INTERACTIV Sliding a shape using iy coordinate does not work indepedent of grid.
+ C! U1 V- f* F9 X* M( O- u1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5& m4 x2 k3 G: q9 b8 y* f1 {
1124570 APD IMPORT_DATA When importing Stream adding the option to change the point
2 ^9 D! u+ \8 z1125201 CONCEPT_HDL CORE Connectivity edits in NEW block not saved( lost) if block is created using block add
1 C% f' n' {3 ]0 V: `. M3 |0 T1 A1125314 ALLEGRO_EDITOR INTERACTIV Enved crash during setting of library paths in user preference
( J7 Y; [6 Q* |* Y1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux
* O/ |* L g! D, r7 Z1125628 CONCEPT_HDL CORE Crash on doing save hierarchy
[4 x3 B' C, G% V) V1130555 APD WIREBOND Wirebond Import should connect to pins of the die specified on the UI.
, e! w R: i S7 E; n2 l+ U( @1131030 PSPICE ENVIRONMENT Unregistered icon of Simulation setting in taskbar( m, J& K! J3 b; G0 s
1131083 ALLEGRO_EDITOR INTERACTIV Bug: 16.6 crash in changing the mode in Find filter window5 \6 b# s3 U; {) o3 T$ l X4 y
1131226 ALLEGRO_EDITOR PLACEMENT When Angle is set in design parameters while placement component is rotated but outline is not.
% |( ~5 {4 p% ~# Y0 I5 K4 ^0 ~1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.0 B2 l6 T+ C! A; m8 {
1131699 PSPICE PROBE Probe window crash on trying to view simulation message
7 L( V1 H' V& J) ]4 [4 G1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.
2 {( \5 F4 k) u( {- X. S1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.- @) o4 X3 x; s* ^0 s. {' O( j! Y
1132698 ALLEGRO_EDITOR EDIT_ETCH Slide Via with Segment option with new Slide command" Z C6 F+ F% `. F! w' m
1132964 ALLEGRO_EDITOR SHAPE Same net "B&B via to shape" errors created when adding shape
# C6 ~# z2 I- L D1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top8 {' t O0 K2 k; X) \% j
1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode., X# ]( `, D; Y1 [
1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property
+ h8 v5 i$ ?& s! x0 u. u1 n1135118 ALLEGRO_EDITOR INTERACTIV Mirror and other editing commands are missing for testpoint label text in general edit mode.2 V3 `0 n0 M: Y7 n! C1 `) e) _
1136420 CAPTURE GENERAL Registration issue when CDSROOT has a space in its path. h, B+ M+ I" l7 N M$ [: }* \& |8 ?
1136808 PSPICE STABILITY Pspice crash marker server has quite unexpectedly
" J( x' [6 J6 R6 y7 L' i, F1136840 CAPTURE SCHEMATICS Enh: Alignment of text placed on schematic page
, i) q+ ~) O# p% _1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs
% [4 N. @6 l3 D6 p& \1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness, b2 V) O# c( j
1140819 APD GRAPHICS Bbvia does not retain temp highlight color on all layers when selected.- Z) m4 b0 L, [+ A, {& U' n# L
1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped* \% J8 f9 W. K: [
1141723 ADW PURGE purge command crashes with an MFC application failure message/ u$ q! I! H1 |
1143448 CAPTURE GENERAL About copy & paste to Powerpoint from CIS: S. e( s3 w6 u+ w
1143670 SIP_LAYOUT OTHER Cross Probing between SiP and DEHDL not working in 16.6 release
& a1 ]& j9 f. n, P, {1 x1143902 ALLEGRO_EDITOR DATABASE when the shape is rotated 45 degrees the void is moved.
V/ ^2 x- N0 ], o1 J4 `1144990 PCB_LIBRARIAN CORE PDV expand & collapse vector pins resizes symbol outline to maximum height! ?8 c) E/ v3 R% Z
1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed
* K Y7 _6 n4 P; H% _/ D1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case
' f% w B4 v3 j8 f: L' s1146386 ALLEGRO_EDITOR INTERACTIV Place Replicate Create add Static shape with Fillet shape
4 P& m7 S% u) k1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail
- w$ }% o5 J2 `+ ^1146783 ALLEGRO_EDITOR INTERFACES Highlighted component is missing from exported IPF file.
' }' P# P+ ]- N5 l3 Z1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block
l, h, [& u( c' l( V1 g1148337 CAPTURE ANNOTATE Checking "refdes control" is not giving the proper annotation result" u G0 \* E: n
1148633 SIP_LAYOUT INTERACTIVE Add "%" to the optical shrink option in the co-design die and compose symbol placement forms
" J: [" i4 v$ D; B' |1149778 CAPTURE SCHEMATICS Rotation of pspice marker before placement is not appropriate0 y8 D0 k6 [! D8 ]) _1 g3 ~' d
1149987 PCB_LIBRARIAN PTF_EDITOR Save As pushing the part name suffix into vendor_part_number value
. @4 L. L! {$ E/ w! O; L1 U1151748 ALLEGRO_EDITOR OTHER If the pad and cline are the same width don't report a missing Dynamic Fillet.& H2 d4 |1 [) w
1152206 CONCEPT_HDL CORE ROOM Property value changes when saving another Page7 v% X! Y& ~: ?
1152755 CONCEPT_HDL COPY_PROJECT Copy project hangs if library or design name has an underscore
& V2 l7 j* f: `) ?% J1152769 PSPICE ENCRYPTION Unable to simulate Encrypted Models in 16.6; f* E. q6 ?3 h$ K
1153308 ALLEGRO_EDITOR DRC_CONSTR Creating Artwork Getting Warning "DRC is out of Date" even when DRC is up to date
. z& }! |1 P7 c0 f, w& z0 O1153893 F2B DESIGNVARI 16.6 Variant Editor not supporting - in name/ Y5 b& H* M4 U, H7 V. w' J3 D4 O8 O
1154185 SIG_INTEGRITY SIGNOISE Signoise didn't do the Rise edge time adjustment." J! `2 t3 Q! \" P& `, N3 E* Z7 j9 x% {
1154860 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
, _ F) G# w7 o1155167 ALLEGRO_EDITOR EDIT_ETCH Via structure placed in Create Fanout has incorrect rotation.% @9 D; C( |2 w) z) w% K
1155728 CONCEPT_HDL CORE Unable to uprev packaged 16.3 design in 16.5 due to memory1 `* e- [0 `0 i# ]8 L# y" I) \$ C
1155855 SCM SCHGEN A newly user-defined net property is not transferred from SCM to DEHDL in Preserved Mode6 i" ]: L0 A5 {( L+ ]2 Q6 T
1156274 ALLEGRO_EDITOR INTERFACES Exported Step file from Allegro is wrong. d! {/ {! {$ S/ ?, V) m8 R
1156316 CONSTRAINT_MGR OTHER Break in functionality while creation of pin-pairs under Xnet in Constraint Manager$ E2 o0 ^8 j6 e0 U6 d8 {
1156351 CONCEPT_HDL CONSTRAINT_MGR Loose members in Physical Net Class between DEHDL and Allegro
% T: Q+ L+ E6 t; d1156547 ALLEGRO_EDITOR DRC_CONSTR Etch Turn under SMD pin rule check through pin Etch makes confused.6 i/ s. r- `( \% V
1156779 CONSTRAINT_MGR OTHER Electrical Cset References in CM not working correctly9 g3 ?9 M) c; s1 g# F
1157167 ALLEGRO_EDITOR SKILL axlPolyFromDB with ?line2poly is broken$ X: N2 { [2 S) q( k
1158042 ALLEGRO_EDITOR DFA DFA_DLG writes the dra file name in uppercase.0 w9 F* z3 G U
1158718 CONCEPT_HDL CHECKPLUS Customer could not get $PN property values on logical rule of CheckPlus16.6.. h3 B/ p- w7 S+ M# p: j5 c0 q
1158970 ALLEGRO_EDITOR SCHEM_FTB Changing LOCATION to $LOCATION in DEHDL does not update the .brd file7 f" A" W. Y) g6 d5 p. W ^0 |" c: R
1158989 ALLEGRO_EDITOR INTERFACES pdf_out -l creates a PDF
0 g, C4 B/ y! N- Y1 x3 F; _+ I% `8 N7 T1159285 APD DXF_IF DXF_OUT fails; some figures are not exported
2 }% c3 H# w0 {1159432 ALLEGRO_EDITOR SHOW_ELEM http:// in the Show Element in 166 do not have HTML link to open the Website% y" ^, g$ A x' ^5 P, i/ U. B& r
1159483 PCB_LIBRARIAN SETUP part developer crashing with
9 a0 }8 Z4 I) o9 o8 S2 T4 {1159516 ALLEGRO_EDITOR EDIT_ETCH Unable to slide cline segment with new slide.
E7 _$ k- W& N% ~( L$ a1159959 ALLEGRO_EDITOR GRAPHICS 3D viewer displays clines arcs incorrectly# R6 j6 e% s% @4 g0 G
1160004 SCM UI The RMB->Paste does not insert signal names.
0 ~7 j4 N+ l1 e, `) m9 s. b1160410 ALLEGRO_EDITOR DATABASE Lock databse with View Lock option is misleading; R6 ~: D5 g( a0 L% _0 y1 R/ V' B
1160529 SCM SCHGEN Schematic generation stopped because the tool was unable to create an appropriate internal symbol structure0 m9 R* n$ w- F6 `+ A
1160537 SPIF OTHER Cannot start PCB Router
8 z1 O( a7 d. M b1161363 ALLEGRO_EDITOR SYMBOL Getting error SPMHGE-73 when trying to mirror symbol
0 z$ }1 [/ p. {; [- V9 K4 V1161781 CONSTRAINT_MGR CONCEPT_HDL SigXp crash when selecting ECset in design
`6 J; l8 X! n/ O0 i n5 c1161896 ALLEGRO_EDITOR DRAFTING Tolerance value added for Dimensions is not working correctly (HF11-12)
# ?) w5 E0 @& t) e1162193 SIP_LAYOUT DIE_ABSTRACT_IF shapes in dia file not linked to the die after edit co-design die
$ {) P; P3 W+ p; K" w: n+ J1162754 APD VIA_STRUCTURE Replace Via Structure command selecting dummy nets./ J0 l Y* ^& F4 ]+ y8 {, R
Q6 s; k! v+ K0 C7 n4 j
DATE: 06-28-2013 HOTFIX VERSION: 012) h' Y2 t1 S8 w* m
===================================================================================================================================' a( @) E( T9 h) W* q
CCRID PRODUCT PRODUCTLEVEL2 TITLE
) |% e. r: q) m: A1 A===================================================================================================================================* N+ H( k, N5 L
914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD
4 E# J* J7 Q) i. ^! u1 ?2 u1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files- g9 C; q/ n$ @+ m7 P% M" u
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
: C) D! N0 C' l/ J; d. q& R- y. Z1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.
7 |; p3 B9 o/ u/ G5 ~! @) f1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line" J: V" ^# r& C. f; k: j! Y
1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.% n6 v2 M1 ^8 ^* l
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.
# e* a! y6 t& B1151458 GRE CORE GRE crashes on Plan Spatial* Q) \; `+ @8 O2 T' D( ?# y; {& _
1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy m E( \4 B p f& H- q. u
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]5 o9 R0 B2 a3 r9 T1 v* A
1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design% i; S- i5 @' w1 T
1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger
$ \8 v$ m& S+ I; j$ u' j1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.
) J c# W' x# J9 x1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places
3 R) O1 j! U0 l) ?! r# L& S: J1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail5 Q: g- j; Z+ n, r5 S
1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.
1 x& C6 ]/ d9 s1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer
! X4 p/ B: _: }% ?: H6 F0 _; `6 K, R y* w
DATE: 06-14-2013 HOTFIX VERSION: 011& k1 V# y. U$ y( `
===================================================================================================================================
/ k. w% g" R8 B! yCCRID PRODUCT PRODUCTLEVEL2 TITLE7 W8 U; ^% U+ g
===================================================================================================================================3 h$ H, V) g. a" u
982306 CONCEPT_HDL OTHER When plotting a PDF publisher output the page coming out half inch bigger in pdf
' n/ P, T5 Q8 V. ^1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers) S% ]; e4 R0 D
1093375 ALLEGRO_EDITOR PLACEMENT Align Module with Zero spacing value space the modules further away the modules should be nearer
- p! t' D6 k/ o, f: }% C( v1103201 RF_PCB FE_IFF_IMPORT Wrong permissions to map file during IFF import
6 [9 W" X& P q4 K! [8 N7 @1106900 CONCEPT_HDL COMP_BROWSER Component Browser performance utility should honor CPM directives for include and exclude PPT/ h5 p4 v4 f; M, S; c
1110178 ALLEGRO_EDITOR EDIT_ETCH Line Width Retention should be controlled via setting
5 R7 s. o- @6 U) x+ a& L1110323 APD DXF_IF DXF out is offsetting square discrete pads.) m5 x1 e [) n; {; S* j: a1 d
1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board9 d4 i5 Z1 v! n$ v+ z; p% r+ l% O
1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.$ C9 i( p0 \( B m0 ^ n
1139338 ALLEGRO_EDITOR DRC_CONSTR The total etch length does not seem to work for Xnets after setting the variable "retain_electrical_constraints_on_nets"# \ |+ S% a; B6 w; C8 k
1139361 ALLEGRO_EDITOR DRAFTING Angular dimension tolerance is incorrect when plus minus tolerances are equal.; y& j* E) p E# b$ E
1141882 ALLEGRO_EDITOR EDIT_ETCH Allegro Crashes during diffpair slide1 a5 H( h; T6 t: _3 Q
1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero
& H4 K1 b" O- p) X* M+ o1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP
- ]2 \% f6 y! J& I( `5 Z4 B2 d1145243 ALLEGRO_EDITOR NC Duplicate drills found in the NC Drill output
5 C! R, X6 j& E9 A4 ]& ?$ h1145260 SIP_LAYOUT DIE_EDITOR Enable "Copy" in die editor
+ k5 n* \1 Q5 c) w ?7 v2 v1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL
$ ~7 P/ E/ v# R1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.
- J& R2 ~# f; c; O# s1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added
' I, w7 n0 B' a# X8 l9 J' T1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps
7 U) Y1 A9 o7 N) S- E1146865 ALLEGRO_EDITOR DATABASE Allegro crashes when trying to place mechanical symbol
, w7 E( _$ B9 m! {3 Z1148513 ALLEGRO_EDITOR OTHER Importing a subdrawing file causes incorrect net name assignment.# S7 F" e- k9 c- E: r2 B+ j) Y
1148734 CONCEPT_HDL OTHER Logical Symbol Text is turned upside down after extracting PDF by Publish PDF
# \- X) j/ f2 e h1149025 ALLEGRO_EDITOR INTERFACES IPC-2581 imports cross-hatched shapes as solid
b1 b" m; l+ H& l1 ]7 ]1149948 APD OTHER Stream_out hangs on this design -- hang processing merge of overlapping shapes using poly_deletecolinear_only()
' Q6 d% _5 e, O7 J1150274 CONCEPT_HDL CORE Uprev from 16.3 to 16.6 is not preserving RefDes
5 q$ e. d6 k6 `) [! W. r1 d; n1151450 SIP_LAYOUT DXF_IF DXF export from CDNSIP missing symbols
% x3 U; p, K# m0 h* h" o
3 }1 b5 n( ^8 ^7 \DATE: 05-25-2013 HOTFIX VERSION: 010 G/ h" P2 W0 y5 J. l( u
===================================================================================================================================
2 g K8 }+ O. T8 m% ^& q' l) z# m! _/ QCCRID PRODUCT PRODUCTLEVEL2 TITLE9 e8 R/ H; a+ e9 {
===================================================================================================================================5 i* B' V. u7 _
1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
2 |( E6 O1 d, s0 W. c0 S6 L/ H) t( K1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border; L! D- \5 C1 o( P+ X
1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files8 g4 W* ^" i" G3 f* O c/ c
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor9 V! S, h% ~* j6 S* Q# p5 r
1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6
$ C3 \" m5 u) f4 S! I) T2 v. r1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border+ ]6 w' j/ \7 ~" X ^0 t
1131775 ADW LRM LRM error with local libs & TDA
7 v r1 N) N0 r9 V2 J0 L) T% B1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4) u1 i0 W+ X! r, v
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo$ a a$ C y0 L/ K3 ^
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
( m% P. U9 L# D2 f8 @1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur
; |# P, ^4 s7 k7 T% Z- `1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?" |, @6 N$ _' u3 D6 }% G
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
. ]( \, F1 F$ j& J1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
: r+ w4 o7 P8 i, v/ D1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro5 {" E3 t" s0 Y6 G7 L/ n6 ^
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.# b: N" e, t+ H$ S7 Z! I' k$ [
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
3 ^8 p- A+ `, [3 [6 W7 K& x R* J+ o1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
) x% a$ n& C# [0 Y1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF/ A) F: p6 m; e" p2 K
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering. M A# P! g) {9 {* [5 v; g
1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor
0 D* h$ t+ C! `) F5 n. ?
% g, z- o6 m3 F7 }% \; K2 G, m5 EDATE: 05-9-2013 HOTFIX VERSION: 009
. D0 l3 w& b& D0 G, ~===================================================================================================================================
) e3 Q3 b) h7 |! XCCRID PRODUCT PRODUCTLEVEL2 TITLE
, o% P8 C6 P$ @/ O! v===================================================================================================================================4 I9 c K1 w- p/ ?$ ?
961420 ALLEGRO_EDITOR PLACEMENT Regardless of the aspect ratio for room of side The QuickPlace by room command could be placed comp8 E8 A( u: X3 Q
1079862 ALLEGRO_EDITOR SKILL Ability to create IPC2581 layer mapping file by Allegro Skill function* ^5 r$ n' T& ]( g
1080734 CONCEPT_HDL CORE Repainting of grid lines during pan or by moving window show as solid white lines instead of gray da
) U7 n% x1 D& T7 i1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB9 r2 I, M P c6 A& F
1107547 SCM OTHER v15.5.1 tcl/tk code not recognised in 16.67 t% H$ n2 ?! L& F: B4 S Z
1110209 CONCEPT_HDL OTHER We can move symbols and wires off grid despite the site.cpm grid lock
0 F! a- U" Q6 U* x% t1117825 CONCEPT_HDL OTHER SHOW_CONSOLE_ON_LAUNCH throws an unrecognized directive warning in the schematic editor3 Z5 i' ~# r. _; P J7 e ^$ y7 |
1118874 ALLEGRO_EDITOR INTERFACES Oblong pad shapes are not shown with correct orientation after DXF export from Allegro: n4 e) s% c0 {7 |1 Z. j$ _
1121873 ALLEGRO_EDITOR INTERFACE_DESIGN Importing Bundles from Net Groups does not allow any further editing.# S `& Z4 O. t1 x B1 }
1122933 CONCEPT_HDL CORE Newly added Toolbars are getting invisible after re-staring Concepthdl
, u& c) W+ U1 f6 z/ h: x: q2 @5 K1124587 ALLEGRO_EDITOR INTERACTIV The Shape Expansion/Contraction command should also be available in EE mode.2 L8 ?9 m: d' { [6 T3 P
1125895 SIP_LAYOUT LEFDEF_IF Tool crash while moving the slider in the Filter options Macro tab form of the co-design die library manager
, K0 O a7 `+ k, y: `1125962 F2B DESIGNVARI Custom Text in Variant Details dialog box is inconsistent
; k7 Z9 o! h/ G0 E- x$ e6 D* j: H1126096 SCM REPORTS Two nets missing in report# c' Q; u$ T& N0 V! ]
1126134 SIG_INTEGRITY GEOMETRY_EXTRACT Attempting to extract topology hangs APD* M3 H# Q. ]( w% i5 I2 f7 K& u1 i
1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.
+ s2 G* D. Z4 ?- S) W1130280 ALLEGRO_EDITOR MANUFACT stream_out command in 16.6 seems hard coded to look for a design called stream_out.brd
7 W }6 Y) Q+ m2 L! c- P1130737 F2B PACKAGERXL Error - pxl.exe has stopped working) V6 i9 w( v. g! i7 s2 r5 r( `9 @
1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters
- \6 s5 _5 f" i& v7 {: t1131764 ALLEGRO_EDITOR EDIT_ETCH Line segment will not slide using the New Slide.: [0 w" F/ g9 [
1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.
) e7 i6 Q) J+ x( J6 E' ]! `8 F1133311 ALLEGRO_EDITOR SKILL ?origin switch is not working correctly with axlTransformObject while rotating shapes
. J, J! a' e, E k5 D, Z) E1133893 SIP_LAYOUT IMPORT_DATA netlist-In Wizard crashes
5 i( W9 p, @& W( g4 j. A
. \) j$ r- r6 h/ T3 t# Y, c" Z* [) nDATE: 04-26-2013 HOTFIX VERSION: 0081 I/ Y d1 R- o5 Z- |' J
=================================================================================================================================== {, K# }' c1 U9 ?$ y% n
CCRID PRODUCT PRODUCTLEVEL2 TITLE
! C) X8 W& m. h( b9 O===================================================================================================================================, U* e T- r- u. q S0 f6 U
876711 ALLEGRO_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit* O0 X: L5 o* K: d! ~. C9 `
1080386 CONCEPT_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation$ \9 Z5 t& S! U1 G5 V: Y% h
1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device, [1 X7 Y1 e8 R+ d$ e
1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
8 o9 w' O5 e" O2 M; `1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section' M9 S# ~# r. n* ?4 A/ M x! Q
1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running
0 N" b. g& v1 q1 J1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.% j5 O5 K! }. h9 s' x$ a X
1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence @, E, ~+ y$ H8 i- i7 Z
1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.
& a& m2 } y- L0 D$ S1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason0 y6 @" F T" y9 G0 \; F
1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.
2 Q- m! s% {% U. W* c* z1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?1 I( z& h2 h% `) Q, n% Q; d
1120414 ADW LRM TDO Cache design issue
$ ]2 Y0 W0 \7 [% j9 Y% Y4 {1121044 SIP_LAYOUT SKILL axlDBAssignNet returns t even when no net name is assigned to via9 t8 E- q9 d) J& R+ N Z
1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups" X ^% h5 O) O/ I5 o9 v* w! ^. U9 U
1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it, X( M! A# {5 n& Y9 ~ R* u* a
1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.
4 ]: T. U, u8 r& V4 _0 H1 i1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced |4 c# W9 @( \$ D3 M
1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.& E1 z$ p/ i5 x2 Q# ]4 t/ v
1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable
+ y' y6 \1 r$ [% @' z1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file
& Z9 k& C+ m: I; R w1123816 CAPTURE PART_EDITOR Movement of pin in part editor3 e3 C/ s8 G$ F) ^+ x
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 500 V( p' C* b, V o3 L
& x& m5 g! V9 l( M6 iDATE: 04-13-2013 HOTFIX VERSION: 007) d* M- k& C' C' M& C- j6 Z8 Z
===================================================================================================================================+ Y/ z& K/ }( {
CCRID PRODUCT PRODUCTLEVEL2 TITLE* |0 R) F9 ~8 k0 D
===================================================================================================================================
- w0 X( @9 V8 b. x' g1 V$ V1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die/ j( t% _* K6 g" R
1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6/ C( u& y% k+ r6 z* b, b; ?2 }" r& P
1112295 APD DXF_IF Padstacks� offset Y cannot be caught by DXF.
. D7 X, X! f2 Q! z5 _/ V1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components
# P" J4 S% Y$ I6 R# @8 m- N1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
# K# y9 l2 m" c O( _/ t8 B1115491 ALLEGRO_EDITOR SKILL telskill freezes command window5 g" t( k+ L/ u" _( Y% X- {
1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
1 Q+ b: |% d) } m& b" x1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer." |/ q; ~' g; g4 E6 l& Y
1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear8 M8 ^0 P. A) _$ X4 |' k, G
1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks
/ R" M* m% m$ p. I3 T9 q1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?
' k5 p! ^) H5 W" {2 Y! f1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh
7 T; o2 N& l& d' T1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh4 l5 A+ G8 Q& m9 q. [3 r
1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors0 k/ N* ?1 M; Y5 R; v. Q7 W
1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6
/ Q1 F7 V( h9 f! Z" N) w1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently
- o! Y3 d- b2 ]. n, H1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps' _3 H! b4 h4 W; c4 F+ Q3 E$ W
1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks
5 w! ^' {1 M [7 {. \1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.3 Y1 N& V; d' W7 f4 _1 k5 d
! j* B0 D, d2 t4 `, m" I) |# BDATE: 03-29-2013 HOTFIX VERSION: 006
1 q: [+ y3 q# U5 X) ?- ~( i===================================================================================================================================7 G* f U t* k6 a! y' A" M% r6 n
CCRID PRODUCT PRODUCTLEVEL2 TITLE
( ^- D; P+ _' ]% k0 t3 M' K===================================================================================================================================. N! k. g" e, v
625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.
5 H3 S: u2 S2 o642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep- \3 a2 v; @& ?* ^
650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".: x4 y+ R9 x- q+ o; D3 L
653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend
4 c9 h {. ?. c687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect) S8 v3 i8 ~5 k
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
: M2 j6 v; A, E0 m8 S825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other1 G H, X2 d# J% I/ K, q4 N6 ^
834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
& O3 X. b3 D, j. C A" n835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
& k+ @/ q0 S$ N z c2 `1 D" o! {868981 SCM SETUP SCM responds slow when trying to browse signal integrity5 z2 S: W3 c. n1 H" K' {
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
9 F9 B8 ?; v n5 t& w5 m: F) o- I) t1 q873917 CONCEPT_HDL CORE Markers dialog is not refreshed: x, C2 L: s$ o5 B1 y( v% f
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
- B; s' {7 ]# |/ S888290 APD DIE_GENERATOR Die Generation Improvement8 @" A) a z3 l/ f( L
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator, d: c. h' q- }& l5 H- q3 g# u
902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice+ Y. v3 S/ K O1 f
908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM
, m8 `4 a% c/ o922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols% c1 z0 J1 d2 u! [% I; t
923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences6 d/ K6 n" o5 O- S
935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC% B$ {+ I, d) g9 ]' j/ y1 @
945393 FSP OTHER group contigous pin support enhancement
# ~6 _/ |* U0 e8 z- \( j! F3 f" z969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database& Y( n v" a8 P R2 u& _6 X; Y2 B
1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes @( I% ?/ O$ Y" I( ~( I' e+ ~3 W
1005812 F2B BOM bomhdl fails on bigger SCM Projects# r) a6 l1 @) t9 N; b3 a
1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture- f- s" n% i( E
1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names
( o1 h' j/ C0 E& ~1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net8 G+ d5 c0 W0 _( T: y
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical4 z d8 p" [1 P# k$ L; E
1032387 FSP OTHER Pointer to set Mapping file for project based library.
1 r4 R" E' u4 E1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with 縋LL PLL_3 does not exist in device instance�, j c1 `& Y' `" r
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
- M( w7 K% J8 @* N4 o1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding* D$ |& h1 n8 h" N' Z0 _- D
1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.2 A. y1 F' w8 S; ]) B
1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type
6 p2 j% w4 l+ L1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll; @( O& N/ H, g% P1 |
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation- N! I7 e' Z8 N( t0 f* W0 X6 @
1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects4 m( w/ i9 V( j% M7 c1 \9 z
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus1 F$ G# K3 w8 G2 ~0 A1 M
1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts
% ~, m9 |% m C3 o/ x' g1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs
. x' w8 j: z9 N5 D1065636 CONCEPT_HDL OTHER Text not visible in published pdf$ S+ z+ w2 w4 S- R4 [
1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings4 I0 k% k- ~8 p8 A( \ v
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary: H" }2 q+ G0 k& V- a
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
) j$ @; f; f6 O( p( O1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic! l/ v W0 ^7 u6 B
1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down0 x, @ C4 e. j+ M. F
1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45( k, `8 o4 J$ w/ M4 k7 N( D
1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal0 S; c4 _; T0 G! Y# T) t
1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
1 w* E a- z% [- G) N. ]) [ E* m6 P1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design." R$ n- ~/ V% ]3 D4 F* [& ?
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)0 B* j' Q8 F5 b" r4 `
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die) A2 N6 @' k# r6 D: S/ N9 U
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
0 _# r, a X, ?0 A7 C& S# W( g: F1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut6 Z3 b6 m0 F; O) P* v5 K
1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects
0 E+ K+ O$ }! q! T- B: p) J9 l1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format4 c$ E( A8 F0 H K3 v
1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net5 G2 Y# a4 @9 M& s3 G; g$ x
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic8 B6 B8 [& w# U, L) T- v+ W# A. G
1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
& `# g. ~* T# C0 x% l8 e1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.
5 ~- p T' e4 F; P( y. ]3 D. c1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.& F4 m7 P8 ]* g1 u& r( m: Z
1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors6 e, y0 }4 s( S. R
1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.+ x5 N @% j* W5 P' q; P2 t
1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition
2 R/ s2 \/ q) R5 D2 `! _ {1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor
) F9 G- F) T% A2 q; s1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
o& ]" _2 a! C A0 |1 y1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5
4 K3 {' Z, |: L* |8 t2 z& ]1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.+ S+ H; n D/ ~8 L& o2 ~
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate) X: ^: }2 ~ L6 J+ d! J) ~) t$ @
1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3
3 g2 Z+ m7 z% q1078270 SCM UI Physical net is not unique or not valid
; ~; I; ?% l8 P( _2 \4 [) R1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted$ y2 ]7 v4 ~+ d# m& v/ a
1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle4 A2 g; G) j# E y( A
1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs
: D: r5 L) F* F) _. o1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage") ]; o3 Q! P8 D; l" R2 K/ Y: P+ `: E
1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters
: w7 P; D" B. h$ R& e; e, Q" P1080336 CONCEPT_HDL CORE Backannotation error message ehnancement6 N9 h1 |& r. z) B+ ]
1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license0 V4 s( [$ g5 M' O
1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd7 ?( b' {+ `) Z$ V' a0 ]
1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error7 _$ M8 }' T8 f4 R, a" ]9 K
1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.
5 U" ^8 \6 p, h! O% ~/ V1081760 FSP CONFIG_SETTINGS Content of 縁PGA Input/Output Onchip termination� columns resets after update csv command
; ~3 Z) k9 W4 E9 X/ M K: G+ z. Y1082220 FLOWS OTHER Error SPCOCV-353
! X, [+ `8 J# ]1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.% F, n" a b* r& l( c" G
1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command
( [6 t& E3 w% c, p3 k% t1082737 CAPTURE GENERAL The 緼rea select� icon shows wrong icon in Capture canvas.
" M0 |' H: U+ i4 I5 A4 q1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name
' {0 e2 ]: {9 }; Z9 d5 N/ M1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way2 u! P4 i- j& s9 |; X* B/ f# `
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher
$ A& s; C- `6 _2 v# O1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI* d7 W4 s$ E/ \; R
1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
/ L* i: a5 w: ?9 [1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.1 E6 K1 Y) X3 f7 ~# b5 E
1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates
@: ?! n& |- n, a- Y$ f( z0 k) h5 Z1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters* Y8 T' u3 R: D
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.& `% e4 \" C7 k: {$ p; y
1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results
) K$ V( g* Z) |1 ^1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.7 Y% Z) @ T( f: A
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update& {- W& O3 H4 v1 P$ _5 r
1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO+ P: g0 r# K2 e ?7 G
1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working7 M0 n5 K$ l* j& \
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.% w- b0 u5 {' h; o, x4 k
1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design
" b& o# j9 ~+ S/ P% F1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated
3 t, p3 ^# U) t3 N' c3 [1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins
( B, _2 D9 |5 W9 b1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity. k. m! K# X/ L5 m7 N6 A( ~ x
1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.5 j# g2 U, e3 H4 `
1087221 CONCEPT_HDL OTHER Part manager could not update any parts.7 a' [3 a: R' k: g7 A
1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space; C9 F5 e/ H+ w! c
1087295 SIP_LAYOUT EXPORT_DATA Enable "Package Overlay File for IC" for concurrent co-design dies too8 D: o2 f* ~; M# I, b" T
1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice
! `! [' }+ |5 \8 t* W: ?) _1088231 F2B PACKAGERXL Design fails to package in 16.5
6 u1 M3 V* H' d7 [+ a1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.' j2 \( _+ ]+ w2 l0 }
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor
& B7 ?- j6 X( N! X1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager
v4 R y7 c& P; l1 A1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?; E3 M3 a% t6 E
1089259 SCM IMPORTS Cannot import block into ASA design
% a* t0 h' a6 H6 z8 h6 L1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form
" k) A& m c7 h0 S1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project) L$ T, w, d+ r' f0 T* E1 s
1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory2 n) B) M2 H4 {5 |/ q
1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
1 k: j. w0 b# k& l9 H1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB1659 }) y* A8 S$ S
1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.
- F3 N+ f$ ]8 _/ E1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22
" C, t9 v A7 P, `. `1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.
5 X4 u; z" F7 d* f$ J& O$ I1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.+ }1 M$ `+ J& b- {. r
1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled$ j6 N5 t" h4 l, V' w8 G2 {8 A
1091359 CAPTURE GENERAL Toolbar Customization missing description
6 S; m- H+ J( n7 P" Q9 I1 \1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
) k3 L1 Y, ^7 h8 c1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time
/ I; q j b* I) ]# E. M$ U. r4 h$ f1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5" L. S% D* Z+ J2 F
1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design, a6 A8 v9 l% i6 A" K* t7 |
1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled
7 F1 m4 q8 d6 p! w9 z2 a1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters
0 @1 J* t' Z$ s2 U) W; u+ W% _1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error
' w6 w L% S4 t1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder
, C2 S3 q3 M8 S- o1093327 CONCEPT_HDL OTHER Getting error SPCODD � 369 Unable to load physical part in variant editor/ l0 ^9 i& _. I- o, z
1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.8 N6 ~! R% z+ p0 h, ]
1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time: ]& B9 G$ K# m9 R( H, ?! p6 m
1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.
" o' E2 e" W: z4 b, F$ F1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
1 y2 s" W( o+ Q' v1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic
3 i8 i; R+ {- h: B) v7 T1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5% z- Z- i) k5 h( t( ]+ n( b4 ?
1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet& M+ @1 C# H$ ?/ [ u1 c9 g
1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die
a4 ~6 Y: }/ b" A6 ]1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block
7 f- ^$ Q/ t/ ?! s/ x+ C* w5 N! |& C1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3' `$ }; K0 d1 t& V/ A8 [
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results- Y a% s. @% o K
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import
, F# @7 N( W N% p: b8 c1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically# Y( e0 \( S M+ i3 w1 T! P
1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias( a& |( Q9 z8 P
1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate
; S) o8 D9 }! y9 q. P0 g# M/ g+ @% ]1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors3 \( J- ?, A! e( [6 Q2 @3 g# z
1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL
/ h" e! }% w( Y; r$ @) v. ^1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly." Q6 N6 n, p w' \$ S9 {2 z
1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side5 c% h) K/ a, G- I* d& K+ I
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command
7 b" _0 @$ h! N0 W0 }7 N( {, a1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.; R/ k, c* e' @/ z
1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives
( T3 j# _0 r( a4 a# }2 L1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork
- {8 n: r& U6 O9 r) A1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts" T! C9 c3 n. s7 b/ W
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy
9 F4 @( W) v+ b. l1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.& x- A( f0 \2 o: K! U1 H
1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties, H0 }5 c, B( @$ {6 ]$ }, f
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6* @- N) S2 B9 A% Y' z/ I$ G
1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad
" B: h" |6 X2 M' g9 y% u9 e1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P38 f" T% X6 B2 e1 U; V" l
1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad
. _0 N% h' \- r" m0 Q1103703 F2B DESIGNSYNC Toolcrash with Design Differences$ c2 S$ ~. l% B. [7 j
1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view7 Y# P3 o1 w! x3 j
1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6
6 i" M+ k4 e0 F, g, N1104121 PSPICE AA_OPT 縋arameter Selection� window not showing all the components : on WinXP
/ T! Z( e1 M/ r& K5 w: W1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly0 E. k# W' X1 j% o. O& [
1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM
" I/ X+ H6 J% k9 Z6 g: \1 O; z( D0 f5 u- _1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.5 j$ v4 {9 _2 C; U: g+ {
1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.! y1 s4 x; r% r: P, L Y
1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form" T% v9 S# u, b; B/ k& q) X; V
1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part
6 w& Q- {8 i$ a6 O1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked& |+ z6 J% @: K& Q
1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
. ^, L- G' S- Y8 H; j0 ~1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6/ _% C6 N" z- K+ f; O
1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only
/ N$ b1 ]& r. v1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid
# k4 b% j1 W- i( ?9 o$ R1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.- G5 R9 x) q8 g$ N* ^
1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param2 [& Y& C8 `: x ~7 D
1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish
+ E- o- p7 T7 Y G1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).* {# B7 g6 G% w% K5 O! f* E
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke
: E, v. E1 S. {1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.
% H/ G0 W9 J* a. c1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode E9 u; U: o$ F3 v
1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs
. j! Z& W- [( V) }1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6
Z) Y$ [! B6 m1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins., \6 v2 z* `0 ?0 u! J* D
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
/ y2 I: [! ?; K; K& v( {1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6( D3 g- _7 m3 c
1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset3 R4 {% S/ K7 c
1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters7 p; l R% J/ p+ h
1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend7 T3 _6 M, ?* a2 T6 _; ~1 F
1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP0 g5 t+ @' O$ D
1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint
, S# D5 w! x; I. ^4 v1 f! m1112774 GRE CORE Allegro GRE not able to commit plan after topological plan
( q% ^) j3 B: h% w1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.3 R3 E# u E0 {2 x) Z7 i' g+ W( b
1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file' \. I) Y4 H3 @* g- O
1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.68 _8 @) z! Z' z, i
2 P. k- ~0 k4 L- g+ fDATE: 03-7-2013 HOTFIX VERSION: 005
( @( O* L9 u" A% M( s0 n! B- @===================================================================================================================================
6 w& y! Q' K' ?CCRID PRODUCT PRODUCTLEVEL2 TITLE
3 z6 D0 O$ f: Z( b; R===================================================================================================================================
- C' D/ K6 i* z5 U5 g1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 11021 N8 M: a A! w U- e
1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed, T1 Q/ t5 N$ J* [% Z; O1 A- u
1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently* d% A9 P, a- L( W2 Y
1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind- ~$ P% G$ T1 Z/ a! @
1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view, C# c5 j( @4 B( ~
1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed+ f3 }% E" G, Y8 r6 [: b
1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM
/ J S/ ~* F q0 L5 N: a1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.61 A7 h1 t4 j# X; ]
1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement.' q1 N3 X$ ^( q2 }6 p
1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design: q3 L- A' p/ A) m1 ^. C0 O
1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in OrCAD PCB Editor Professional
" ]8 E/ c6 Z$ D2 o: W7 E, P4 n% a
1 J3 R( C! X2 [- p8 k! zDATE: 02-22-2013 HOTFIX VERSION: 004; s4 x& Z: `: C! ~: t9 n1 g, [
===================================================================================================================================
1 y7 H- l4 E8 r+ A |9 y- wCCRID PRODUCT PRODUCTLEVEL2 TITLE& K0 r* L: E3 o0 N0 A' P
===================================================================================================================================
) [" @7 N1 n& r4 s- B8 s4 f1081026 ALLEGRO_EDITOR GRAPHICS 3D Viewer do not show the height for the embedded component correctly
[1 x1 \& `. F3 b1095225 ALLEGRO_EDITOR EDIT_ETCH The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing: A, Z. S q4 Y$ s6 G9 p' X9 N) Z
1096356 ALLEGRO_EDITOR DATABASE Cannot Analyze a Matched Group in CM
, H: m2 _+ f _# I% C6 g- X1097481 ALLEGRO_EDITOR INTERACTIV Allow replace padstack command in design partition% U5 \! s. C& N
1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend
8 f3 Q5 X: s- Z1099958 ALLEGRO_EDITOR PAD_EDITOR Library Drill Report producing an empty report! V' o% v9 J0 C6 j
1100401 ALLEGRO_EDITOR OTHER Invalid switch message for "m" for a2dxf command
& Z0 y0 S) |+ v% x" P2 Y7 ~1101026 ALLEGRO_EDITOR OTHER utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit.- W3 u; {# L8 a1 A, l' m- s
1101064 SIP_LAYOUT SHAPE 'Shape force update creates a rat4 S1 m9 G4 c# l3 M: z6 [* @
1102798 SIP_LAYOUT OTHER Stream out puts offset pad in wrong position if pad is mirrored but not rotated.
2 m$ L% F/ L9 w) d) o. ?) G1 I+ S* B' b
DATE: 02-8-2013 HOTFIX VERSION: 0033 X8 m- H9 P5 X$ t" Z" g
===================================================================================================================================+ t# C m' t. l3 ?2 S; V/ _
CCRID PRODUCT PRODUCTLEVEL2 TITLE& Y F/ W a2 D
===================================================================================================================================5 `# B" c( l8 p5 V" \+ M! j5 J) {
1077728 APD EXTRACT Extracta.exe generate the incorrect result
9 p1 s% U! j7 M1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF+ D5 U0 a# P# n& n$ U* [ ?
1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer
9 E& s4 f/ E( |8 @8 D( p2 y1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.8 s& d8 c$ e! y4 u7 e, `0 p( m
1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on# B+ G# }* c1 }8 R6 E
1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent2 E% i7 |5 P, V% Q
1094788 SIP_LAYOUT WIREBOND Wirebond edit move command
; Z( i, w; E. t! q2 j6 K1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor
8 D( G6 B; A# M0 a- D/ P) L" B1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn縯 show up after 縎uppress unconnected pads� option.
$ `0 W) `3 q% R( A0 O1 a% v/ \1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff* ^* K* i/ }: J' X: r
1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible
0 {" O: q8 U% ~3 {1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35
7 q( g9 h' M$ w9 l3 g1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.
) T }1 F9 w& w' c+ h+ W1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.
& C! Q4 u! E& \3 C+ y9 ^3 s l3 N1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.
* f* k) g1 q4 I2 Y* v0 D- B& V. E$ T" H& O2 I5 }4 M
DATE: 1-25-2013 HOTFIX VERSION: 002: g4 w3 W! m6 A" Z5 a! n3 I
===================================================================================================================================0 K) e$ }0 _4 n8 h: ]* \3 k
CCRID PRODUCT PRODUCTLEVEL2 TITLE* a' f/ I' q3 E* o, c: }( j
===================================================================================================================================$ O/ ]* W/ S2 l2 N% n$ Z
491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute
% }5 }8 w9 v, {# l |863928 ALLEGRO_EDITOR INTERACTIV Segment over void higlights false "nets with arc"
O. T9 d# M) v( [" A1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes
& c1 P1 ^- J0 k" p, \+ F1074820 ALLEGRO_EDITOR GRAPHICS losing infinite cursor tracking after selecting the add text command with opengl enable
. `4 O7 n* Z( g- f; o! w+ |1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33! D1 e/ N% `# H) s9 c
1076986 APD WIREBOND Wirebond Adjust Min DRC does not maintain the finger position in the same sequence
H+ U: V+ m, c) r1078031 SIG_INTEGRITY REPORTS Requesting improvement to progress indicator for report generator( n9 X! b# w( Y/ j' H% V
1080213 SIP_LAYOUT WIREBOND Wrong behavior of Redistribute Fingers Command
) k" V5 k# Q4 i* K( ^% X' F1080667 ALLEGRO_EDITOR GRAPHICS Allegro lines with fonts not displayed correctly in 16.6
( @8 j; n/ {6 j5 a/ n* s5 F1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note.% P+ G0 l7 I4 B$ o" m- _2 A8 j
1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.+ I! X2 s- g6 D# {: B$ w
1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL.( {0 z, T& l+ U+ j1 x* F
1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0$ D' k9 F* `0 S3 {7 H
1082595 ALLEGRO_EDITOR COLOR Infinite cursor remains white even we change background to white
; j0 Q0 \, ?* [' n; ^1082704 ALLEGRO_EDITOR GRAPHICS infinite cursor disappears when using Display>Measure' d' B7 ~: O: ~+ T+ N0 Q; s/ c( k
1082715 SIG_EXPLORER INTERACTIV Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer0 A G/ H' ]4 h" K0 _% ~" U8 o
1082774 ALLEGRO_EDITOR TECHFILE Import techfile command terminates abnormally when importing a generic techfile.) {4 Q+ ?& F# u1 i
1082820 CONSTRAINT_MGR UI_FORMS The configure generic cross-section pull downs do not work.0 |1 y! ]4 }/ X- W
1083133 SIP_LAYOUT INTERACTIVE SiP will crash when using the beta Pad Rename command to change a BGA pads name.( `8 Q9 d) r5 Z* I2 @
1083158 ALLEGRO_EDITOR GRAPHICS The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.6& ^" L( g* v( S7 R( d8 G7 I
1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout
0 M o" F. Z, s0 c1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file
! O' u# m; X9 D/ z$ q! w) g4 ~1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing.+ ?0 i8 a" f( c, }
1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.% n& `/ e9 |6 B9 ^: [, ~! L ]
1084166 SIP_LAYOUT DIE_ABSTRACT_IF Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties, I% i$ |+ K) j; c- V
1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error
2 k! X, c* F1 [0 m% ]5 h- f1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric
1 O0 |& n4 t/ v& U+ R; W4 n0 x% T1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol.) M5 D1 {0 F! C3 y
1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue& m: z7 @, i* }) }4 {) ?
1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command
! T/ P: `; S) o' m; |! k/ O4 N9 o1085139 ALLEGRO_EDITOR GRAPHICS Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled/ W# {, x7 l7 S* I6 m" O& J
1085187 SIP_LAYOUT INTERFACE_PLANNE netrev with overwrite constraints fatal error
0 G8 \$ a- A: ^+ H0 ^, v5 A7 E1086402 ALLEGRO_EDITOR GRAPHICS Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled.0 x: ^) ~1 J8 j$ ?3 ]
1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function3 c9 V u4 Q9 Z8 j- w7 R9 j
1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command.
1 Y$ T4 \1 v0 j9 ]6 n0 S/ ^1088412 SCM CONCEPT_IMPORT why reimport block adds _1 to the netnames?
: m, Y! m1 D8 W1088958 CONSTRAINT_MGR INTERACTIV annot create Differential Pairs out of nets that belongs to a Net Group
1 o2 s4 r( D# i& W1089336 ALLEGRO_EDITOR GRAPHICS infinite cursor and pcb_cursor_angle2 i: L0 h1 r& ~: t/ H6 p
1090689 ADW LRM LRM: Unable to select any Row regardless of Status
4 ]- }+ n+ j: x0 D1090955 ALLEGRO_EDITOR OTHER Cancel command crashes PCB Editor when add rectangle7 x0 T+ q+ Q+ f; U( a, R+ |3 H
1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas.5 X3 ?$ t) T7 v
1091218 ADW LRM LRM is not worked for the block design of included project: b" r O$ S! c0 O, O
1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads$ @. d. s* q; R0 N. k1 K
1091706 ALLEGRO_EDITOR EDIT_ETCH Allegro crash while routing after setting variable acon_no_impedance_width j1 _2 Y/ _" F2 c. A% H1 P
1092916 CAPTURE OTHER Capture crash4 E8 k* c( L3 m0 u
1093573 ALLEGRO_EDITOR DATABASE team design opening workflow manager crashes allegro. possibly corrupt database
4 S6 W% t3 Z% l; M+ ]; t9 f2 U# ~" ?) d1 s
DATE: 12-18-2012 HOTFIX VERSION: 001
) h% B, H$ j3 k===================================================================================================================================+ O% t: b! ^; S
CCRID PRODUCT PRODUCTLEVEL2 TITLE
, x& Q, s$ C3 n7 E9 f( F& B===================================================================================================================================. }7 S/ I& S# \+ T2 {" J' ]+ Q1 ]4 g% B
501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap
* H. U( q6 Q1 G' X# H8 C745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched/ y7 P9 \9 w7 s/ G2 S/ m
825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted8 Y2 a, u: I6 \% J
871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash* i0 u @9 O8 W ?% Z$ j
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
# {2 [. u% O- `/ {9 n$ A; }898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore9 U! d7 l. A) M7 f2 k7 f% w
923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties
5 s2 }7 Z2 O, x' R: X$ o938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic3 R9 h$ k/ R" G7 k
947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.
/ V& N9 w' q3 \. ?6 B% S968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
5 N* I6 U' N$ }. I2 `3 I' {976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor* ~) s4 f5 R% }* d" E: L2 _
981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected. S# V4 d* K( j, O( u* K
982273 SCM OTHER Package radio button is grayed out
8 n$ O9 p. H" `988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command
' R1 C; Y g$ C0 o7 g989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode
' x& n9 C/ \% n+ _- b( g& j993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).! Y7 i7 [( P# r2 Y
996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections
8 g7 v7 b$ Y. U+ `; E997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
1 T7 S$ K+ |5 B" I1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model
: t' Z$ U$ k/ ]9 r8 ~1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs
4 j+ S4 K3 j( e6 [1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg$ K( C. E9 ]: y! C
1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
/ C( O, Q% O6 _4 _1016859 SCM REPORTS dsreportgen exits with %errorlevel%
7 @# X/ X* l, H2 d0 t' [' {1 p3 W1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin
- _1 X) o- Z& k: R: m0 H8 O" `1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs' W% v0 G' v7 G0 d
1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts
$ P: |' _! [, j- a% z8 A1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
, J9 H7 h3 `; D4 s `1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire." r- w% i5 ]7 n# T2 w$ O
1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
) t. J! P9 E1 U2 l1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out
8 ?8 \* h; P2 @+ D e9 \9 q: A1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist
/ j9 T! v$ Z( _. r* O0 ~/ I7 t1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed
+ @+ g5 N, Q5 a1035624 CONCEPT_HDL CORE Options pre-selected when launching base product
- j3 X" u Z' |0 @9 a7 T( j6 S5 e1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly& m w; s8 N. J6 G/ k1 E
1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.% [- f) p0 I9 c t6 ^' B4 f
1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)0 R4 o8 N W/ K7 e7 X9 p4 U
1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol; w0 L6 O! k) S; p( H
1038285 SCM UI Restore the option to launch DE-HDL after schgen.
3 [- X+ b4 u' @1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."
4 S$ ~7 V5 d I7 Q: T0 d+ G1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro
, E9 |( `1 }8 i. s0 N% r1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected. Q/ b9 s6 A) P
1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing' v e" D$ u& G7 V U6 y/ k9 e
1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found.
8 ^4 d+ T7 S. U8 `* ^3 V: |1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.
: N, F# m' F' j1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu8 }9 Z6 Z# Y8 i. p9 Q8 w( f% t
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.
1 o* r, ?# h" q; d5 a1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow2 f4 y% _! q, f5 }
1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory
" Q, v- J3 {- E$ W7 [, P0 K1043903 GRE GLOBAL This design crashes during planning phases in GRE.1 B1 N# O1 ?8 E) l; E& H6 P
1044029 PSPICE ENCRYPTION Encrypted lib not working for attached8 F, O9 R, ~. t3 i$ q. E
1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory! D) {( D) U; g
1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
. y6 |6 P- x- ?1 P1044577 GRE CORE Plan > Topological either crashes or hangs GRE ?0 w7 C/ D7 n) U7 Q: X
1044687 TDA CORE tda does not get launched if java is not installed5 O( L5 }$ I5 P/ ^8 d: Q; k
1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die
4 k* w, b1 I. k% o2 v. u- ?1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.
* g2 N8 y# c! k) n( {" ^1 q1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?
! K" f3 n4 S2 G- K/ ~9 P1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.0 J- M/ u1 Q! [& k U* V
1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry., o0 C0 z, {# U/ F5 X
1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow
& y( H1 j' G: c- e( S( u3 q$ y1 U1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.+ T" ?: o2 ?' B+ ^0 e& G
1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill! ^! w6 p# K/ ^
1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.
4 l3 F2 ] `+ ~; G1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5
$ R9 W8 ?3 k7 g# r) H7 e1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.51 O! h4 b0 q, O1 y! h- w+ X
1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value
7 D8 @) F& u; O2 P' R- d3 w1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version6 Q: N! y7 c, r7 o2 e
1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn縯.% r: ?3 L1 J+ p0 [# b4 A0 c
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.: T, H5 q- Q- k4 t N' ~; s
1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.' N) K* B4 |& e/ L
1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes# ^8 W9 a, l, i4 \$ ]1 t2 N+ |- O, @
1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
7 j% h/ D' a7 d( `: ~& |# I1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3
+ B0 A3 v; ]3 [/ T) M1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file9 a3 g3 X& b* ^% k& N# J5 E) T8 Q* p
1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors
0 K6 b. v0 C+ e7 B* r9 j" [2 W1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.
+ @% h8 G- @7 \. }) C1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.1 T/ }, N# t+ p, C, N
1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design7 @2 y7 Y& D2 k) U. R2 C! r+ |
1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs
6 i3 a( X0 Z# n: H: K/ \1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label
' x9 Z2 G- B9 k. R1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.
: I1 F$ M4 @! k3 B+ m9 U1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy. u! s K- o3 F! r5 J
1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down
) i: u1 M2 x3 R/ Q( C" n+ t1 K1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection B+ B4 W A3 A5 X) J
1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.6 L2 F) _' H" q" [1 v: z* F
1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views ?: \6 P) Q0 r: c1 L' P' C: D
1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline# t& {, d7 S, `" h
1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.
2 v$ ]: A# `: I$ S( s" @7 Y$ L1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created.
( A$ T# ~0 d& u7 q. J1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move
4 m! @ q& E- J' w1 ~1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value
( U+ v: k& W3 n: m1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer8 s0 P+ N. q6 D8 h
1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report
; t) k) X4 Z& n2 C: Z- I' @5 a2 p1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.# I8 A) G6 D2 ~5 z
1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete% O! [6 E+ E4 e6 B, v; x3 X
1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
/ r5 Y# L X3 R1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets8 v% q/ [$ |+ F% b' T% u! k5 ?
1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?6 f; ~1 r$ m) }8 p8 g0 }
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.
; N! J* `' G8 f" ^$ j/ {1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished.1 O1 [# u5 L/ s9 X$ O
1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00! b6 W/ o7 e* p2 Q* y+ R# A
1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation- }+ e7 \0 G: Q/ x& T
1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed./ w1 X. u4 C8 [9 a8 v8 L% p
1063284 PCB_LIBRARIAN OTHER PDV Save As is broken( U( ]0 L1 m1 ?0 w0 L* |5 {
1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs
3 A# z" ^2 B. K. g1 u1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.
& x$ r2 c7 ]; X1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.; C& R0 w4 J6 j" P6 d- {# U8 S
1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design# e0 T# u& c$ y6 p' y" d
1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV4 p0 v8 X8 K& X9 v/ X3 U8 B. L
1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green.+ V) z; k7 S, P5 L
1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X+ i5 n2 W5 W! ^2 I0 d: z5 ~
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application
. b- L2 h1 D; V( N# P2 Y1 T1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report
5 s( T4 ]$ e9 D9 ^# }* H1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
' l) B! B9 Y. Z. c1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic
; P: ^" ?' c4 U* [9 A Q9 y) j. d1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.! Z* i6 n* d* l" h/ O* R% Z
1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file
8 s/ E3 i6 [3 s) {4 r( R0 B5 r1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command/ `! y7 Y+ M4 m! m3 e3 ?8 J
1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended8 K4 g0 e" H3 C
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067
\. \ C. b: e( S1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design
2 ]- q1 m1 V5 r5 v& s1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify7 j" {- U- `8 ?" C! i
1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids1 V G+ w \3 N0 p& L
1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes% R) {. G6 v+ t) r3 }
1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow# e! K( s3 }8 \% `# B3 e$ |) f- R
1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal4 O. Y# d m0 R! D: B) e
1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.
7 A7 Z/ ^* u8 P2 N" y8 M1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6* \0 R0 I% _+ W1 q
1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5
4 H4 F4 Z( \; z5 x9 D1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode.0 c/ o; f3 m% C
1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.: X9 F& O' _, I, X9 z- n2 @
1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor
1 R& o1 i" [# j& l+ f6 D1073464 SCM SCHGEN Schgen never completes.
7 e2 E- n9 x/ V; S4 s1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory# i& c2 n( u# Y. u( z+ i
1073745 CONCEPT_HDL CORE Import design fails
9 j, Z- ^$ J, N9 }: B4 {" Y2 b1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin', Z T6 T4 A; M2 U; O
1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE8 A3 g5 n9 R) N( s% e
1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist/ J d6 s$ g# V( x5 m
1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter% W! _/ X& d3 n1 }, K. L
1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal/ s6 k7 m/ ?0 E; t! t
1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.
/ W' s2 w& S$ _9 V7 \- _4 k* X1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI, F0 b0 R( f+ ?8 @; L
1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block
" Y0 t; ] t8 [. j1 @1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer
& Y* Z+ Q2 U1 c0 e2 Z) p8 b) f1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces( v! D4 E% Y# G3 m
1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2& O0 u- U$ ^" l% M
1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix
5 t3 M. u" k& R/ u) }# r1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
. `2 { U! w4 o7 D/ ~4 B1 C# u1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top" v }! B3 d7 n2 G- Z4 s
1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas.- U& ^; c3 h- Z& ^ G; W0 [ x B
1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value# o7 H0 r; s! m* _, U" s& |
1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.69 r* W+ l- N6 W' @+ G, Y
1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey! r+ Q: e" O+ }/ C/ a1 c
1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database% z( E0 ^: \5 i& U& H
1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset! R2 T. t9 K% D3 Z) \/ B
1077169 APD SHAPE Shape > Check is producing bogus results.
3 O6 m" \ ?" y' W1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board.
w! l0 \/ ~7 D, G1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim2 L0 d9 i: M$ H, i4 }
1078380 SCM OTHER Custom template works in Windows but not Linux
) s* k- |. [$ G- ?1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.
# I6 }7 \8 n# ?1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide
: H4 R6 @5 D: j8 D0 Y7 }. y1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
& O& Z0 m7 J6 Y1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match". y; l1 [; w" N+ `" W& O
1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text) y1 i6 b1 k; @ f: s; z
1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control- ?) j7 C8 O4 W& M5 ~0 M
1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical.
6 ]5 w& U( c" t- u2 n1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release./ K% c2 S7 L; E5 r
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发表于 2014-7-31 09:06
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