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DATE: 07-25-2014 HOTFIX VERSION: 032' i- o+ n l/ p, i" x4 s* Z. ]
===================================================================================================================================$ @4 X6 t+ Y p: y4 M
CCRID PRODUCT PRODUCTLEVEL2 TITLE
+ D9 {* d$ X; g6 _* S, D% C===================================================================================================================================, s) D5 u3 I+ B3 f# I8 U
381127 SPECCTRA CROSSTALK Specctra xtalk reports aren't correct
$ T% O; `+ t# p7 i6 y- @' `& [616770 allegro_EDITOR COLOR Remove the APPLY button in the Color Dialog window.1 K; r/ g1 {% Z' f! z' C
982944 ALLEGRO_EDITOR COLOR seperate the Etch to the Shape and the the Cline in the visibility window
C3 |2 Y; u: Y8 \" S1 y982995 ALLEGRO_EDITOR INTERACTIV Shown infomation for the selected physical symbols
* _2 W! m9 [+ f# u: |% {0 U: e& J1024832 Pspice PROBE Shows wrong data & header when exporting trace to .txt3 {% t$ j6 C" P) R
1063258 PSPICE AA_OPT curve fit fails with error same data works in 16.5 Simulation error: out of range of data2 B( d1 M$ |0 q% q9 w" n: s
1112360 PSPICE AA_OPT Advacne analysis gives runtime error while using Optimizer in attached design
6 H; d, s' ^4 W/ F5 r+ d1154323 PCB_LIBRARIAN VERIFICATION Con2con is choosing incorrect Primitive from Chips file and failing FTB Checks
# H' T4 {% c; F1184690 concept_HDL CORE Weird behavior of genview for split hierarchical blocks
' p( V8 A4 s- Z* y! L; E" ?1212577 PSPICE MODELEDITOR IBIS translation fails without any information in log file: v. y3 H0 @) d; Y0 J; u6 p! q3 k- H. s
1213204 ALLEGRO_EDITOR PLACEMENT Place Manually with existing fixed net behaving incorrectly V6 x3 G+ E" f/ ]
1213837 ALLEGRO_EDITOR INTERACTIV When copying a stacked via the temp highlight does not display on the last layer of the stack.! P, Z/ [& L- x6 S
1216519 SPECCTRA ROUTE Autorouter will not add BB via between uvia within the BGA area
; _7 |4 q6 f W7 E1220655 PSPICE DEHDL_NETLISTER Support for automatic addition for Power source and Ground Node for Globals in DEHDL PSpice netlisting
( {' Y' Z+ v$ E3 X3 Z1223018 CAPTURE OTHER Diff pair Auto Setup not working for the buses.
5 J4 ~1 h5 G! Y, W1225689 PSPICE AA_SMOKE Smoke analysis crashes with attached testcase
7 A$ |3 v% M: ?& D1232124 CONCEPT_HDL COMP_BROWSER unable to generate ppt_options.dat file in first go
O' ]- V( a; t6 j; r3 [+ w/ b1235059 PCB_LIBRARIAN IMPORT_CSV pin_delays not being imported into PDV- F, v4 x; v* D. o, @) `7 H6 J
1238815 CAPTURE OTHER Capture doesn?t retain more than 191 library in add part/capture.ini under part selector configured libraries
/ b. y- I0 Z" S1 _2 N1239241 ALLEGRO_EDITOR INTERACTIV Via replacement doesn't replace with correct via but right padstack name.
. U5 P5 y$ h; l2 g. N* r2 a1240201 ALLEGRO_EDITOR EDIT_ETCH RPD DRC unresolved evenif HUD turns Green5 _* ]" n. X J" h. Z6 ]
1240314 PSPICE SIMULATOR Getting internal error,oveRFlow for the second run
/ A# u' a- e3 V% F, @# }2 R/ h1242805 ALLEGRO_EDITOR DRC_CONSTR no_drc_progress_meter variable hangs allegro after running update drc3 u ~$ a z% n8 |) [4 [3 j& j$ B
1243267 ADW TDA URL to TDO-SharePoint should be defined in CPM File
3 m6 v: G" C3 E1244857 ADW TDA Policy File Variables not working correctly in policy file
6 ^) Q; o/ f( o: j1245779 CONCEPT_HDL CONSTRAINT_MGR Obsolete objects in DEHDL CM
- z, K9 h, O/ e$ M% [: `7 q! B6 b1246811 CIS EXPLORER Option to keep the part type tree in CIS explorer expanded on every invoke0 J1 X! X$ ?; F. B2 H7 |9 W
1246964 PSPICE PROBE Simulation Crashes in 16.6 but running successfully in 16.5
~. _: ]; m( C7 \4 c3 G1248782 CONCEPT_HDL CORE Display winning physical bus names (occurrence mode) in the the lower block of an Hierarchical design! f0 Y+ E) S5 Y
1249238 CONCEPT_HDL CORE Uprev from 16.3 splatters text around sch page0 ?5 P. H' _+ _2 R/ K
1249692 ALLEGRO_EDITOR GRAPHICS 3D Viewer is wrong when resizing its window.
. w' g3 A% r5 B1 o$ J- T3 \: w9 [' G9 ?1249850 ALLEGRO_EDITOR SHAPE With shape_rki_autoclip Route Keepin to Shape DRC is created6 T$ Y/ ^% v& I- x/ d
1250683 ALLEGRO_EDITOR INTERACTIV devpath corrupts if edited from user preferences.9 t; Q0 u6 E& o7 S. T
1252059 ALLEGRO_EDITOR INTERACTIV Preference Editor is unable to delete a previous path entry for library paths
) U: m1 ?* p& w1253563 SIP_LAYOUT DEGASSING Not getting degassing voids when close to shape in center of design
# Q$ v6 X% I* O, x/ A' m1 }- L1254319 ALLEGRO_EDITOR GRAPHICS ENH: Functionality to change the 3D Model color for more realistic view3 v- B/ ^7 P- s/ Q# k" J* X
1254562 ALLEGRO_EDITOR DATABASE Unable to delete a subclass that exist only on classes Package Keepout, Package Keepin and Route Keepin. m( ^; D* g3 w2 V% g1 L1 E& S% K) M
1255169 CONCEPT_HDL OTHER ADW (BPc) Packager should report the specific corrupt directive in the .cpm file
, n/ V4 B8 [/ i+ U2 b& \4 M1255573 ALLEGRO_EDITOR DRC_CONSTR Need soldermask DRC checks when same net via and smd pad overlaps
; U( a8 S/ L( v( S1257950 CONSTRAINT_MGR SCHEM_FTB Changing xnet name on Allegro CM.0 b0 I" H$ p: J
1258165 F2B DESIGNVARI changing visibility of Probe_number in variant schematic changes it to $Porbe_number H i) H. O5 i5 }& k. D
1258274 PCB_LIBRARIAN VERIFICATION con2con crash with no notification or error message
9 u. C" Y5 b& F- x8 {% [* ]7 k) T1258860 CAPTURE PROJECT_MANAGER Bug: Text Editor (File> New> VHDL File) filters characters from Text; j) Z8 s- V$ `4 t8 W) Y
1258872 CONCEPT_HDL CORE Objects are copied (instead of moved) when moved from sheet to sheet2 D D" q9 ^$ i$ l! J/ k
1259284 CONCEPT_HDL PDF HDL_POWER ( global) net does not get transferred to the published pdf; `' Q5 h( I; j; f% H
1259375 CONCEPT_HDL CORE Help link to cdnUsers.org needs to be changed1 v6 S2 i/ J4 n$ Z
1259860 ALLEGRO_EDITOR INTERACTIV Edit > Mirror does not display asymmetrical pad correctly when the footprint is attached to cursor.
; ^6 E r+ @6 Q% Z3 z1 y) c1260002 ALLEGRO_EDITOR INTERACTIV Alt sym hard is not obeyed when using Edit > Move > Mirror
: J4 O7 d" y! w1260006 ALLEGRO_EDITOR PLACEMENT funckey r iange 90 rotation issue
, k5 O) y6 G) j n1260667 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes when running AICC command on few Diff Pair traces.
7 K1 i6 q$ F+ S8 N1260763 CONCEPT_HDL CORE Export Physical fails with $TEMP entry in Setup-Tools
( I( T& g( h- h$ T1260847 SIP_LAYOUT SYMB_EDIT_APPMOD Border texts seen as triangles.
+ C+ j7 B9 Z6 E2 D. q1260948 ALLEGRO_EDITOR SHAPE Dynamic ground shape is shorting to via of a different net at layer 4 & 5 in this design
2 Z$ n8 j0 k7 d( X! Q5 e1262011 ALLEGRO_EDITOR PLACEMENT Key Properties on Component Instance/ Definition on available to use with Quickplace by Property
" X3 B, G9 q$ q4 ?# V7 L4 a, e1262322 ALLEGRO_EDITOR PADS_IN Pads_in can not translate route keepout which specified for the all layers.1 X) c3 b. `$ x1 Z% R, c
1262626 CONCEPT_HDL CORE PROBE NUMBER attributes lost from the nets after upreving the design
/ A; X2 A7 r# O- _- V2 j3 Y* e6 h1263592 PCB_LIBRARIAN VERIFICATION Unable to check in Schematic Model due to pc.db file
& N. T+ y0 q: ]+ `# X$ K' G" ~1263685 ALLEGRO_EDITOR INTERACTIV Editing Photo Width value from non zero to zero allegro gives warning- Value must be greater or greater to zero2 X/ @7 l7 ^9 i. i V. G
1263704 ALLEGRO_EDITOR EDIT_ETCH Bug - AiTR wrongly deletes blind vias and do reroutes.
% W- A6 U3 O" e1265120 ALLEGRO_EDITOR SHAPE Require voids in dynamic shapes to use pad value7 f$ A) d7 `1 p4 l" T' K' n3 H
1265275 ALLEGRO_EDITOR DRC_TIMING_CHK When XNETS are dissolved by removing the Models all Physical and Spacing NetClass associations are lost
0 a) i9 z5 J6 |) _" l1265633 PSPICE SIMULATOR Bias point result is different in consecutive simulation run of the attached project
% U- B$ f% g5 ^+ a/ Z1266349 ALLEGRO_EDITOR PLACEMENT Rotating symbol while placement show wrong angle of rotation than the placed angle when Angle is set in Design Parameter: |# e+ ~0 O" d* d# ~: J
1267541 PSPICE PROBE pspice.exe does not exit when run from command line
( V" {5 x+ c% G1 _1267707 ALLEGRO_EDITOR PLACEMENT Mirror Command - preselect/postselect bug with general edit mode
+ Q& v0 v5 ]. w8 }1268299 PSPICE STABILITY Pspice crash on attached design
& _2 b" M9 _2 n: {1270879 ALLEGRO_EDITOR COLOR Color view save creates .color file using older extension* x6 w1 g6 n! b$ s- ?" Y0 C
1271295 SIP_LAYOUT DIE_STACK_EDITOR Die stack editor support needed for large variant combination designs.
! z/ @: V+ f! K( C9 G) ?4 S1271385 CONCEPT_HDL CORE Locked property can still be added
6 A7 h$ f/ j4 v1 Q- i( z; S1271853 APD OTHER When using the beta "shape to cline" command, add improved messages and partial completion of individual segs in error." q# {' v6 ] Z B% j
1272197 CONCEPT_HDL CORE concepthdl_menu.txt contains invalid Variants menu) Y4 z' G7 o, g1 i5 ~* t
1272318 CAPTURE GEN_BOM BOM_IGNORE not working for Capture BOM on hierarchical designs.3 s2 o- ?9 K B2 x5 `
1272743 ALLEGRO_EDITOR PADS_IN PADS Library Translator does not open the Options dialog window.
: w8 T) K' H0 r0 P# R. l/ O. m1273517 F2B PACKAGERXL Netrev error - ERROR(40) Object not found in database6 [+ P6 Y/ ^ Y
1274000 ALLEGRO_EDITOR DATABASE PCB layer can't be removed& B$ R4 g8 {: @# i: h3 P! z
1274530 ALLEGRO_EDITOR INTERACTIV Add Circle radius value changes next time using this command
3 t, Q& |9 }! I0 }7 p* m1274697 PSPICE AA_MC pspiceaa crashes when running Advanced analysis monte carlo for the attached design5 K7 i J* \4 O0 X0 {# W8 x
1275154 CONCEPT_HDL CORE Hierarchical Blocks lose ref designators when moved to another page
2 i$ T$ t) }: C, {; q; l1275724 GRE CORE AiDT delete another clines
: Z' X- S" Q- l& ~6 b) W0 o1275831 ALLEGRO_EDITOR DRC_CONSTR Waived DRCs return when using multi-thread DRC check
' g' I8 `. h$ M. N1275834 CONCEPT_HDL CORE ERROR (SPCOCD-569) on global bus+ C! ~# s, N" `5 [
1276334 ALLEGRO_EDITOR PADS_IN PADS Library Import problem with outlines
! K5 Y# h. \# P ` {1277062 ALLEGRO_EDITOR PLACEMENT Swapping parts from top to bottom Orientation changes
: S# q2 F! B9 W/ |2 e, G% G% D0 l' b1278746 ALLEGRO_EDITOR DRC_CONSTR Package to package DRC allows place_bound_top in 0 spacing has drc in 16.6 version.
/ Y8 T' }5 w# b! r" c1 w4 V0 r1 o1278804 CONCEPT_HDL COPY_PROJECT Copy project crashes
( |( Z1 r3 Z' H+ z& ^5 F1279362 ALLEGRO_EDITOR INTERACTIV User skill file makes Allegro Icons gone away$ M+ \/ b- K: X) y0 j, ~9 U( v
1279619 ALLEGRO_EDITOR DRC_CONSTR Netgroup in a Netclass doesn't inherit Spacing Cset0 r3 J! D# ` G3 K" g" h5 V Z4 d
1279815 CONCEPT_HDL CORE Text > Change and RMB Editor does not allow multiple text edits
% k$ y: n6 w* `6 |: u" j0 \1279876 ALLEGRO_EDITOR DATABASE Using the Curved option in Fillets results in a pad to shape DRC2 \" t! `9 C% P- ^9 p
1280435 F2B BOM BOMHDL with variant repeats the PART_NUMBER value& a: b0 }, ~/ y
1281669 CONCEPT_HDL COMP_BROWSER Match Any radio button in Component Browser didn't work.
) h" ?' S; g, j1282001 ALLEGRO_EDITOR DRC_CONSTR Updating the DRCs on this design cause the DRC count to change on every update
4 |, I1 i# {0 o9 k7 h1282480 SIP_LAYOUT WIREBOND Info on the Wire Count property needs to be updated indicating that it is a User Defined Property5 B( g- |% {* R7 m K5 u9 m* O
1283952 ALLEGRO_EDITOR PLOTTING Published pdf does not show dotted or phantom lines8 E4 h6 T! y# U1 c H2 r
1283957 ALLEGRO_EDITOR INTERACTIV Replace padstack in "Single Via Replace Mode" is changing netname of the vias with the latest hotfix of Allegro 16.6" G& P7 j0 \# r
1285588 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase control has wrong analysis result when add rectangle test bead in Clines.3 ]* ~& Y( n* f# N& E2 o, E9 W
1286743 ALLEGRO_EDITOR SHAPE Getting copper islands in the design after running the Delete Plating Bar command
0 @( O8 N4 A, u& B1287215 ALLEGRO_VIEWER OTHER Allegro viewer plus does not support constraint regions
$ R" g: `& z1 G1288808 APD LOGIC Derive Assignment stalls out or won?t finish and appears to run out of database room.
, j8 a- n9 p" _1289251 ALLEGRO_EDITOR SCHEM_FTB Pin escapes (clines and vias) not inheriting new net name from a pin with a new net name.
9 \5 x8 F" \, E% J3 |1289293 F2B DESIGNVARI Warning 04: Cannot merge the variant properties on variant instance C119 component with same canonical path not present
* E' y0 a1 q' i# ]- ]9 x- r1289809 SCM VERILOG_IMPORT User not able to import a verilog netlist into SCM
2 a' r5 f g4 \9 s1 q- A1290696 CONCEPT_HDL CORE Copying a net name repeatedly causes it to go off grid" b7 [' X' |; t. e
1291162 CONCEPT_HDL CREFER crefer crashes when selecting generate cross refernece for all nets selected8 Y3 f* @- m( n. U$ @5 ^/ v
1291285 SIP_LAYOUT IMPORT_DATA Replacing a Die with the Die Text in Wizard causes some Clines to Shift, creating new DRCs.
/ U) i7 X6 x U( S! B% p/ |& ?1291658 ALLEGRO_EDITOR INTERACTIV Cannot add Frectangle to Group
: h4 H. U- r3 ] ~; Q5 J5 A1292180 ALLEGRO_EDITOR SKILL Allegro Crash while performing query contents of "Maximum_Cavity_Size" with the skill command 'axlDBGetPropDictEntry'
% L! j2 G: i0 M, @1292210 CONCEPT_HDL CORE DEHDL crash if design was opened with -nonetlistuprev option.% q1 ^9 ]2 j6 d9 H5 I. L
1292278 SIP_LAYOUT WIREBOND When creating Wirebonds by Importing a Wirebond File, (wbt) the wirebonds are not on the correct Die layer" Z/ G! H5 W" d+ T! u$ `
1292282 SIP_LAYOUT INTERACTIVE Getting Multiple GUIs when the Wirebond Import is open and we select outside the command GUI.
/ j7 I S" ^$ k$ N0 w1293381 SIP_LAYOUT IMPORT_DATA Import SPD2 error6 M1 i3 c# r0 @3 D
1293889 CONCEPT_HDL PAGE_MGMT page name regression result deleted by netassembler
, R. a6 E) Z( ~* h7 K9 P1294124 ALLEGRO_EDITOR INTERACTIV Samsung Mobile division wants to disappear the grids in the display window when zoom-out function executes in the allegr" K7 }7 X' i. f1 l
1294749 ALLEGRO_EDITOR ARTWORK Null pad is flagged as an error that break Thales automatic tape out
4 g, I/ s, ]9 T6 ~! `) c1294777 ALLEGRO_EDITOR SYMBOL Mechanical symbols missed on STEP result
5 _' H# m$ o2 y }
; ]5 x9 v! ]9 u$ |DATE: 06-20-2014 HOTFIX VERSION: 031
4 D, c/ e P: O) |; K===================================================================================================================================3 j, x/ K. d) x% u
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 P- y0 K4 [: O4 W- m; K% M===================================================================================================================================. G4 B) ~# J0 E" N1 c
726553 FSP CAPTURE_SCHEMATI Method to select bus bit?s order while generating Capture design from FSP.
4 e8 X9 r- F8 f. ^' `# K/ N" r( i1257631 FSP DE-HDL_SCHEMATIC Schematic Generation selects incorrect symbol version7 G3 Y. ]9 |4 I2 Q7 ?! a! _9 P% N
1273456 ALLEGRO_EDITOR PLACEMENT Place module instance causes Allegro to crash
- f- F* T5 k$ u r* } m1277099 ALLEGRO_EDITOR INTERACTIV Clines and pins are disconnected even though they are at the same x, y coordinate.3 b0 Q0 B- ]) f
1280913 ALLEGRO_EDITOR EDIT_ETCH Add Connect should be able to be made by go straight even though the cursor is not exist on straight line
- @4 N/ t! h% B9 `8 x1282491 ADW PURGE ADW PURGE is removing Page Name data in DEHDL
& Q! I0 Z( T( w0 `* R/ X1283045 ALLEGRO_EDITOR DATABASE Ecset not getting downreved.$ I4 O7 F F5 m3 C# `# s0 S
1283138 SIP_LAYOUT IC_IO_EDITING symed app mode chooses wrong text block sizes for I/O driver inst names
2 v* C8 s" y* g3 [% {2 \6 z1283227 PDN_ANALYSIS PCB_STATICIRDROP Enhancement request to add 32 bit files for IRdrop
0 l6 w! |) U9 |# L6 ?1284656 CONCEPT_HDL CREFER Crefer fails on large design
; G. v) }- _# v: d4 f0 J/ ?1285814 CONCEPT_HDL CORE DEHDL crash on opening the Design
o$ W5 q0 j( U1285967 ALLEGRO_EDITOR EDIT_ETCH Slide via in circle pad" W! ~( }2 r2 n$ K7 x* h8 {' m
4 h- g$ |; S- O3 ^% RDATE: 06-12-2014 HOTFIX VERSION: 030" n: [0 R# f/ w
===================================================================================================================================1 s9 C6 i6 _* z- u6 x* D% F
CCRID PRODUCT PRODUCTLEVEL2 TITLE
0 S; I M1 \6 r===================================================================================================================================: b X$ H9 r7 ?
982961 ALLEGRO_EDITOR PLACEMENT Show the Rats when one selects physical symbols to place them
* N0 o9 x1 }. ]! M1138680 FSP POWER_MAPPING Ability to assign decoupling capacitors in spreadsheet like application
. _7 W1 C! Z" l; Y1 n1243410 SIG_EXPLORER EXTRACTTOP Circuit topology extract failed in case of CLASS
1 v8 [$ e# N7 D9 x1262977 ALLEGRO_EDITOR TECHFILE When importing a certain tech file into an empty .brd Allegro crashes.
/ k( ?$ c. H, Q3 x" a, l6 t( R8 b# k1267558 ALLEGRO_EDITOR INTERFACES Arc part of symbol pin missing in 3D view of step model
3 M7 N6 o& z2 h3 U& N1268252 ALLEGRO_EDITOR GRAPHICS step place bound issue(3D View)+ B* R9 o2 P/ `
1270450 ALLEGRO_EDITOR INTERACTIV footprint add line on line crash8 y* j& E7 w1 x
1270962 CONCEPT_HDL PDF PDF Publisher command line does not print pdf file if double back slash is present
8 h: l+ O% w2 v9 y: P1270964 ALLEGRO_EDITOR mentor Mentor translation crashes with no errors in log file9 J( o7 z4 Q; W8 \
1270999 MODEL_INTEGRIT TRANSLATION ibis2signoise Issue, A* a1 S8 y# z: b$ D2 I* V: J9 e
1271543 ALLEGRO_EDITOR PAD_EDITOR Library import reporting missing padstacks
9 \% P/ j3 D9 r* j! K% I6 j1 e( \ {1272099 ALLEGRO_EDITOR GRAPHICS Plotting does not fill shapes
! h: T" M% n5 N. D8 ^1272406 ALLEGRO_EDITOR DRC_TIMING_CHK SKILL command 'axlDBTextBlockFindName' returns 1 when nil is expected# e/ ^# h4 X, Z! F- R
1272748 ALLEGRO_EDITOR GRAPHICS 3D viewer crashes on this specific testcase
# q7 L; K1 j4 {1272793 ALLEGRO_EDITOR GRAPHICS 3D view doesnot displays hole with offset correctly
2 R" J) H) X- U8 s5 Z- X1272863 ALLEGRO_EDITOR INTERFACES Ability to find the origin of STEP File in order to place it exactly where it needs to be on footprint during mapping.8 j" D3 P/ B0 a7 S- c$ k# V
1273264 ADW COMPONENT_BROWSE hyperlinks not recognized in the component browser& j: |# p0 B# B
1273304 CONCEPT_HDL PDF Publish PDF from commandline does not work if there are spaces in the Path$ h5 s5 d- P' {3 @; B
1274661 CONCEPT_HDL CORE I can't copy a property from one component to another" ?' \+ R! s [8 Q- T& D
1275237 ALLEGRO_EDITOR DATABASE Allegro Crash on running DBDOCTOR for a board
, @1 I- |/ H% P, w# z, k1275345 CONCEPT_HDL CREFER The Xref information page number values are incorrect) N7 o7 z& l% A" f* J6 U/ |1 v
1275748 APD IMPORT_DATA WireBond starts away from the Die Pin after importing Die using Die Text In Wizard: v$ V8 b7 o( `( U; \5 h( d, \7 f
1276270 CONCEPT_HDL CORE DEHDL crash by Zoom In > Ctrl+A > Move
1 B5 }& J* b% `7 y* r1277735 SIP_LAYOUT IMPORT_DATA sip layout spd2 translator issues with offset die and mirroring
( d4 Q+ b: ~7 ~" d+ I- H1279258 CONSTRAINT_MGR OTHER Import logic stops with error. D" a e3 h: k7 X+ C T% a3 e7 k
1279694 ALLEGRO_EDITOR SKILL axlCNSSpacingMin('via nil) crashes Allegro PCB Editor
, Z: W$ I# [3 c1 |& z. Y2 y, p- T2 ^) X j! I5 V
DATE: 05-23-2014 HOTFIX VERSION: 029
4 P3 \- C& t2 k! `4 Z* `$ K. F+ V===================================================================================================================================, v. p& f1 j2 A! f; v
CCRID PRODUCT PRODUCTLEVEL2 TITLE A; ~0 p; e- @! o) V5 l
===================================================================================================================================
# O; J' f; n$ f1209461 FSP DE-HDL_SCHEMATIC Hierarchical Block Size not automatically adjusting to text needs
; p d; ?8 I/ m2 |& Y0 C$ R. S5 H1217832 SIG_EXPLORER SIMULATION S-param generated by SigXP doesn't match with HSPICE/ADS.
( r. G! F) d5 Y" b3 b& \; [1263575 CONCEPT_HDL CORE Copy-Pate makes Components Off-Grid+ n" ] ?$ k$ ]# H( a
1267602 SPIF OTHER Route Automatic hangs
. e9 j; b" n8 r" k1268022 FSP PROCESS FSP is not respecting the use banks for attached design.
4 [5 v1 j3 ^, p1 m" X) N1268587 ALLEGRO_EDITOR INTERFACES Enh. Preserve relation between hole and padstack in IPC-2581# W# k8 N& W$ g: F5 {
1268918 SIP_LAYOUT DIE_ABSTRACT_IF SiP - DIE export from co-design object to XDA results in missing data- V3 ^9 S2 R4 K( w) M6 r
1269232 CONCEPT_HDL INFRA While pspice uprev the design crashes5 @% n K: S R% C* B7 F. I
1269825 SIG_INTEGRITY SIGNOISE PCB SI hangs when running crosstalk simulations
- [' L6 O/ T% r) k5 Z# m$ t: V* V4 F1270963 ALLEGRO_EDITOR GRAPHICS Add Circle lint font hidden/Phantom has resolution problem
, b: x* _. X; a; a1 l/ J" Y1270990 ALLEGRO_EDITOR GRAPHICS Allegro response is slow when added circle2 N Q6 W! R* m! M
1271655 ALLEGRO_EDITOR MANUFACT Dimension option causes a generic crash, reproducible in any design
4 A# ^8 \5 }+ ^ u% M8 o) ~1272495 ALLEGRO_EDITOR MANUFACT Filtered Part numbers in IPC-2581 still pass actual part number for references onutide of BOMItem
$ U9 m, l) Q5 L- ^+ c" Y1272839 ALLEGRO_EDITOR MANUFACT Kindly explain the drill legend behavior when padstack rotation is 45 degrees and mirrored ?
0 p, E" }& [9 u6 a: y+ x* {1274518 ALLEGRO_EDITOR ARTWORK Artwork does not create void correctly.. n/ T4 L5 }" H
* z! J e4 \( Z* j/ ^; o0 q w
DATE: 05-10-2014 HOTFIX VERSION: 028
' R; T& m1 p! v, X9 X===================================================================================================================================
# z* u0 h8 n" [- O iCCRID PRODUCT PRODUCTLEVEL2 TITLE
: v3 M T9 c8 E===================================================================================================================================
0 T; `: \0 Z8 n# Z1199256 ALLEGRO_EDITOR INTERACTIV DFA bubble does not appear when moving a symbol to within another symbols dfa bounds on specific symbols; S! V% Y. J% s0 }+ C
1220196 ALLEGRO_EDITOR OTHER create xsection chart results in ERROR(SPMHA1-73): Text line is outside of the extents.- m: O2 f; L9 @& l
1259520 ALLEGRO_EDITOR EDIT_ETCH Allegro will crash when adding connections to a differential pair.
( H N" n7 b. ]! j' B8 Q+ V1260446 ALLEGRO_EDITOR VALOR Creating odb output the xhatch shapes where arcs are will become inverted. Difference in the geoms.out extraction?4 D2 v: b9 k& Y5 X& o* M
1261313 ALLEGRO_EDITOR INTERFACES Step mapping does not show all Available Packages4 W: `# l1 y8 K" v! [- H
1261356 CONCEPT_HDL CREFER crefer is crashing with generate for all nets option
; c* m [7 R8 V+ j6 L) B. K, b1261514 ALLEGRO_EDITOR ARTWORK Exporting raster artwork with overlaping voids fails.
& t2 ^- C a5 S: {7 e, |+ l9 |1261735 ALLEGRO_EDITOR ARTWORK Presence of Smaller shapes inside bigger shapes is crashing artwork generation.
0 Z8 A0 v# \: B+ M1262019 ALLEGRO_EDITOR INTERFACES Artwork control form hangs if we close PDF publisher gui, F/ f) T- o8 P- F
1262246 CONSTRAINT_MGR ANALYSIS Constraint manager shows ALL PASS when Adding members to a NetClass and adding parallelism rule
: k' [" W6 v+ a6 v' ]! l1262560 APD WIREBOND bondwire can't connect to GND ring directly3 k+ G1 s. {. G- v
1263275 CONSTRAINT_MGR OTHER Import of constraint file hangs in this design
8 S: A# ^; A1 e- H, y( z9 K1263358 SIP_LAYOUT OTHER SiP Layout - Void adjacent Layer enhancement to merge voiding for PADS without changing shape params) P7 J8 B: x: e
1264109 ADW LRM LRM error - WARNING(SPDWREV-7): Unable to read the design! P/ R* |% v1 Y X
1265580 APD MANUFACTURING Icp_soldermask_allow_pins cannot create correct solder mask when the pin rotate.3 V, x5 o# ` h* C0 z8 a% K9 Z# P
1266391 APD LOGIC SPB16.6 Derive assignment : want to select 1 DRC marker only.2 f4 {1 d3 ?4 D& a
1266687 ALLEGRO_EDITOR SKILL The SKILL p8 ]' f) P: I( {2 {9 n8 _5 ~, u
1267267 SIP_LAYOUT WIZARDS Attempting to create a die using the die text in wizard but the tool is not creating the correct die outline
" _6 J& S' ^4 |8 b1267308 SIP_LAYOUT OTHER When updating a BGA with the Symbol Spreadsheet tool it will start, update a few pins then stop.9 S! \6 u9 C$ t( y0 ^- j6 `) T3 L( E
1267639 ALLEGRO_EDITOR PARTITION Allegro crashes when partition is created and opened from a location that contains "!" in its path.0 f ^5 N. R5 W
1267704 SIP_LAYOUT STREAM_IF Cannot import stream file, the tool starts scanning the file and never stops.4 \) N* d+ @) f. @2 C
1267907 CONCEPT_HDL CORE Ctrl+RMB Context Menu Option doesn't work.
! ?" m8 T' U$ R5 f Z( }# e! v$ C3 R, ?8 z5 p; ~, S3 V
DATE: 04-25-2014 HOTFIX VERSION: 027$ S$ w6 ]$ w. Z- L% G) S3 [2 _, l
===================================================================================================================================) {6 T9 s1 M. Q) }9 s
CCRID PRODUCT PRODUCTLEVEL2 TITLE. P, y! O! U3 f4 ?2 ^3 P1 [5 e
=================================================================================================================================== e$ b1 H* m6 J9 A$ {0 B
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM4 F% O9 \' q! U o* a5 [4 Y
481674 ALLEGRO_EDITOR PADS_IN No board file saved from PADS_in- v6 C5 F4 c; v7 q
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.3 l. o7 k5 ?5 ^- B
1012783 FSP OTHER Need Undo Command in FSP1 T# }4 L; p- [# y6 v% v& p
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.
5 [! L1 F+ s3 o' Z5 @* P1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved( Y" s& v; F7 [0 j3 U* ?
1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.1 A2 Y6 u$ b9 w. } z5 G9 l
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups) G9 h* V( H. {* {8 J8 ?& x
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash$ e% V/ h( T D: P) G+ s3 z" ?
1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command8 q1 x% A% _! b! n. O7 r0 [
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
% d9 F; Z% @- s4 p) N5 E1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present B/ e" R! \4 g+ U+ F; s
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
5 ^) E* T7 U& x( \0 C1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings
+ X7 k2 f0 a: z1 n7 k! O1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
% B5 e6 N2 u( N/ h9 b: N1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
2 e: y" y- N" V0 Y- t9 Y1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
/ F; m7 D! _$ Q2 O, A0 `7 |1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
' R; E& ?" s) W+ U' [6 C1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime
. f/ F w5 C: f6 e; z1208478 PSPICE PROBE Attached project gives overflow error with marching ON.
7 B4 u H+ @% W' z- G" H$ R/ U1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol
( h, ^" w& ~$ _" r6 y, P1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
8 t1 y3 n+ u8 q3 e/ |1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape" m* y0 P, P/ D# n
1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers
7 G% x* L O* K- `0 t7 p& y) H1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?
$ d+ p8 A; e7 o+ H8 f4 P1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.
% e$ [0 ~: z/ S! p/ H9 I: O, a1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values8 E& g1 Q6 ^$ ~1 |/ |
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging
' ]2 B( P+ A3 v1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information1 h" U/ L: `8 X9 s( s
1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added
4 s% n2 w, |* y& n1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.- V# C, r1 A3 [2 M$ o+ A; K# A
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
: {& h' S7 _6 @+ N( Z0 k% h1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux
; q2 U' g) [0 }- r! |1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
; @/ V3 B, V8 u( k1221182 ADW TDA Team Design with SAMBA# p% ~! E c7 R" m9 a5 j: g5 K' @/ ^
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
4 X; u) y3 Z" \) t9 `1 D* t1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
( A3 F" K g) i" d' x' ^ \1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?6 ~5 m( Q8 T0 f$ g& d
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts: m! f, j. }- r
1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms; j6 @3 N- X* {; A9 a& h6 V
1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.- d9 y1 S( L, S& [
1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor# x6 u3 Z2 ?, M0 y
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.
& J5 z) P% L+ p" Q1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
: A. n% p+ |/ {1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin6 ~2 U$ G: t G E! f
1225494 CAPTURE DRC Different DRC results for Entire design and selection
2 ]- o0 S6 x: ~- D! h1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property
# P, P# m9 J6 _' v/ M9 @4 T1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet' N. A8 O( f* A% [7 M2 Y1 k' ]
1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
" Y2 }- ~/ i+ D4 ^1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts� function is inconvenient for Global Signal9 \5 b) {$ ~* a# n! |
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file$ K _6 _0 y$ R; V4 h
1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
8 s3 [# g: Y$ M/ E6 M1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
3 L _+ V* u8 g/ ^0 J1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration- K1 _4 N4 W. b$ Y+ _8 e
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part1 I* k6 c1 A9 w
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case
# r+ J* }6 `7 ~; T: E/ h1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins+ M5 w* p6 x% y: l
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
2 P$ X* K. ?* T1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
( L/ h9 u$ \4 g- W( h; y7 m" g1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
& z% Z5 T, N* |- o. Z1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
! M% R- W, p' q; w! ^6 ~; Z3 h+ c1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM; z4 ?0 r, O! j8 m
1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
) q8 C: y+ P% M! Y+ I, `1230432 CONCEPT_HDL CORE No Description information in BOM I5 @1 P, ]; \' B# S
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
8 v9 z3 p0 U( l- p) t1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files4 o& u& g8 {0 F$ H4 `
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands+ |8 z! a6 P0 z
1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets
- d8 D0 t ~; d+ V+ N1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.; C! \9 h5 |: ~5 ^
1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode
. S0 h2 q) t' H+ J: g3 P# A1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical
: D& z2 R7 a# s! e; @( h/ b1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode! S1 y- R9 D6 s7 S
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files
8 w J6 t$ ~% F' P3 p: Q6 _* a1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy
# k9 j3 ~, y" E4 ^1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved2 U0 U) v3 S" [, w0 A* f
1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect
& g+ Q8 J: ~! e- l1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set) p' |* H1 W; N5 x% G6 _
1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic$ b' A0 Q4 H9 w3 V
1236161 CONCEPT_HDL CORE Import Design shows the current project pages
' P* h# N2 d( w6 J T2 r1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances., T0 f7 A/ a+ O, f/ q. ~" Q& V
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion9 E, L V3 ^5 d6 w7 l( e0 I8 W
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file' g- z2 j" F, w1 |' ^
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape( R! B3 D5 g9 h3 s1 e& A7 V. U, v
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming0 u5 o" @$ v: Z3 J
1236781 F2B PACKAGERXL Export Physical produces empty files
1 x$ `4 L4 V3 r6 Y1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
. b3 S4 U* q2 E0 F% R3 c& G1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib� command
3 `% Q, P2 [- ~' n; e1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
# ^: e0 n2 J9 N- Q$ P) u( b1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
9 T# ~6 x1 V8 x2 N4 O' P1238852 CAPTURE GENERAL signal list not updated for buses
$ Q0 C; H w" H+ H: K. z1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes
1 [0 A0 ^! m% }% ? [6 C3 |1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
+ Z) l7 K/ O# C# ]0 S. Q1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE7 m( z5 _$ P( m9 u% ]
1239763 PSPICE PROBE Cannot modify text label if right y axis is active; E! L: ^, w' G) x/ L0 a
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images# C$ P9 A0 P I1 |3 _; `: i
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
4 n( }7 m0 ?' T) v1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
3 t4 P7 m0 ^6 Q# ~1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file
?6 d8 T8 g: W* R1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable9 Z& F1 \1 M! \# {; D: R0 Z
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy
1 ^ M. e. x8 a6 j# m/ V. I1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms* E5 P: g) j$ r D; r* j
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working* f& t1 x( C' h" ^( L7 c
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.: v6 [3 m) \- G' a2 p, x
1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
" w: o1 W* R9 Y6 b+ @2 r1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
l4 c: o* L- N3 Q& D1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side
$ R9 K0 i$ Y+ Y% _1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer
0 r4 t) M. y& L6 J1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
3 [; i9 U: _+ S Z1243609 CONCEPT_HDL CORE autoprop for occurrence properties0 X+ E* j% r: C7 h2 I$ U8 p
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI! Q; \4 n% Z9 g$ A$ w
1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
& f* D7 ?0 j) `+ h7 T" g+ {1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring X5 c2 u/ y; j5 L
1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
% X; J. O- _) h- d8 K1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is _$ `& Z1 Q5 f5 _/ f
1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design/ [* b: Z! v) m% m9 a5 m
1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?
! ]. q+ u# x( Q) U1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
@; n7 h2 Y0 {9 @8 Q8 v( T1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters
- K! ~0 i' |1 `/ G+ t) u1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
: W4 Q' q3 J, W/ z5 M* _* J1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number8 V# A6 q& e. w9 f$ {4 @. v2 N
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
( Y4 L: ^! T: m* J1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained' w: W$ ~9 j1 c- k; \
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box5 O1 `! b# i; M
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered1 M: a7 t7 N0 [2 ^8 O/ D' k6 D
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components h6 g. ~7 Y+ M& C9 R& U- F. h
1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts
: `7 P, r, l [" C1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.$ O h, d, [3 R/ u' B
1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
) ^" v! |8 |7 U& [9 S( H2 T1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly0 v/ e, F7 X! s3 S( {# @. j
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
! n' o# r) `6 c, S9 Z1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies+ C( R2 D8 l; ~7 F8 D
1253424 SCM SCHGEN Export Schematics Crashes System Architect4 x: x# _- g0 R* S( t$ V
1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled
6 d# o( L# N9 B* Y* {' Y2 Y4 b1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
! p, V: j2 ~& P) b# L% _1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router6 g2 G% N& m( W0 o7 |
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error
# Y+ s( a% d. C3 K1 T1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
' M# O8 T) V$ o8 e; T" M1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation
: z/ V! b* X g( c1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects
+ ~+ ~, |# }5 n1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode: q: `7 s$ o3 O/ X* o. `
1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
3 ]# z6 a( x3 V- ]( w2 b2 e l1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
) c) F+ R7 N) F: ]9 d$ d& g1 b2 i4 Q1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
1 c/ Z" A) u/ S3 f% d1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design9 k5 m6 g" P4 ~+ H
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library/ U, n0 R% _2 D+ @# T
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
, d+ `1 K& V4 T+ J( N( g1 \1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash' S; d$ w/ L0 m0 _" _: }
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time3 \2 B" E( w, a$ k5 l, Y, s6 i
1258029 APD WIREBOND The bondwire lost after import the wire information
9 Z) t. W7 O H5 J6 F" F! t1258979 APD NC NC Drill: There is difference of number of drills.5 R. S$ l: B" m. Q4 L2 M
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement
" }: A- M% K7 x' g9 [, P8 r1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
' N) W2 Y, |/ b9 e1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"
4 }5 u3 `' j# Y7 a1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines
3 j9 e( E1 {9 y) G$ _, c1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void
& i3 f( R9 U% A7 B; x1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
! C6 X5 W2 U# R" j$ o8 I% m7 ?$ M- E8 A1 |6 I" |! c7 _
DATE: 03-28-2014 HOTFIX VERSION: 026
( @+ T5 M+ M9 l7 v! y4 i% g2 G===================================================================================================================================
% s' S: ]3 N* wCCRID PRODUCT PRODUCTLEVEL2 TITLE
! T5 S4 h& x) a7 q3 s===================================================================================================================================
9 e7 G i! n7 m" A% m1190942 CONCEPT_HDL CORE Cannot copy locked .xcon files
6 {, P3 E- L9 O4 @1226085 F2B PACKAGERXL Winning net NC shorted with loosing net due to PACK_SHORT
; k0 j$ E3 @( K$ i1244894 SCM SYSTEM_OBJECT Get packaging error when adding a pullup/pulldown resistor- R& ?5 R C* E# @/ B9 f
1247432 CONSTRAINT_MGR OTHER PCB Editor crash. G( m( K+ g, u/ |% f
1248560 F2B DESIGNVARI Variant Editor > Help about for S024 says unreleased ?
' i# F2 o6 \& a, U# d1248712 SIP_LAYOUT WIREBOND Changing the charecteristics of a Bond Finger causes it to shift position
" V5 d1 X4 f' }( ]% ]! Q1248839 ALLEGRO_EDITOR OTHER 16.6 S023/024 crashes on Logic Change Parts command.
5 U; v# }1 d/ q1249000 SIP_LAYOUT DIE_EDITOR unexpected shift of instances/pins by co-design die editor+ d( V9 p6 {. c- U0 u- x
1249186 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 ignores property UNUSED_PADS_IGNORE, j' F }; v0 I% \$ b
1249272 SIP_LAYOUT IMPORT_DATA film resistor pins/pads are created on the wrong layer. Always synthesized on top cond layer regardless of config file# A4 E9 I7 P& [3 O6 T x) P
1249792 ALLEGRO_EDITOR INTERACTIV Cannot place rectangular shape as per included width and height.
2 L9 @8 I, F6 c! m" v1 j5 s1249801 ALLEGRO_EDITOR INTERFACES Bug - Arcs in IPC2581 export are corrupted2 A. E0 [0 A; u& L7 V& G
1251006 ALLEGRO_EDITOR INTERFACES IDX does not recognize PKG_PIN_ONE property1 P7 w$ b3 t ]* z
1252142 ALLEGRO_EDITOR INTERFACES Remove inappropriate Conductivity specs from the dielectric layers from the IPC-2581 output t; N4 ^: P! K' [5 E; u
1253047 ALLEGRO_EDITOR SCRIPTS Bug: SAV file when creating symbol
' m1 t: | O: S$ Q l; ^0 |7 m( o; _- l2 Z( p( f5 M! d; h8 G- D
DATE: 03-13-2014 HOTFIX VERSION: 025
) h* G) m2 Y, g" ~ V9 |; q- @===================================================================================================================================+ A" ?2 A8 M5 D* Q6 s2 c: t
CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ o0 S. q! o T0 W, x; [===================================================================================================================================: P, z }' y- D& S
1194646 CONCEPT_HDL GLOBALCHANGE Global Update > Global Component Change does not work D9 G. a: A& a8 `, X+ m. Z
1227843 SIG_EXPLORER EXTRACTTOP Cannot extract the topology correctly.. `: _9 g2 K- S* }
1231510 ALLEGRO_EDITOR INTERFACES IDX exchanges with CREO 5.0 issues4 P0 @$ [2 G1 I3 b% f
1233030 SIG_INTEGRITY GEOMETRY_EXTRACT Net Parasitic of ground Connection" c) U; i$ H; q2 M! `% k9 ]
1236961 SIP_LAYOUT OTHER Moving component using Place Manual -H causes mirror_geometry.2 Z. [' {$ A! v0 Z) [! V0 {
1241456 ALLEGRO_EDITOR EDIT_ETCH When creating Die pins or changing their attributes an oval is placed on the pin
0 M" K* w0 r3 J1242461 SIP_LAYOUT OTHER SiP Layout - DIE is being mirrored when placing
0 g- B* o/ J% s$ ?! C1242682 CONCEPT_HDL PDF PDF Pubisher crash DEHDL on design
1 C# d+ |5 C$ F* y% L1242685 SIG_INTEGRITY SIGNOISE Incorrect net name was displayed/output if the net include consecutive underscore.
5 x1 _( S0 R) X% L* G, C3 c1243357 ALLEGRO_EDITOR INTERFACES Ability to add any new name2 G8 J+ t" M3 i4 U
1243758 ADW COMPONENT_BROWSE I don't see an option to switch between database and cache mode# G$ G& c2 O% j7 m
1244325 ALLEGRO_EDITOR INTERFACES Merge all the BOMItems with same part number into one single entry in IPC2581B.9 S% K+ {- ]$ |& \
1245363 CONCEPT_HDL CORE Design Entry HDL program crashes upon save2 s+ R5 c. m3 }. w7 q
1245790 ALLEGRO_EDITOR PADS_IN Bug: PADS Translation with 16.6s023 gives parse error4 Z/ `1 W/ z( p8 T: A
1246343 ALLEGRO_EDITOR SKILL axlAirGap command is broken in s022
$ G7 r7 O0 Y- C$ k8 A0 F4 Y! F1246419 CONSTRAINT_MGR OTHER Netrev fails with SPMHGE-268 on existing design7 \ [7 P8 A, D7 D
1246878 CONCEPT_HDL CORE Changing Symbol in Variant Editor makes schematic page crash
. Z a+ [) Y/ n, ~1246884 ALLEGRO_EDITOR GRAPHICS Infinite cursor disappears from the canvas after step package mapping GUI is closed.
$ `1 N1 {. r0 |5 w1247016 ALLEGRO_EDITOR INTERFACES STEP Model of connector cannot be zoomed sufficiently after mapping it to symbol dra file.
1 `: e$ t6 ?6 p6 z1247107 ALLEGRO_EDITOR INTERFACES Incorrect Spelling in IPC-2581 EntryFillDesc field
2 q) K( A2 n: d: ]/ E4 H) O1247177 SIP_LAYOUT WIREBOND Bondfingers not aligning to wire when tack point on the other wire end is moved from center1 A& s8 A$ N* C
1247400 ALLEGRO_EDITOR INTERFACES option to Export optimized PDF in color
4 h. ^6 F0 f: {& p4 _/ j0 Y# }) m/ q2 F4 R7 \
DATE: 02-28-2014 HOTFIX VERSION: 024 z- y7 `- U6 ~6 b* b; I
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CCRID PRODUCT PRODUCTLEVEL2 TITLE) e, N) }' g* X6 a4 N
===================================================================================================================================
* q, k3 D( z; e1207753 CONCEPT_HDL OTHER The Variant Name with a dash is represented by #2d- [% z B# ]$ |9 {
1234991 ADW TDA Team Design does not remove deleted page files from zip files
2 j3 o9 v6 o6 b. ?8 ~1235919 CONCEPT_HDL PDF DNI crosses are not printed on the correct components
9 y L) l: i; x1238007 ALLEGRO_EDITOR PARTITION Import partition removes properties from RKO that were on the exported partition
% L( w O5 {, p3 k( U- A, U( F1238140 CONCEPT_HDL CORE Design Entry HDL Crashing' I& j5 }- S# t' T! w
1238195 ALLEGRO_EDITOR DATABASE Via's losing net idenity after being mofifed or replaced.
+ k' Z B: C- t$ g) O) p3 ?. u- o1238478 ALLEGRO_EDITOR ARTWORK IPC-2581 negative artwork layers does not recognize shape bounding box value( O& _ u4 L3 R9 J
1238483 ALLEGRO_EDITOR ARTWORK IPC-2581 not drawing negative artwork correctly with traces in voids.+ d! p" n( _* r* L
1239070 SIP_LAYOUT WIREBOND When importing wirebond data onto a Die rotated 90 degrees the WB data is placed in the wrong locations. z3 F! P5 ?; X4 |
1239433 SIP_LAYOUT WIREBOND Need the Wirebonds to lock to the die aftter importing wirebond data
6 w" V+ [# [8 \8 `6 o, I. C- B1239952 ALLEGRO_EDITOR SYMBOL Allegro crashes with a component rotation of 45 or 135.
9 p/ l' Y2 V% _0 q) P1240205 SIP_LAYOUT DIE_EDITOR Crash occurs when trying to "oops" for a moved driver in co-design die editor in SiP
* m2 s, s, @5 i( [9 V1240288 ALLEGRO_EDITOR INTERFACES Why are some of the mechanical holes not showing up in Step output of thi design, while others are ?
% d. ^! b3 A6 F6 k* X) C1240305 ALLEGRO_EDITOR INTERFACES STEP Export gives some errors which are not documented
/ X% U6 D7 B3 H/ m1 N1240425 ALLEGRO_EDITOR DATABASE Export ODB is not working on 16.6 HF 22' d7 B8 H" ]0 Q' Z. }" ?/ U
1240879 ALLEGRO_EDITOR NC NC ROUTE file is not correct using hot fix 22 of v166; Y M: {/ D& w! S# S
1241904 ALLEGRO_EDITOR INTERFACES IDX baseline import displays false DRC with Package_height Offset until DRC update is run.
5 N0 ^+ H0 I2 Z* \- _& o1242266 ALLEGRO_EDITOR INTERFACES IPC2581 crash on HF22 and HF23
7 }# V1 l! I! U1242433 ALLEGRO_EDITOR INTERFACES ipc-2581B incorrect LayerRef values in BOTTOM side RefDes elements* ~" Y, R- x% H/ z' M( B
1242988 ALLEGRO_EDITOR SKILL Allegro crashes on skill command axlDesignFlip
4 `$ t5 I& ^$ Q1243845 FSP FPGA_SUPPORT FSP design created in 16.6 s018 will not open in 16.6 s021
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DATE: 02-14-2014 HOTFIX VERSION: 023; K( z* @ s8 q: d% m0 s
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3 r- M, g; f$ I5 \# ~CCRID PRODUCT PRODUCTLEVEL2 TITLE
- w6 h1 R) b+ |& b. ]3 z===================================================================================================================================
5 x& g! m' Z: w8 H7 A: g# Z- b, V/ @1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
1 V0 X7 Q' c5 S* d1202715 SPIF OTHER Objects loose module group attribute after Specctra
3 E y! |( z' g! q8 h( S) a" ^8 F: z4 m1203443 ADW LRM LRM takes a long time to launch for the first time
! q# K/ v9 @5 B6 [, {7 t1207204 CONCEPT_HDL CORE schematic tool crashed during save all
5 ^% x, D0 o8 G. r; Z( a1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter
) a0 \8 u/ w* D1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA" ]. d: D- N+ Q! j2 k
1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side/ L3 r8 r- O% {. [
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr8 B7 m& ~7 }& ^; h
1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.
! ^( Q: T, j4 ?! a1229234 FLOWS PROJMGR Can't open the part table file from Project Setup: h. S, Y5 U. d+ t: J! M, g
1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly." T* {- o( Y. I& K5 {
1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I72 Z; {9 W1 s6 @5 K- d
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's
3 V. a' p$ T9 A" {) M1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.2 O8 B- M4 g7 T7 ~$ o
1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes
5 _! M& s3 Z& n. X2 y3 X1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form" R$ i. E, z2 n# R7 Y
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
! g7 y1 \+ x# R7 C/ ^1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
! h; z' H# O! Y: ?# N* d0 [1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.8 k0 Q+ n1 Y/ G/ R& v' g' }; t
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.5 w7 X. Y2 z& j; |6 P
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol5 q; ?, s, u" F6 C
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
6 ]2 _0 s6 ^" G& S1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File
2 t. ~+ |5 D$ C* W1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat
8 ]0 ?) o6 j7 q
" ~4 `/ [" O5 N9 @, aDATE: 02-7-2014 HOTFIX VERSION: 022* T+ u" N# e6 R/ \1 n
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4 [+ [& a! b- N! X# fCCRID PRODUCT PRODUCTLEVEL2 TITLE7 E% Z/ o- L: f7 D7 ]
===================================================================================================================================
K% {) \) }; d; t7 L; c192358 ALLEGRO_EDITOR PADS_IN Pad_in does not translate some copper shapes
% W' J! z0 D' h% i222141 ALLEGRO_EDITOR PADS_IN PADS_IN: Extra shapes are created when importing PADS design9 V1 M- l1 c+ }, z+ j' \
274314 ALLEGRO_EDITOR PADS_IN PAD_in boundary defined for flooded area be translated DYN
( Y* }+ I6 H$ J0 k: Q% a+ Z413919 ALLEGRO_EDITOR PADS_IN pads_in cannot import width of refdes.
' f$ H# u+ T) _2 o8 F8 h2 j, t609053 ALLEGRO_EDITOR PADS_IN "Mils to oversize" of "pads in" did not work correctly for MM data.4 O* z; k. G* \& L
666214 CONCEPT_HDL OTHER Option to increase Line thickness in publishpdf utility! n d7 s2 \2 R$ Y5 p8 k
738482 ALLEGRO_EDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphics card
^' |* L# w8 Q) G( k1 P& P982950 CONCEPT_HDL OTHER change the mouse button for the stroke to have same function with in pcb editor& z2 a! L8 I) m4 X% i
1020886 SIP_LAYOUT LEFDEF_IF a quicker way to promote die pins (by importing macro_pin list)% K5 t6 v6 Q3 K
1032678 CIS VIEW_DATABASE_PA View Database Part gives incorrect result in complex design with variants.$ f. }9 q$ F! u' o" ] j3 z
1033864 ALLEGRO_EDITOR PADS_IN pads_in doesnot translates teardrops present in design
$ E" d9 \/ | H9 f7 H) i1054862 CONCEPT_HDL OTHER Option to increase Line thickness in publishpdf utility
9 \# R" ] e) R; B7 }1055252 FSP PROCESS Add a synthesis option to target a group to contiguous or consecutive banks: d/ o8 M$ B" Z4 I2 M. V! f
1100772 CONSTRAINT_MGR OTHER In Constraint Manager > DRC > Spacing the Show Element DRC totals are wrong.
7 q4 F( M& x! c" p1 R2 ^, S1135020 CIS DESIGN_VARIANT Variant list is showing wrong results for hierarchical designs
4 L* i; g% t. P0 F: _1138951 SIP_LAYOUT DIE_ABSTRACT_IF Fix die abstract r/w to properly support pinnumbers on ports
7 t5 c' R- C6 ^1 ^4 j. k1140042 CONSTRAINT_MGR OTHER Diff_Pair lengths and analysis are lost after closing and opening Constraint Manager.% G- |. }; h3 t, j9 y( G4 S9 Q
1143662 ALLEGRO_EDITOR INTERACTIV Enhancement Request for RMB - Snap Pick to options increased to include Pin edge
9 j! n6 q) o$ D2 o1147961 PSPICE SIMULATOR Simulation produces no output data3 d) d! x% b& O; ?) s, M5 g
1150874 ALLEGRO_EDITOR PADS_IN Dimensions in PADS are not translated correctly during pads_in translation
, _1 d# t# F% g& c; j: ^- o1154184 CONSTRAINT_MGR CONCEPT_HDL Difference in the way topology is extracted in 16.3 versus 16.6
- x# I- z& e, ^1154770 CAPTURE PROPERTY_EDITOR Variant Name property doesn't show value in Variant View mode f, d/ k+ y Z6 u2 P O
1158350 CONCEPT_HDL CORE Need a warning Message while importing a 16.3 sub-design in a 16.6 Design
7 n' _' L9 e! a( E; \/ y1162347 ALLEGRO_EDITOR EDIT_ETCH Enh- Allow new option in Move command such that it allows stretching etch using only 45/90 degree segments directly
* \4 d# p _ G$ W* P: e' x1165553 ALLEGRO_EDITOR INTERACTIV Subclass list invoked from the status window does not represent correct colors.
X0 @3 M' [' M1168079 FSP MODEL_EDITOR Clicking OK or Save As in rules editor allows user to overwrite the master with no warning
# P: v$ X4 K' y% N+ L1172043 SCM OTHER : in pin name causes SCM to crash
4 Z' F H/ K3 N) ]8 S# g: ~; \1172207 CAPTURE STABILITY Capture crash while adding new part from Spreadsheet
5 S# X; b: w w$ @$ O" x# w1172743 ADW TDA Allowed character set for the check-in comments is too limited p! U3 }- E5 X0 z! T6 r0 g( s$ v
1174099 SIP_LAYOUT WIREBOND Option to reconnect wire based on 縫in name� in the Wire Bond Replace2 P4 u0 \2 V( D# x
1177672 APD IMPORT_DATA Netlist-in wizard didn縯 provide detail information about what columns have been ignored by import process
4 E# C3 s5 G- F7 H& \0 J1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATION property can not be set to invisible
: d+ Z3 R9 S/ _9 A1177820 CONSTRAINT_MGR INTERACTIV Done the Allegro command when attempting to launch CM) c" [9 Y- T8 Z. O$ d
1178586 ALLEGRO_EDITOR EDIT_SHAPE Number of digits displayed after the decimal point of Shape Creation function does not match the Accuracy of BRD
, d2 h; \" D2 `- I2 J( o5 p' P1179688 PSPICE STABILITY pspice crash for particular HOME variable vlaue* `" Y" `1 @$ c' l
1179827 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to Symbol export - enable field to add Keywords for data fields to excell cells
' Q9 M4 r6 i% B$ N; n: a1179879 SIP_LAYOUT STREAM_IF Data file corrupt when exporting Stream data from SiP database.: b: {: L5 D# x4 `2 P5 ]
1180164 F2B BOM BOM csv data format converts to excel formats
; B& G5 E1 G/ `5 J* m r5 L1180477 ALLEGRO_EDITOR INTERFACES IPC-356 output is listing a duplicate location in the comment section. m5 N+ ?+ F/ U- l5 t5 g( Y7 G
1180932 SIP_LAYOUT OTHER SiP Layout - Symbol to Spreadsheet add option for writing to existing spreadsheet: Z$ H8 n6 x* `- B: _
1181377 ALLEGRO_EDITOR INTERACTIV Pick Releative does not work correctly with RMB-Move Vertex
* M8 i5 _* y: _: w4 r( N1 k, S1181516 ALLEGRO_EDITOR DRC_CONSTR Getting a "Thru Pin to Route Keepout Spacing" when there should not be one.* E) m. G/ i1 L4 k5 ]7 }& L
1181739 GRE CORE Running Plan > Spatial crashes GRE
: X1 I/ Q. J. s) n, k: M9 w- K1181935 ALLEGRO_EDITOR DATABASE Enh. Property that allows internal C-C DRC errors3 T- u5 z+ j& r# k( Y' F, T
1182185 SIP_LAYOUT OTHER SiP Layout - Import symbol spreadsheet - suppress Family for the font in the XML spreadsheet
; t* t! V: J g, f1182566 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to symbol - Enhance ability of spreadsheet exchange to allow for a portion of a full pin map
, i+ U7 a, O" Q) h8 u1182599 CONSTRAINT_MGR DATABASE CM Prop Delay Actuals do not update after Z Axis option is turned ON or OFF and Analyze is run., l6 j: m$ N9 d E; @: V
1182892 CAPTURE SCHEMATIC_EDITOR Pspice marker rotation before placement
/ a9 k. T5 q3 x+ X1183682 ALLEGRO_EDITOR DRC_CONSTR Implement Nodrc_Sym_Pin_Soldermask & Nodrc_Sym_Pin_Pastemask to symbol level
F( e3 Q$ c, o* [1185445 SIP_LAYOUT DIE_ABSTRACT_IF Die abstract export needs to be able to select xda file type when browsing
- s v6 [. ]9 ]6 l1185932 ALLEGRO_EDITOR SHAPE Soldermask in solder mask void DRC c2 L0 r3 ~5 X+ d* F
1185946 CONCEPT_HDL CORE Ericsson perfomance testing report 5 sept 2013" ~# j- Z4 x/ n
1187213 FLOWS PROJMGR Unable to lock the directive: backannotate_forward5 M @1 b/ g- K: m$ ]
1187444 ALLEGRO_EDITOR DRC_CONSTR With this design Database check prompts error "SPMHGE-47: Error in call to batch DRC"
1 p' N, a8 N+ i- \1187597 ALLEGRO_EDITOR DRC_CONSTR No Package to Package Spacing DRC error, when symbol overlap sideways at 45 degree.+ @* `, i: S0 S3 u6 I2 N
1187723 FSP PROCESS Synthesis can fail depending on component placement
4 k( r) K- t3 h( z0 k. r- z1188164 SIP_LAYOUT OTHER SiP Layout - Spreadsheet interfaces Import Export and Add Component - include Keyword for NET_GROUP5 z2 g4 E) r- p. z* h
1188245 CONCEPT_HDL CORE INFO(SPCOCN-2055): You cannot run the CHANGE command in a read only schematic$ K$ ]8 b) H' p6 {5 P2 @4 t& s
1190927 CONCEPT_HDL CORE Check sheet does not report shorted signal/power nets if power symbol is connected to a pin }+ q9 A1 i" Y, C; G6 U
1191497 ALLEGRO_EDITOR INTERACTIV ENH: Adding names to the text block parameters numbers! l7 Q, ]6 q/ |2 W5 |, V a
1192005 SIP_LAYOUT IMPORT_DATA Import SPD2 is missing 1 smart metal shape from file$ E: l" [ J" B* n5 Z- N
1192204 ALLEGRO_EDITOR EXTRACT Need ability to extract vias that are labeled as microvia) h$ J& g7 e2 u0 M
1193063 ALLEGRO_EDITOR MANUFACT TestPrep log displays "Pin is not accessible from bottom". The component is through hole.
! R) Y% |3 h, i1 V C1193418 ALLEGRO_EDITOR GRAPHICS 3D Viewer can`t export image in both SPB166S015 and SPB165S0470 E% r+ \0 F" L( G
1194305 SIP_LAYOUT EXPORT_DATA export package overlay creates file with no package info( f9 k9 x6 j0 v8 }
1194418 APD IMPORT_DATA issue when do File->import->netlist-in wizard
% z& b3 e$ e9 O6 K5 d+ L5 M1195279 F2B PACKAGERXL Ptf files are not being read when packaging with Cache( a' R" z' t# l, ]7 R# J5 n
1195374 ALLEGRO_EDITOR INTERACTIV Modules are not showing up in Tools > Module reports( g9 y6 j5 W5 e$ Y2 a% U
1196603 SIP_LAYOUT EXPORT_DATA Change form for "Write Package Overlay..." to better support longer lists of routing layers2 n) V% y- `: i
1197302 CONSTRAINT_MGR UI_FORMS Inconsistancy in selection of object for Spacing Constraint Worksheet
7 l/ W/ M1 o- I: U$ B1197399 CAPTURE OTHER Draw toolbar disappears when using Print Preview& X; b, }* f5 d* }
1197543 ADW TDA TDO does not correctly show deleted pages/ n& P- D, ?5 `5 ^
1198033 CONCEPT_HDL CORE Signals do not get highlighted when Show Physical Net Name is option enabled
; j, S6 k4 A/ Q2 k5 ~+ V/ F( @1198468 ALLEGRO_EDITOR GRAPHICS 3D_step model does not show the correct view in 3D_Viewer when symbols have multiple place_bounds., k: U% Z$ F% l9 M( E
1198617 CIS GEN_BOM Mech parts are showing with Part reference in CIS BOM2 S* }" ?1 X$ ]* c
1199764 ALLEGRO_EDITOR SHAPE Allegro crashes when trying to delete small island on POWER layer.
7 L) P: h" @! x1 [1200232 ALLEGRO_EDITOR INTERACTIV Moving all items including board outline which is made of lines does not move the board outline in General Edit Mode.% U1 s' m: b( [9 M- i
1200748 ALLEGRO_EDITOR INTERACTIV Additional pin edge vertex object to snap pick8 M) t! E6 l9 e, _! J8 B3 l* W) B
1201056 ALLEGRO_EDITOR DATABASE Unsupported functionality strip design creates a .SAV file/ h- Q j3 I0 Q4 }2 X, J
1201638 CIS PART_MANAGER Part retains previous linking inside the subgroup2 E7 Y# z1 ~; e: M7 s$ T% V; n
1201834 ALLEGRO_EDITOR PLOTTING Bug: Import Logo command changes resulting imported object
. C7 U9 s* L$ X# t _1202406 SIP_LAYOUT OTHER enable the dynamic display of component pin names for co-design dies in Sip Layout# M# B9 I. r" t; s& g
1202431 CONCEPT_HDL PDF The publishpdf -variant option should have a "no graphics" option
- O( d6 Z; N" Z! q# F1202717 ALLEGRO_EDITOR DATABASE About Warning(SPMHA1-108):Illegal line segment ... end points.
' F* D9 O1 d O s6 ?1203459 CONSTRAINT_MGR INTERACTIV Object Report has no mechanism to output information for a specific design.
! S+ @) w% [) h# G8 O1204544 F2B DESIGNVARI Variant Editor does not warn on save if no write permissions are on the file
, ] x P1 U2 h/ v; r1 R1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDL syntax+ a* e L& Y7 m& z
1205952 ALLEGRO_EDITOR GRAPHICS Step Model for Mechanical Part is visible in 3D viewer only when Etch Top Subclass is enabled, Z2 p T3 w; {8 k5 r
1206103 SIP_LAYOUT IC_IO_EDITING add port name property to pins, and add Skill access I/O driver cell data
: c$ q' {0 M7 Z1206546 CAPTURE ANNOTATE User assigned refdes are resetting when 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�5 e- p% ?% g/ p7 \+ u
1206561 ALLEGRO_EDITOR GRAPHICS Not all mechanical symbols made with Step files are displayed in the 3D View
) ^; P2 V8 W# e9 w" B4 N1207125 SIG_INTEGRITY ASSIGN_TOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus
* p4 A' U% n' _1207386 CAPTURE GENERATE_PART Altera pin file not generating the part properly
7 X* T+ R6 [# b2 r) r Z1207629 CAPTURE TCL_INTERFACE Bug: GetMACAddresses tcl command not working9 p7 ?! _6 f6 p8 i
1207994 CAPTURE TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pins with black color3 U* [5 g% }# s a0 r( M) v
1208017 F2B DESIGNVARI sch name is not same when updating Schematic View while backannotating Variant
3 r* u/ w3 n9 G1209363 ALLEGRO_EDITOR INTERFACES When placing pins using the polar command the tool returns 4500.00 for 45 degrees.
. R5 W; M7 A7 p$ Y8 J) y/ |% N1209769 CONCEPT_HDL CORE Top DCF gate information missing: b& y/ C8 R( V) f8 S( Y8 G) {4 S
1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box8 y' `9 X( b6 B) K
1210442 CONCEPT_HDL INFRA Save design gives ERROR(SPCOCN-1995): Non synchronized constraint property found in schematic page
# d* E: g/ M2 v x1210685 ASI_PI GUI User can't edit padstack in PowerDC-lite
5 @) ?# g; Q2 J- n% r9 R5 c1210744 SIG_INTEGRITY SIGWAVE SigWave: FFT Mode Display unit seems not to be correct( C8 i0 @' h& V! z6 K1 [
1210829 CAPTURE NETLIST_VERILOG Shorted port is missing from verilog file
. w+ x, c9 W& I7 k$ L: V# [1210850 CONCEPT_HDL CORE DE-HDL backannotation crashing after instantiating specific cell from Ericsson BPc Library* y% N' F+ M8 X! q) w( q
1211620 ADW COMPONENT_BROWSE Component Browser Performance) ?3 [% [1 s" f. X
1212102 ALLEGRO_EDITOR INTERACTIV Shape edit boundary adds arc mirrored to the highlighted preview.; X9 j) X* Q; e! [
1213294 CONCEPT_HDL SECTION DE-HDL windows mode multiple section fails to section first contactor pin from column of individual pins
# `1 ?# E ^+ n$ @% o1213402 APD DATABASE The old "ix 0 0" fix is now causing the features to lose nets entirely.
. V+ J$ n* J9 k$ J4 T2 t1213694 ALLEGRO_EDITOR PARTITION Via connected to Dummy Net pin in Partition gets connected to shape on the board after importing partition
$ y! |* W( l+ e& S1 h: j1214247 CONSTRAINT_MGR UI_FORMS Selecting the "All" folder in Spacing Constraints in CM does not automatically select the first column for editing* c3 f4 i2 d' B- z8 \$ b
1214320 SIG_INTEGRITY SIGNOISE signoise command with -L and -k option
. z6 z+ ]% ~% ?9 T4 {! n8 \* w1214433 CONCEPT_HDL CORE Genview does not update sym_1 with ports added to the schematic
" \( L/ c8 ^+ x! y$ M0 f1214909 ALLEGRO_EDITOR NC NC Drill Legend show extra rows for drills
8 N: e: l6 ~& P1 k" B1214916 SIP_LAYOUT OTHER package design integrity check for via-pin alignment with fix enabled hangs
) q' S+ u* z1 O" A2 |1215954 SIG_INTEGRITY SIMULATION Cycle.msm does not exist error when simulating extracted net# u5 Q% t. U2 v q8 _
1216328 CAPTURE STABILITY Capture crash6 @1 R. k* S" ^+ s+ `
1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.0495 k" h. x( [- B
1217450 F2B BOM ERROR 233: Output file path does not exist6 G# o1 e' K$ U K; V+ I3 a
1217612 ALLEGRO_EDITOR INTERACTIV Replace padstack will not replace padstacks that have multiple alphabetic characters in the pin name - AB21-AB377 h/ p: F. } r* `; l; }# }$ S1 ]
1217823 ALLEGRO_EDITOR INTERACTIV Compose shape fails with SPMHIS-4734 ? W1 m1 g }- b) ~
1217887 ALLEGRO_EDITOR INTERFACES An undo option to be made available in the STEP Package Mapping window
2 X W7 R3 \, {- R( \, e' D6 {1218665 ALLEGRO_EDITOR INTERFACES In step viewer, the bottom side parts are placed above the pcb board surface
7 U# T2 P3 Y9 Q, l a$ Z) S1219053 PSPICE PROBE PSpice crash with the attached Design A( X, s3 G3 o7 R F+ g
1219067 ALLEGRO_EDITOR EDIT_ETCH dynamic fillets behavior is unstable
! Y/ G8 R* [ X1219095 ALLEGRO_EDITOR MANUFACT Design Cross section chart is tapered for two layer board
Q- i# q& j: e E: k& c3 N: I1219126 ALLEGRO_EDITOR SKILL Skill issue with axlRefreshSymbol()6 Z+ N. Z! ?+ q6 z ^7 T W6 U
1220701 ALLEGRO_EDITOR INTERACTIV View > Windows > Worldview (showhide view command) fails with command not found- J2 W$ |8 I$ D4 P# O; N
1221057 ALLEGRO_EDITOR REPORTS Units in Cross section report for spacing is not synced with the design3 i% D9 C0 b& `+ @9 x, s
1221139 ALLEGRO_EDITOR EDIT_ETCH Delay tune is not tuning differential pair4 `5 I3 y6 l# ~' v. p# j9 `" l& I
1221157 SIP_LAYOUT IMPORT_DATA import spd2/na2 file is not importing data correctly into sip
; U6 \. E- C' P) L1221163 SIG_INTEGRITY GEOMETRY_EXTRACT Simulation aborts with severe convergence issue when coupled vias is enabled.( a3 X V6 n |; S& S! g
1221416 ALLEGRO_EDITOR DATABASE strip design for function type
& P) F) a/ P9 L U# n3 j# d. c" ~1 m1221931 ALLEGRO_EDITOR DATABASE Fatal software error when embedding component
$ ^1 I. `8 Q C9 X1222105 CONCEPT_HDL CORE Moving Pins around the edge of a Block causes the text of the pin to change its text size.* ~+ t3 [8 n% |7 r
1222124 APD DATABASE Same Net DRC's exhibiting inconsistent behavior.
9 H3 d4 y. e+ [1222272 SIG_EXPLORER EXTRACTTOP Cannot extract net or open SigXplorer after selecting a netgroup G/ |& A2 P8 g/ J2 u/ K
1222329 ALLEGRO_EDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top
0 \0 K! L1 u' N: u1223183 SIP_LAYOUT BGA_GENERATOR Getting an incorrect error message when using the BGA generator with a long BGA name.
D& T5 m- l, ~1223662 ALLEGRO_EDITOR REFRESH Allegro crashes when trying to refresh symbol! r( O9 g7 e3 l1 @
1223932 CONCEPT_HDL CORE DEHDL block desend does not find 1st page if its not page1
3 |3 n( y0 n7 Q% ]+ Y+ U" D8 I1223940 CONSTRAINT_MGR UI_FORMS Unable to change CLOCK name in Setup/Hold Worksheet under Timing in CM.
, T) @; O- c& l; o! q) g1224127 SIG_INTEGRITY IRDROP Is the old static IRDrop in 16.6 officially supported?
. L' R/ J' `! s7 A1 e. @1225492 PCB_LIBRARIAN CORE PDV expand vector pins resizes symbol outline to maximum height again4 I8 N8 D; p4 k# J( t* g8 ^
1225546 CONSTRAINT_MGR ECS_APPLY nets where the referenced ECS maps correctly in constraints manager for front end but not in back end: |6 u2 G& _2 S3 { i3 j
1226405 ALLEGRO_EDITOR INTERFACES File > Export > IDF ask for filter config file eventhough it is created in same session and stored in parent folder
# P: W5 K3 a: d& V) O% s1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDN Analysis with XL and GXL% r% [7 _; Y8 Y1 h5 S
1228721 SIP_LAYOUT OTHER File Export Netlist Spreadsheet enhance sort to be a natural method per Jedec according to customer/ t v( f: @' @, X B
9 l, {' t7 r! I! Q
DATE: 12-20-2013 HOTFIX VERSION: 021
, J) @) q% w5 v* R8 m/ c# k===================================================================================================================================) |! W* E& p5 _" V
CCRID PRODUCT PRODUCTLEVEL2 TITLE" M d) g' E3 n4 K& F# `+ g+ w: K
===================================================================================================================================
' ~4 E* g3 Z% ?4 z5 E) @1214932 ALLEGRO_EDITOR OTHER Allegro will crash when performing show dimension on linear dimensions.! v& \9 S6 Y$ w$ M9 _ A
1215045 ALLEGRO_EDITOR SKILL Successive file open / ipc calls crashes Allegro 16.6
7 V' V- @( O* L8 B3 W8 S1215115 ALLEGRO_EDITOR NC drawing name doesn't display in the ncdrill.log file
: C& ]* P* m t3 f7 u# D, u% A1216028 SIP_LAYOUT PLACEMENT Design will not update embedded component symbols.4 s- o3 a' d3 s \$ m( x. \: w$ a
1218451 ALLEGRO_EDITOR DRC_CONSTR Route Keepout to Pin DRC created even after adding Void in RKO shape! @, V' d$ `6 y
1218636 ALLEGRO_EDITOR SCHEM_FTB netin process will rotate embedded symbols
9 d$ m) S& u% K6 C& {1218706 CONSTRAINT_MGR CONCEPT_HDL NCC associations get deleted from FE CM
7 e* v7 m( M- T9 i/ f1 S; `( ~2 t8 [1 }: U L
DATE: 12-4-2013 HOTFIX VERSION: 020
, U$ m3 ^; |' V3 p, H6 L3 c% G===================================================================================================================================8 C& I* V" D# p) s
CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 \( L( L) z" ?===================================================================================================================================
+ C4 x1 @: R0 H# y) N' e& o- a7 Q1116426 F2B PACKAGERXL Packaging in 16.6 increased by 3 folds compared to 16.37 D c5 a( V- T3 v7 f- o! @, |& l
1190095 CONCEPT_HDL CORE In Windows mode select the part and click on version placed selected version +1., F5 J9 b+ f+ T1 S) v0 |2 F
1199410 CONSTRAINT_MGR CONCEPT_HDL Constraint Differences Report window hangs in 16.6-s0166 T% f' ]/ g8 u+ ~- e, U. |
1199425 CONSTRAINT_MGR CONCEPT_HDL Import Physical fails (the cmfeeback.exe has stopped working) in 16.6-s016
9 H! D1 f8 P7 ~* j! n' |1199700 PSPICE NETLISTER Netlist fails on addition of netgroup
. D+ F* H+ d% g4 _% u! X8 d1200936 CONCEPT_HDL PDF publishpdf fails if UNC paths are provided from the command line
/ ~4 b3 _3 @9 {! n7 y, z( g1202391 CONSTRAINT_MGR OTHER Getting 'An Invalid argument was encountered' when generating Net Class-Class report in CM3 _# y, ~( p" _5 {/ n) J
1202587 CONCEPT_HDL CREFER Crefer schematic reports cannot be deleted on Linux.
2 O) i' w+ h3 `( y9 F1203143 GRE CORE GRE crashes on running Plan > Spatial
- f: e* \- x- X6 P1206019 ALLEGRO_EDITOR INTERACTIV Allegro needs to be restrated to read steppath with 16.6 S017$ b; c8 y! @& i; h, f- d
1207050 ALLEGRO_EDITOR INTERACTIV Refresh Padstack fails on Warning
& b! _! F1 L1 U. _: f# ?/ c1207178 CONCEPT_HDL CORE Aqua color on wire does not matches icon color) ^; d5 L, h8 g( N% g
1208152 F2B DESIGNASSC ERROR: Dictionary File: cmdict.l could not be found% U5 m6 q; C. ]) k2 C
1208276 APD STREAM_IF Stream in fails to import what Allegro exported6 v; h! ~$ `# T I8 {/ s
1208345 ALLEGRO_EDITOR SKILL Why axlChangeLayer not working for shapes on this attached skill file?
. _& Y* l- x a6 V& m1208351 ALLEGRO_EDITOR SKILL axlFilmCreate do not define the IPC2581 domain correctly.
$ `/ r4 V. z% W' Z4 m9 p1208467 PCB_LIBRARIAN VERIFICATION con2con mangles cell data after checking cell having syntax errors on part_table6 B2 K0 N& Z w7 r* l# {/ e
1208579 SIG_INTEGRITY GEOMETRY_EXTRACT Incorrect traces are extracted when void area is less than anl_min_void_area setting
: ^; e+ z" P1 n, ^, m& G" K1209347 ALLEGRO_EDITOR PARTITION Import partition that has diametral dimensions will crash Allegro D4 L! j$ R* B6 `% S0 ~/ c) A
1209897 ALLEGRO_EDITOR PADS_IN Pads_in will not translate design.
5 J6 }, C; L- d: j. ^1209902 PCB_LIBRARIAN CORE PDV crashes reading part; x- d( n0 @, M# i; z
1210183 PSPICE SIMULATOR SimSrvr crash with ORPROBE-3211 RPC Server unavailable Message0 K, F9 D4 ^, V: t
1210408 ALLEGRO_EDITOR EDIT_ETCH AiBT hangs when doing interactive breakout on bundles using latest hotfix.6 T" @, U! m# U# Q
1210443 ALLEGRO_EDITOR INTERFACES Allegro Design Publisher does not create fully searchable PDF for some of the text that are present or certain layers; c% L) @6 v5 M
1210876 CONCEPT_HDL ARCHIVER Archiver wrongfully deletes directories.
. D4 t: V3 P6 ~. K1211839 CONSTRAINT_MGR DATABASE Topology can't be extracted correctly.: ^/ M& ~) d3 _) E% R3 r
1212709 ALLEGRO_EDITOR DATABASE No connect can`t be detected in SPB165S048
! A6 `, k( Y* d( ^$ ?% m2 n9 Z1213752 CONSTRAINT_MGR OTHER "Show Constraint Difference Report" option at File > Import > Logic does not retain the last setting
8 v! j! @9 d$ M% \. a0 H; _' g7 l" C. Z7 c7 `
DATE: 11-15-2013 HOTFIX VERSION: 019$ V. P) u! f" A$ Z" C* C
===================================================================================================================================
# S' j" n9 h8 H wCCRID PRODUCT PRODUCTLEVEL2 TITLE8 c/ S0 r S, d1 G& g5 ~
===================================================================================================================================
# l; b `! s2 g+ k' A; b- Y3 W* l, H1176155 CONCEPT_HDL CORE Graphics remnants with 16.6 QIR 3
% _+ p' |* C9 d1178272 CONCEPT_HDL OTHER Verilog netlist does not include split blocks correctly% T/ x" U4 u. _3 C* T
1190782 FSP FPGA_SUPPORT Support for Altera > 5SGXEA9N2F45 device.
8 T+ u" C! A B8 @1194140 ADW LRM SYNC_PROPERTIES is not resolving issues a based sync_properties settings5 D8 d' ]! J" F! P8 @9 D ^
1195744 APD EDIT_ETCH Diff_Pair routing fails on certain Uvias in the pair.- z/ Z+ p/ H6 Q1 \) p1 K/ \2 L
1196704 ALLEGRO_EDITOR INTERFACES ENH: During ipc2581 export checkboxes corresponding to 縈iscellaneous Image Layers� should automatically get selected! g- ` j) ^/ b5 ?2 V& J3 d8 T
1198340 ALLEGRO_EDITOR OTHER Multiple -product option on the Allegro command line does not access the second -product* T& K, O0 _. u* H6 o
1198596 ALLEGRO_EDITOR INTERFACES When copper thickness is increased for the outer layers, step Viewer does not show correct component position.
" R3 S( k1 c, H" [" I1199673 PCB_LIBRARIAN OTHER Component Browser fails to load footrpints if they are set with UNC path
* ^1 {- j9 |" c3 o0 v2 s1199889 ALLEGRO_EDITOR DATABASE Allegro crashing with latest hotfix.8 e+ ~: I" R& `) t( N1 c
1200303 ALLEGRO_EDITOR GRAPHICS 3D Viewer does not update after changing STEP model mapping: u6 N9 s2 k" i9 [: o. Z n
1200449 ALLEGRO_EDITOR REPORTS Allegro crashes when generating Net Loop Report.
, w( F6 I; D$ i6 ]% c1200915 ALLEGRO_EDITOR DATABASE Reducing accuracy of this specific design crashes Allegro
: m& s8 X. d5 m0 _5 ]: N5 e0 o1201011 ADW COMPONENT_BROWSE Component Browser crashes in DB mode2 q3 O3 `- ~& C+ w8 [! R9 k0 K( |- E4 `
1201376 ALLEGRO_EDITOR INTERFACES Allegro hangs when trying to map a specific STEP model to a package drawing.7 R" [) B: x" K# b, D5 B
1201897 SIP_LAYOUT IMPORT_DATA BGA Pin Colors not matching the Colors defined in the Symbol Spreadsheet after updating.
( h u* Y+ m' ?) y1202709 ALLEGRO_EDITOR INTERFACES STEP File generated from Allegro is not overwritten when the variable "set ads_textrevs
7 ]6 E8 }* e8 S8 ~; {1202820 ALLEGRO_EDITOR INTERFACES Different xml generation for same step model on S106 and S017
9 Z0 V2 l. ]1 ]+ f1202842 ALLEGRO_EDITOR INTERFACES Step model invisible for one pin dra in allegro 16.6 symbol editor z9 w/ _7 z" Z
1202983 ALLEGRO_EDITOR SHAPE Shape voiding creates DRC with Route Keepout
+ l% s ~8 ?8 O7 |1203125 ALLEGRO_EDITOR OTHER Exporting STEP file with External copper enabled does not show all copper when viewed with Solid Edge or Inventor
" L8 L- d3 V# w, \0 H* Z: l1203236 ALLEGRO_EDITOR INTERFACES IPC2581 output with crosshatched shape is not correct. e1 m; A: H, Y$ d; A; C
1203995 CONCEPT_HDL CHECKPLUS CheckPlus rule, local_signal_no_offpage_body, getting an incorrect failure.
, m$ T# \# a I- w% ?1 s+ F1204629 ALLEGRO_EDITOR SKILL axlUIDataBrowse crashes the editor or returns error8 h- j% ^2 m5 E+ j
1204640 SIP_LAYOUT DIE_EDITOR Concurrent co-design update fails
, c: \3 T' e6 _& K$ j( {1204881 SIP_LAYOUT BGA_GENERATOR Pin numbers are messed up after deleting a pin at a staggered bga
5 i3 L! J4 T! o/ m1 h" t0 {" G1204885 CONCEPT_HDL CONSTRAINT_MGR Cant assign discrete models after the wrong model was removed.
" m% j: O* Z. s+ k6 R4 \- U1205374 ALLEGRO_EDITOR OTHER pdf out command creates incorrect drill Symbol Characters placement in pdf file when setting film mirrored.( x3 \7 h# B$ v0 g: M" M8 j
1205729 SIP_LAYOUT DIE_EDITOR update of codesign db fails on exit from die editor4 }3 W7 t, ]5 t6 r. K
1205801 ALLEGRO_EDITOR OTHER Tool crash when do export IPF." C5 W. r$ g. ^& A6 ?
1205881 CONSTRAINT_MGR OTHER In CMGR , Objects > Create crashes Allegro
# K1 K& y% {/ s) ?
: G- R N, O. V- ~& F! kDATE: 10-25-2013 HOTFIX VERSION: 018* d1 D* p: k; }- z- I Q
===================================================================================================================================
3 j; u* G+ _; o, k! ICCRID PRODUCT PRODUCTLEVEL2 TITLE
8 \, q+ Z( P) R$ H" K9 j2 ?=================================================================================================================================== g) U' @5 v3 F* |" N$ N
1118303 CONCEPT_HDL CONSTRAINT_MGR can not prdefine default units in HDL
* R6 D7 I* Q ~( p0 I4 `1174901 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl
9 p& o4 [ m5 R+ N, f! L4 [' p# w1176990 CONCEPT_HDL OTHER DEHDL BOM tool doesn縯 see similar names.
1 Q4 {$ c" O3 k5 a1179665 GRE CORE Plan Topological Crashes after around 8 hours of routing.3 N/ Y# F# Y0 t& Y* R' J
1188193 CONCEPT_HDL CHECKPLUS CheckPlus not recognizing PIN as a base object.
4 q7 A# U2 g9 ]! F" s8 B1189100 SCM OTHER Replace part in SCM using ADW as library fails4 { U: B3 J6 J4 {0 X2 n/ `
1189507 SCM SCHGEN ERROR(SPCOCN-2009): Package error after second schgen run with Preserve mode.$ g+ ~0 I. ~9 }) f6 x4 D
1192391 CONSTRAINT_MGR CONCEPT_HDL Restore from definition deletes local objects in other blocks
0 }* s3 g) D4 ~5 J4 N1194597 FSP OTHER Pin definition problem
! K. U. H0 n4 W# D( j* d/ ?2 h1195202 SIP_LAYOUT LEFDEF_IF Cannot add .lef files in IC Library Manager. Getting warning message WARNING(SPMHLD-52)- s6 t- v9 J2 {, [: }
1195309 GRE CORE GRE crashing during Plan Spatial.5 Y* j/ o5 z4 p5 k. A) S
1197262 ALLEGRO_EDITOR MANUFACT Angular Dimension created in symbol is placed w.r.t. board origin and angle is blank& o' k, l% J& b6 h1 W8 M0 ~
1198521 CONCEPT_HDL OTHER cadence DEHDL issue - Note for Hotfix_SPB16.60.016_wint_1of1
4 O7 a z, e. V8 m$ H1199219 ALLEGRO_EDITOR INTERFACES Question on STEP Model export which uses PLACE_BOUND layer for any symbols that do not have STEP model mapped; k" P2 D/ i( i. Q% h
1199235 ALLEGRO_EDITOR SCHEM_FTB capture's behavior is redundant while creating pcb editor netlist& P- h6 C7 i% ^8 X1 Q
1199323 GRE IFP_INTERACTIVE Crash when importing logic/ ?. C/ u5 n. V" R, Q- g7 q- t) w
1199368 SIP_LAYOUT DIE_EDITOR Refresh of die abstract in die editor with this design takes over two hours
, C* [. r0 a! c+ H$ m1 f- m# a1199760 ALLEGRO_EDITOR DATABASE Allegr won't display Soldermask Top layer6 r* U+ T' {- q7 u' Y
+ D1 M0 t. Z1 o7 r* Z
DATE: 10-10-2013 HOTFIX VERSION: 017: w5 q' i% @6 w5 }0 U7 R5 i& n8 e
===================================================================================================================================$ D I" K. A( ?) O4 f& [/ P2 m
CCRID PRODUCT PRODUCTLEVEL2 TITLE2 U' C' B) ?4 L7 z
===================================================================================================================================
6 [' h% y& h# z5 U4 \# P# o$ @735992 ADW LIB_FLOW Create Test Schematic does not use the correct package type
8 E# f% m" Z- @1121403 FSP PROCESS "Assign to Pin" not getting obeyed by Synthesis.7 q" h! r6 v Q2 Q$ Z. D* }! s
1141844 RF_PCB DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing
2 I) s) _, g% O9 S' F1169269 ALLEGRO_EDITOR DRAFTING Dimension placed on package symbol moves to different place when it is placed on brd file.9 X+ S5 K( T0 z1 I) k
1170488 ALLEGRO_EDITOR MANUFACT Dimension text(on .psm) move to different position, when it is placed on .brd.$ @! ?$ ^1 X6 ]" X" b/ s% P
1173345 CIS CRYSTAL_REPORTS Crystal Report - Display Parameter dialog for export option
3 I( R/ j+ K0 H# h+ H1181759 SCM LVS SCM Crash when doing update all that executing import physical command. F$ L6 ]! I6 g
1182499 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks (all pins and via) drill.
/ k$ V" a0 Y6 ]3 D1184682 CONCEPT_HDL CONSTRAINT_MGR Net Constraint not transferring to layout from schematic6 Q$ `+ T7 M g$ z# C( S6 _% t
1185524 F2B PACKAGERXL Enhancement User would like notification of pack_short in pxl.log
5 |$ f8 j* F9 U3 _1185902 ALLEGRO_EDITOR SHAPE Update shapes dont clear some diffpairs in HF15: m$ N O: L0 ~" x+ H) p
1186152 ADW LRM Part Status for Deleted Part in LRM is distinguished with other part status+ @0 f& e, @* f2 @ h7 R
1186387 ALLEGRO_EDITOR OTHER DXF cannot catch offset value in s047 hotfix., a& W1 Q; U! g0 D3 _
1186805 ALLEGRO_EDITOR OTHER Exported STEP file missing multiple components placed on board3 E( S1 X8 U! I
1186818 ALLEGRO_EDITOR COLOR Custom color not retained during dehilight, p3 s2 R! w' r* i4 A6 Y# }( b
1187196 CONCEPT_HDL CORE TOC not populating (page 1)
' y: o j% v/ t5 C! L" L1187667 F2B PACKAGERXL Existing hard LOCATION property in drawing was left unchanged
6 x9 \0 t" ?# }! w2 C" K' |4 e; j8 g1188264 ALLEGRO_EDITOR MODULES Some fillets not regenerated in module created from a board file.) D5 L( j) Q" b- I4 ~/ r
1190144 ALLEGRO_EDITOR OTHER Fillet shape is not genrated around cline! F _0 e* Q. C0 F
1190210 F2B BOM The bomhdl.exe fails - MFC Application has Stopped Working
$ x% f7 t8 y l* @% s5 r2 e. x1190618 ALLEGRO_EDITOR GRAPHICS Enhancement for Visible grid
/ q5 X, n. ]( G4 c' f: K" E1190813 ALLEGRO_EDITOR INTERFACES 3rd party netlist file in TEL format fails syntax check but imports successfully
8 j" R7 ?& ]7 M+ S i0 `1190895 ALLEGRO_EDITOR EDIT_ETCH Route delay meter displays violation when sliding diff pair
4 o6 ?! p7 N/ u d4 m& t1190908 F2B OTHER DE-HDL aborts if dummy net is being cross-probed from PCB Editor5 C- \; X$ T E0 J% X7 Z0 l6 G+ A: I1 B
1190990 CONCEPT_HDL CORE Mismatch in .csa and .csb files
" l4 V/ w9 L# a5 ?1191008 CONCEPT_HDL CORE Remove Binary File feature doesn't work
& Z/ m' O( N$ g6 L( h1191514 SCM PACKAGER Packaging error PKG-100
* `4 u5 j7 b9 ?& {% m1191517 ALLEGRO_EDITOR DRAFTING Metric +tolerance when using dual dimensions is not displayed correctly
! e. P- @& ^6 G1192561 ALLEGRO_EDITOR GRAPHICS Padstack with offset is not showing correctly in the 3D Viewer.
5 b6 G) p0 o6 j1192916 ALLEGRO_EDITOR EDIT_ETCH Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.
7 r/ s4 s8 @' l2 H" {1194197 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks.
7 W% b# A2 \6 U; M/ h8 y1194239 PSPICE DEHDL Associate Model does not launch from DE-HDL: W* H% V& p" |% G' s8 u, J4 P
1194736 PSPICE SIMULATOR Design causes RPC failure when run consectively ?6 I% ^0 X, X# q
1195139 ALLEGRO_EDITOR PLACEMENT Components disappears from board file once they moved0 C" M7 @' |$ K$ I% Q ~2 U
: C, q6 ~$ U, |& E, b
DATE: 09-27-2013 HOTFIX VERSION: 0165 n: H- ^- v& U' Z8 g: A. w
===================================================================================================================================
* _& g G7 k5 Z* |5 i& A% A! F* tCCRID PRODUCT PRODUCTLEVEL2 TITLE( B9 \; `# i- a3 z0 ?( u
===================================================================================================================================. o7 n. ]5 i2 h+ h; z. d
548538 CAPTURE NETLIST_ALLEGRO Enhancement:Include mechanical parts in Allegro netlist, v8 ~( d7 F/ r" R/ U+ t
1076579 CAPTURE GENERAL Display value only if value exists
9 J& L! Q% A0 J- C) _2 {& U3 n1083904 FSP GUI Need Filter in Change FPGA dialog to select desire FPGA from the long list.
4 p+ r" D/ k7 T, E$ r/ ?' ?# y$ p1089313 ALLEGRO_EDITOR INTERFACES Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility
4 x+ B3 `, @# d' t5 t1095728 ALLEGRO_EDITOR EDIT_ETCH Slide to grab adjacent elements when extend selection is enabled" u# f9 S0 M# r
1102698 SIG_INTEGRITY ASSIGN_TOPOLOGY ECset will map on single ended nets but fails when the two nets are define as a diff pair.
! y( _. ~- Q# p& r/ @6 ]1104071 SIG_INTEGRITY REPORTS Shape Parasitic value changes for bottom shape for changes in top shape, }6 d* E8 f6 Y. L1 \
1117731 FSP POWER_MAPPING Ability to sort in Power Regulator forms9 e: K- {+ ` T7 L4 P
1121539 FSP CONFIG_SETTINGS Cannot configure special FPGA pins (temperature diodes)
1 T7 @" N8 G2 |5 ~1122721 FSP MODEL_EDITOR Partial copy-paste overwrites the complete cell in XML Editor
9 O' U* [; c1 e& F" @& r% l1123238 FSP TERMINATIONS Report functionality for terminations defined in the complete design.! u& V1 P. A" a5 p8 J
1123364 FSP GUI Clicking on column header should sort the column.
) H1 j. t& e& e- x1123403 FSP EXTERNAL_PORTS Improper checkbox selection for 緿o Not Connect� or 縀xternal Port� column1 ^; t5 ]9 P+ L+ ^! N% I* ?
1125611 CONCEPT_HDL OTHER display unconnected pin in schematic pdf.
% J1 J2 B ^) ~9 ]1129871 ALLEGRO_EDITOR INTERACTIV Wire Profile Editor can't read mcmmat.dat in working directory.2 {- `6 v% }: K9 m' s5 L+ K2 y
1133688 ALLEGRO_EDITOR GRAPHICS Enhancement request to enable 3D Viewer to show STEP model from .dra file." _$ ^2 g$ b& p: v# }4 m% J
1141747 ALLEGRO_EDITOR GRAPHICS 3D view dooesnot displays height if step_unsupported_prototype variable set
" x7 v8 D9 C l9 a$ k' d- i. d" B+ q5 f1142215 SIG_INTEGRITY SIMULATION PULSE_PARAM set on DiffPair wasn't used for designlink simulation.! }" O: v9 O$ y5 u. ~# a# _
1142798 ALLEGRO_EDITOR INTERFACES Step file output is incorrect in step viewer when composed of arcs and line.% q- b1 H( t) A& b% q6 J
1142894 FSP GUI Ability to RMB on a header and select `Hide Column�
. d8 q- w2 s4 t1142940 FSP EXTERNAL_PORTS Issue with checking/unchecking "Do not connect" and "External port" cells
+ J0 C& I) E4 j7 U l1142949 CONCEPT_HDL SKILL Usage of "Preferences > License Settings� in FSP
. O. R, _# f+ z5 e1143091 SIP_LAYOUT SYMB_EDIT_APPMOD symed: When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract
' B. ?7 A3 W6 m0 f( O1144371 CONCEPT_HDL COMP_BROWSER Component Browser search results are inaccurate7 J8 C; J( I+ E
1145033 ALLEGRO_EDITOR PLACEMENT When aligning components with options in Placement mode displays no busy indicator, ~) t( x4 U: j+ {3 i7 b6 |
1145286 CONCEPT_HDL CORE Directive required for switching off the console1 v* A) @' K! D* Q& g. q
1145800 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl.: U4 W9 j, k* `. M/ u3 z5 A$ t$ [
1147899 ALLEGRO_EDITOR SHAPE Autovoid two overlapping shapes that share the same net6 x; A4 w: b) z6 Y% G+ m
1149996 ALLEGRO_EDITOR EDIT_ETCH Routing does not follow the ratsnest 'pin to pin'.
2 ^( Y- K% {/ r1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.( p8 w. O* }+ O
1152577 ALLEGRO_EDITOR DATABASE slide removes cline seg
6 j, B. z) ]) Q1152751 CONCEPT_HDL CORE Option to double-click and copy the Netname3 l- k- h5 j5 Z8 W$ f3 v! k7 P
1153220 ALLEGRO_EDITOR INTERFACES ENH: option to supress header/footer during PDF Export
" N, X: S/ v5 a) y- `1153625 ALLEGRO_EDITOR INTERFACES If Symbol has place bound bottom, the step model shows incorrect placement.
* p+ N3 I: C( A7 I, s1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form8 n9 C& y" e- e' j2 {, ~
1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties. G6 V1 e4 A. r4 h& o/ Y
1155161 CONCEPT_HDL CORE Add Signal name: Suggestion box overlaps with the typed signal name that is typed
6 ]. u9 l% e- j8 j1155922 CONCEPT_HDL OTHER How can I use the batch mode for PDF Publisher and print a variant overlay?3 e) t$ x5 @, @! b$ b' X: Y; c6 _
1156858 ALLEGRO_EDITOR PADS_IN PADS Translator: Missing drill on square PTH padstack: Z6 L; _3 U3 Y4 ~, G3 T
1157362 APD 3D_VIEWER Need a way to color multiple nets in 3D viewer from APD/SiP.8 L. S9 t! `; M' U2 n
1158130 CONSTRAINT_MGR ANALYSIS Constraint Manager do not display the Cumulative Result in Reflection Simulation$ b/ [2 J6 V) f) a% a5 q! |
1158210 ALLEGRO_EDITOR SHAPE SIP Layout happens crash while users move the shape with route keep-out
: i- x. L0 ]& U! Y+ u! f1158452 SIG_INTEGRITY GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle
2 T+ \$ N6 E: g: Y1158827 ALLEGRO_EDITOR EDIT_ETCH Slide a via in pad automatically add cline back to via to pin.+ f, {$ z4 K& a1 `( J$ }6 z
1158871 PCB_LIBRARIAN IMPORT_CSV PIN TEXT is not automatically added when importing the .csv file- n( c% ?# G3 u u8 v
1159738 ALLEGRO_EDITOR INTERACTIV Selecting the Cancel button in the Text Edit command does not cancel the text. {+ u' a7 ]5 A# M3 ^9 g
1159878 SIG_EXPLORER OTHER Ecset mapping dont follow topology template7 @* F! c/ s0 N* g
1159971 ALLEGRO_EDITOR MANUFACT Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file
, j, N7 w; _) y r1160017 SIP_LAYOUT DIE_ABSTRACT_IF Add text to clarify shrink operation( K1 @; L* L# U! Y' U6 Y( V
1160507 APD EDIT_ETCH Script not playing back what was recorded when sliding lines3 V# N% l) O; T; B8 [$ j
1161261 ADW TDO-SHAREPOINT Schema for TDO-SP fails on Japanese OS
7 \ z- P" d, C9 ^% a/ E: [% l1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
W% U7 r: z! @+ V5 q1161636 ALLEGRO_EDITOR DRAFTING need new function for PDFout : hatching shape5 k+ A/ u& L: v+ q+ r0 v
1161777 ALLEGRO_EDITOR OTHER default line width for PDF output
+ S1 i z3 j# L' X4 Z1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.3 s9 J5 ~" ^/ v1 J3 r% ]6 |
1162562 CAPTURE STABILITY Capture crash on second attempt of pspice netlist creation in 16.69 J6 D- c0 S, l; \4 N# D3 f
1162629 FSP PROCESS "Load Process Option" under Run does not work properly6 V |) N5 U. H" X8 N2 b# H
1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE
' J) D! b5 p( f7 C1163149 ALLEGRO_EDITOR DATABASE Autosilk creates Illegal arc to corrupt database
* y+ }: Z$ _/ m; w- d3 s0 x1163439 ALLEGRO_EDITOR COLOR Duplicate Views Listed in Visibility Tab.0 `( ^) {& n4 P' l3 @, ^5 s. u
1163521 CONCEPT_HDL COMP_BROWSER System Architect crahes on replace
6 k1 d% b! x" h0 |0 s( d( x1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin
2 C4 r3 n2 B, U2 H# q) ?1163902 APD EXPORT_DATA Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?5 |6 d. H/ C) @' B% Q$ R
1164337 CONCEPT_HDL CORE Cannot delete attribute filter value in PDF > General > Attribute Filter list o& W( d+ u t& q" f( ], D
1164365 ALLEGRO_EDITOR INTERACTIV Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol, u1 v* [# i8 P' z' C
1164769 APD VIA_STRUCTURE The replace via structure command does not accept a single canvas pick.
, T3 ]! O: p- R0 m" Q1165026 ASI_SI GUI EMS3D exist in Via Model Setup of SI base. H# K/ N" i7 ]1 D1 a
1165561 CAPTURE DRC File > Check and Save clears waived DRCs
' x7 u% o' c [$ Z H$ ~1165631 CAPTURE STABILITY Capture crash in the hierarchy tab of Project Manager window
" D" y8 T7 V+ A1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)
* I% R7 i, f! m( u9 |3 A5 e1165911 FSP PROCESS Editing group name in protocol causes incorrect Process option checked
( n6 c& E" `) B% i3 Z- I1166026 ALLEGRO_EDITOR DATABASE Running DB Doctor removes net name from vias
0 q. n2 w& Q4 G- C1166034 SIP_LAYOUT OTHER SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle
8 M1 Z( S& E0 B4 t; B% @" b1166074 GRE CORE GRE crashes during planning phases) Z" g0 `/ \4 ^ ~# r0 g
1166319 ALLEGRO_EDITOR PLACEMENT Swap not succeed& u3 u5 ~+ m( B9 b$ A2 B4 o
1166484 SIP_LAYOUT WIREBOND Bondfinger "Align With Wire" problem during move
0 \$ D C; ~9 d3 c+ ~5 ^) X1166530 ALLEGRO_EDITOR INTERACTIV Bug: Mirror in Placement Edit resets the options tab for Edit > Move
5 x$ J+ ], m* m1 `' C( @: {4 T1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue' T: j( M3 Y1 T/ I
1167847 CAPTURE PROPERTY_EDITOR Implementation name length greater than 31 character causes capture crash$ \0 I% w+ J) ^1 l+ S
1167887 F2B OTHER Improve message on symbol to schematic generation
4 h: @& A0 A" Q) b6 z1168369 F2B DESIGNVARI Variant don縯 appear in increasing order while Annotate.
3 W# Q- A7 z$ q; j7 T- M1168629 APD OTHER Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD4 y9 ^+ s* g' m
1168678 ALLEGRO_EDITOR NC Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.1 l* x$ u/ E5 n5 o; E/ s- u& c
1168798 ALLEGRO_EDITOR INTERACTIV Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk
6 _7 _2 f& N+ z1 @+ M9 B1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check
! z$ q L$ a+ n# z8 L$ \: s, i1168864 ALLEGRO_EDITOR CREATE_SYM Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty) w a/ i( Q( a6 S, m& x
1169213 PSPICE SIMULATOR Parametric sweep is giving incorrect reuslts4 K8 l8 @/ |) _; L6 ^3 l# w" \# z
1169436 FSP FPGA_SUPPORT Add support for Cyclone V CSX and CST parts
' n2 J1 e, v G/ }7 ]* f1170108 ALLEGRO_EDITOR INTERACTIV Enhancement to preserve Rat T location for Topology assigned schedule. X- P4 p- m' R) C# h
1170313 SIP_LAYOUT LOGIC scm adding additional pin names and unassigned property to codesign die chips file
. W' n4 ^0 X; s* T/ u8 `1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window.
( w, y L: D' s# L- @2 h. d5 U( K1171747 ALLEGRO_EDITOR PLACEMENT Allegro crashes when doing a gate swap between components
- k2 F; R v" O! y1172183 ALLEGRO_EDITOR INTERACTIV Alignment modules fails on equal spacing
2 y$ ?3 c: ]0 C+ d) z1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via
2 }* H& x' n6 [- w7 y ^% c' E" M! G1174067 ALLEGRO_EDITOR DRC_CONSTR Soldermask to shape drc does not show if the layer is a PLANE." |' \9 q* C+ V a
1174338 ALLEGRO_EDITOR PLACEMENT preview has rotated pads. s! l! |7 H% I, s' h
1175307 CONSTRAINT_MGR ANALYSIS CMGR fails to report RPD DRC for accuracy 4 - mm3 m) S6 C( i/ s, Z% O
1175537 ALLEGRO_EDITOR REPORTS net loop report crashes Allegro. Design specific
5 O" g+ u- ]3 S9 U0 T1176126 ALLEGRO_EDITOR INTERFACES 3D viewer doesnot change models units dynamically
" S( x+ S8 Q# r1176281 CONCEPT_HDL CORE Option to Auto-hide excluded modules: Z+ N5 m7 { }/ y9 u
1176413 ALLEGRO_EDITOR MANUFACT Q - testprep parameter settings is not retained, what could be the cause..! B% J A- x, t+ e. q
1176791 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl. u' ~' O7 t8 j$ l# U
1178052 ALLEGRO_EDITOR SHAPE SIP crashes during shape degassing.
# ^; q2 R$ o! S; g0 y* K- j1178158 ALLEGRO_EDITOR INTERFACES Export step file creates step file of same height
c9 v0 T* @9 f1178201 ALLEGRO_EDITOR GRAPHICS Large oval pads rendered as oblong hexagons in the 3D viewer
5 Z3 r& |# k/ l$ ?4 B1178671 ALLEGRO_EDITOR GRAPHICS 3D Viewer in package symbol editor not displaying correct place bound shapes.
6 x# P& J) n1 T8 @$ o2 K: @3 o1178725 ALLEGRO_EDITOR OTHER With fillets present, rat lines do not point to the closest endpoint.$ l. J+ o! Q7 E& J. B
1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.1 r, i5 G X" o1 i/ a7 O
1179093 ALLEGRO_EDITOR SHAPE Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.
$ p+ u. @* ^# s T1179109 ALLEGRO_EDITOR OTHER DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version8 x$ r+ Q+ Y2 f% y0 c
1179571 ALLEGRO_EDITOR ARTWORK Artwork crash and artwork log report Aparture missing
: ^' \7 B/ [$ e0 a! L. B8 \1179636 SPECCTRA ROUTE Route Automatic will not start if NET_SHORT are attached to a mec-pin5 j& z. W' ]- \' f/ F
1179659 SIP_LAYOUT DIE_EDITOR die edit on co-design die losing c4 bumps
. i9 J* J& z2 D( p0 S4 d1180306 ALLEGRO_EDITOR ARTWORK When trying to create Artwork the tool crashes with no error messages just a little X box' ]& @/ d; K0 \+ O. [7 {0 h
1180573 ALLEGRO_EDITOR ARTWORK If one layer has warning, all artwork films are "created with warning".% L" `( C3 E' i* T5 m* @
1180960 SIP_LAYOUT PLACEMENT swap function is not swapping logical paths in sip layout!3 W' ?& D: |* K% F$ P
1182534 ALLEGRO_EDITOR SKILL axlLayerPrioritySet() not working with v166 s013 and up5 D, r) G/ c/ L$ S' \2 N! n& r
1182560 ALLEGRO_EDITOR PLOTTING Creating plot 2nd time casues Allegro to crash8 w8 _) a( j5 |
1182616 ALLEGRO_EDITOR PLACEMENT Application crashes when attempting to place a high pin count BGA
) G: `7 H. @1 F, A4 s7 z1183752 CONCEPT_HDL CORE Unable to modify location properties within a read-only hierarchical block
8 N, d/ W) i0 g. n% N3 P1183774 SIP_LAYOUT DIE_EDITOR Die Refresh hangs1 x. ^/ \; Q8 Q2 m6 U$ t, x
1184178 CONCEPT_HDL CONSTRAINT_MGR Ecset xnet members lost from electrical class when restore from definition of subblocks4 B* ?+ Y# {8 z ^- |+ O' y3 L. N" |
1184787 ALLEGRO_EDITOR EDIT_ETCH Allegro SPB166 s 015 crashes during normal add connect function.
. o4 v" P9 n+ m# Z, f
+ w {+ U1 f$ @6 \! iDATE: 08-22-2013 HOTFIX VERSION: 0152 n, L+ ]) q2 u5 J. [: ^% x" m
===================================================================================================================================4 i( @" V& i. g6 F
CCRID PRODUCT PRODUCTLEVEL2 TITLE
* |0 o/ Z. j% d: _3 H) Z===================================================================================================================================6 k a# ^/ F2 U0 T
1156102 PCB_LIBRARIAN CORE PDV severe performance degradation on Linux platform makes PDV counter productive after some time
# S; L1 I2 z, b- G5 L- [1165756 CONCEPT_HDL CORE DE HDL 16.6 adding ASCII character to properties
. m# @/ o& A' I4 N! {5 ~1 S% u1169896 ADW LRM Library Revision Manager makes updates but the interface never returns to the user
' L; E2 e" f+ u- @' z8 ~" z1170635 SIP_LAYOUT WIZARDS BGA PIN NAME doesn't sync with PIN Number) d" m7 l: q6 _/ b e% v i
1171061 ALLEGRO_EDITOR PLACEMENT Place Replicate Apply cannot place module
( d, w7 }5 `4 s/ ^" r$ {! V' ^# j1171415 CONCEPT_HDL CORE Mismatch in the interface ports in design bw_hybrid for block a38410_scsp
! F' ]- B* _5 n3 i1171598 APD WIREBOND Cannot load xml over 65 profiles defined in file.
" c6 M U( `5 R9 q; o1171713 ADW LRM Blank lines appear in the LRM - RM-Clicking causes LRM to crash( ^& P- K% y9 X
1172576 SIP_LAYOUT IMPORT_DATA AIF import fails with Error: symbol is missing refdes( _. X# Y. }$ k- M
1172938 ALLEGRO_EDITOR PLOTTING Export IPF probrem
! f* x1 v3 K2 b/ W+ f) u1173190 ALLEGRO_EDITOR ARTWORK Not able to Add/ Replace film_setup.txt file in Artwork control file.
9 v. w; h6 Y6 J1173750 ALLEGRO_EDITOR REPORTS SIP tool crash when clicking report "Net Loop Report"5 D6 h+ {8 \, h4 Q4 a
1175582 ALLEGRO_EDITOR SKILL axlDBCreateFilmRec error undifined function" S3 ~: [5 @+ h' ?6 J9 A8 [
' g& r4 m+ O* B* |& B0 D
DATE: 08-9-2013 HOTFIX VERSION: 0142 X, f. [2 m! N9 {, X( `3 K! Q/ G
===================================================================================================================================
3 t$ K" v2 l9 T+ iCCRID PRODUCT PRODUCTLEVEL2 TITLE b7 a7 c2 y9 x+ R: m* [! u, i
===================================================================================================================================! Y3 B5 a" x5 E( D( f* A _- |
1155569 APD MODULES P1_U1 and P1_U3 Die pins are missing after Place Module.
- X& K+ x) _6 c8 @6 \" c1158528 CONCEPT_HDL OTHER Dual Monitor issue: Retain Hard Packaging option is missing and attribute test distorted: K+ \9 h5 r/ |8 A
1160968 ALLEGRO_EDITOR SKILL Text Subclass change difference in Edit > Change and axlChangeLayer Skill command0 t( Z% q5 j; t
1161986 SIG_INTEGRITY SIMULATION Flatline waveform seen when via model is set to detailed closed form or analytical solution
* m5 c: u$ }# Q+ F1162323 SIP_LAYOUT DIE_EDITOR Die Editor is incorrectly leaving an unassigned function pin in the die during refresh from die abstract# T6 s# U" ^4 v, p/ x
1162752 ALLEGRO_EDITOR SKILL axlDBChangeText doesnt recognize ?layer as a valid argument as documented
& P2 G5 @; X' ?- E1165002 GRE CORE GRE Crashes during Plan Spatial giving "Memory Allocation Failure" Error.
+ W+ O0 F: N; T9 T5 r1165469 CONCEPT_HDL CORE Import Design loses design library name/ Z( q' S6 a/ v) ~
1165708 ALLEGRO_EDITOR TESTPREP Test point router failing when attempting to insert new TP via's" ?" [. F" P( l/ u/ Q
1165801 CONCEPT_HDL PDF Pin texts of spun symbol overlap in publish PDF.- b9 R6 H* t- S) [, s7 c
1166020 SIP_LAYOUT WIREBOND Bondpads created with shapes do not follow the orthogonal pattern when adding wirebonds.0 i" i: b6 l% R( U* I
1166371 ALLEGRO_EDITOR DATABASE File locked for writing in 16.5 cannot be unlocked in 16.68 U& w! O5 l1 ?* h" W' c8 G
1166482 ALLEGRO_EDITOR INTERFACES Step orientation for y-rotated component is not exported correctly.
* _% w6 ?# W1 `7 N8 `/ V1 x$ ?1167519 ALLEGRO_EDITOR DATABASE Uprev dbdoctor does not log warnings about renaming properties.
5 K9 |8 B- x$ o/ ]6 O# o; b' [7 Q1167588 SIP_LAYOUT DIE_ABSTRACT_IF do not create a new pad stack for each I/O pad2 u# O0 R! L; t' L. j2 {1 X( A
1168496 ALLEGRO_EDITOR SCHEM_FTB Export Physical Crashes when netreving the board4 r5 b" @% \- ]( m, a; V) ^1 P6 |8 J
1169510 SIP_LAYOUT WIZARDS Netlist in Wizard is crashing with this text file where the Net Name for one of the assignments is blank, meaning dummy
) Y% \0 |0 n# u3 u6 R1169593 CONCEPT_HDL PDF Published PDF file's hyperlinks do not work fine when user click 1D10 or 2A10.
$ s3 Y& U8 {; w3 i1169984 F2B PACKAGERXL Error Mapping cset when packaging but not in CM Audit
: I2 c, |$ q& e: Y/ \" \, a1171008 SIP_LAYOUT OTHER SiP Layout - Beta feature Void Adjacent Layer Shapes - changes or modifies "priority" of other/all shapes$ P }& ^/ p" ?$ H; g3 p4 b4 s
1171411 ALLEGRO_EDITOR OTHER Enh - Break in Step 3D view in latest hotfix v16.6s0135 N5 ?2 V& T2 r0 ^6 ]* D9 x. _0 ?! ?
5 N/ a" L+ I' S0 N
DATE: 07-26-2013 HOTFIX VERSION: 0130 ]; P: i! G# x; Y$ O. E
===================================================================================================================================
- s+ P8 I$ v& k+ {3 C$ v- |: rCCRID PRODUCT PRODUCTLEVEL2 TITLE
. e7 T4 b8 l9 |' w. u0 z. R===================================================================================================================================
7 K4 h) b+ e3 g111368 CAPTURE CORRUPT_DESIGN Capture - will not produce allegro netlist with 10.06 C% v8 s; H- V9 `, V, Q
134439 PD-COMPILE USERDATA caCell terminals should be top-level terminals% O$ y9 ~, g5 P9 z7 }) v- [
186074 CIS EXPLORER refresh symbols from lib requires you to close CIS1 T: k8 Y$ ~# v9 L o$ Y3 h/ D
583221 CAPTURE SCHEMATIC_EDITOR Option to have the Schematic Page Name as a Property in the Titleblock6 s- C& ?# @8 F$ Z5 o" e+ ~
591140 CONCEPT_HDL OTHER Scale overall output size in PublishPDF from command line% ^; s1 j* l/ j
801901 CONCEPT_HDL CORE Concept Menus use the same key "R" for the Wire and RF-PCB menus
3 B6 W% c' |! V) c813614 APD DRC_CONSTRAINTS With Fillets present the "cline to shape" spacing is wrong.2 N0 Z) w% }3 @9 ?( n
881796 ALLEGRO_EDITOR GRAPHICS Enhancement request for Panning with Middle Mouse Button
' P! v1 S/ p" K887191 CONCEPT_HDL CORE Cannot add/edit the locked property/ e- V$ w! X) l# `3 S$ H
911292 CONCEPT_HDL CORE Property command on editing symbol attaches property to ORIGIN immediately) [1 ]7 `- `. Z4 I( T: P$ {
987766 APD SHAPE Void all command gets result as no voids being generated on specific env.
2 F5 k# R7 D- e+ X; k. r1001395 SIP_LAYOUT ASSY_RULE_CHECK Shape Minimum void check reports lots of DRCs which are not necessary to check out., i0 d% w% b3 r/ n* ~
1030696 ALLEGRO_EDITOR INTERACTIV Enh - Allow another behavior of PAN movement using middle mouse in Allegro+ d/ V, l$ o- I% i. J% i i C# O- T; L
1043856 ADW TDA Diff between TDO and DE-HDL Hierarchy Viewer is confusing to the user0 v- g" z* @1 C8 n
1046440 ADW PCBCACHE ADW: ImportSheet is not caching libraries under flatlib/model_sym when the source design is not an ADW project
. b; m1 F3 ?& _. _# e; f1077552 F2B PACKAGERXL Diff Pairs get removed when packing with backannotation turned on' Q# Q- l( F, P5 S
1079538 F2B PACKAGERXL Ability to block all 縮ingle noded nets� to the board while packaging.
4 V* q/ e$ y" _7 ?4 J. L; i# F1086362 ALLEGRO_EDITOR SHAPE Enhancement request to autovoid a via if shape cannot cover the center of the via.
3 K8 ^3 g3 H t0 s! [3 t Z- d1087958 PSPICE MODELEDITOR Is there any limitation for pin name definition?
6 y! I4 H6 z, ?1 K; `+ x1087967 CIS UPDATE_PART_STAT Update part status window shows incorrect differences; s. Z( h/ k+ n* [" ]3 P: j& _
1090693 ADW LRM LRM auto_load_instances does not gray out Load instances Button% Q) i$ X" ~# N
1097246 CONCEPT_HDL CORE ConceptHDL - assign hotkeys to alpha-numerical keys7 V1 F2 D* P, u% s C! R
1099773 CONCEPT_HDL CORE DE HDL goes into recursive loop if a custom text locked at site level is deleted from Tools > Option3 @* Z; ?: S8 k& W1 E
1100945 SCM SCHGEN SCM generated DE-HDL has $PN placement issue
) W5 X& a& o1 ~4 o2 e: S ?1100951 PSPICE SIMULATOR Increasing the resolution of fourier transform results in out file
A: U7 o8 k) |1103117 RF_PCB FE_IFF_IMPORT Enh- Allow the Allegro_Discrete_Library_to_ADS_Library_Translator to output in its original unit+ e# j* z! d/ `& c/ H! K
1105473 PSPICE PROBE Getting error messages while running bias point analysis.+ `0 C J" q' Z+ Q3 f3 x
1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.0 d7 r6 u; H! X+ L6 F# H) H
1106298 ALLEGRO_EDITOR INTERACTIV Copy Shape uses last menu pick location as origin and not the Symbol Origin as specified in Options.
& m. I2 F) w( Z% S( C1106626 CONCEPT_HDL CORE Concept HDL crashes when saving pages
) l6 ?1 \ P% ~# R7 r% Y- ^1107086 ALLEGRO_EDITOR INTERACTIV manual void with arc's goes in wrong direction during arc creation
, t, ^5 |( @5 V' U' M- B6 h1107172 CONCEPT_HDL OTHER Project Manager Packager does not report errors on missing symbol
! P( H" f4 v- Q$ P! X1108193 CONCEPT_HDL CORE Using the left/right keys do not move the cursor within the text you're editing
: t V+ y! _: e) W2 S& T* Z [1108603 PCB_LIBRARIAN VERIFICATION PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm! c) I* G8 U+ S1 ]. m( X- K: f0 c c# j
1109024 CIS OTHER orcad performance issue from Asus.
/ M" R3 g- Y) s) A0 ~1109109 CAPTURE NETLIST_ALLEGRO B1: Netlist missing pins when Pack_short property pins connected" A" g! b' Z& o7 F- \
1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerber lines for fillet.* u2 x- `+ _- i( o9 c6 h' k
1109647 SIP_LAYOUT DEGASSING Shape degassing command enhancement - control over what layers are counted in even/odd layer sets.
" L, g! g# H0 ^2 m/ f/ ?$ Q1109926 CONCEPT_HDL CORE viewing a design disables console window) ^% e7 P! i) i
1110194 SIP_LAYOUT WIREBOND If OpenGL settings for display of dynamic net names is enabled, should be visible while push/shove wirebonds., _9 z2 e# Z( `6 Z" f6 z- o
1112357 SIP_LAYOUT WIREBOND wirebond command crashes the application) Q* L& v$ F! {5 X" J' L3 t
1112395 CONCEPT_HDL CORE 縗BASE\G� for global signal is not obeyed after upreving the design to 1650.
" ]( S7 L2 N; c7 C1112658 CAPTURE PROPERTY_EDITOR Changing Part 縂raphic� value from property Editor Changes Occ refdes values to instance' I) _1 S) B: o3 \: H
1112662 CAPTURE PROJECT_MANAGER Capture crashes after moving the library file and then doing Edit> Cut' |$ a8 ~- ]( T5 T( v
1113177 PCB_LIBRARIAN CORE Pin Shapes are not getting imported properly- w' H9 I3 Y( e3 c, ?
1113380 ALLEGRO_EDITOR INTERACTIV Change layer to - option for package type .dra is not available in 16.6 release
; f& w9 @' Z; O; |; m7 {1113656 SIP_LAYOUT WIREBOND Enable Change characteristic to work without unfixing its Tack point.: E2 c1 _# n x0 e' p& L# M
1113838 SIP_LAYOUT DIE_ABSTRACT_IF probe pins defined in XDA die abstract file are added with wrong location
% l4 _* N" {1 {" |+ i8 I0 q2 U1113991 CAPTURE GENERAL Save Project As is not working if destination is a linux machine, G4 o6 j# ]3 ]6 d' N
1114073 APD DRC_CONSTRAINTS Shape voiding differently if there are Fillets present in the design.
# V" K7 l" W S2 \% \3 O1114241 CAPTURE SCHEMATIC_EDITOR Port not retaining assigned color, when moved on the schematic: e6 e& x7 R: m9 _3 H
1114442 PSPICE PROBE Getting Internal error - Overflow Convert with marching waveform on0 @3 \1 F1 ?: E% }8 m
1114630 CONCEPT_HDL ARCHIVER Archcore fails because the project directory on Linux has a space in the name
, N' c T% ?4 C1114689 CONCEPT_HDL CORE Unknown project directive : text_editor
8 t+ V" O$ m$ m1114928 F2B PACKAGERXL 縀rror (SPCODD - 5) while Export Physical even after change pin from A<0> to A
% J; }; P* X/ S" t% m8 }1 D' s1116886 CONCEPT_HDL CORE Crefer hyperlinks do not work fine when user use double digits partitions for page Border.
' [) T2 j) k+ V C5 a1118088 ALLEGRO_EDITOR EDIT_ETCH Should Plan accurate and Optimize be removed in 16.6?
w6 j" S( \% N' ?% l* V1118734 APD EDIT_ETCH Multiline routing with Clines on Null Net cannot route in downward direction
2 E5 U! x: G6 j$ F7 Z3 i1118756 ALLEGRO_EDITOR SHAPE Shape clearance parameter oversize values getting applied to Keepouts5 ?( u: A; u( j0 s9 e
1119606 CONCEPT_HDL MARKERS Filtering two or more words in Filter dialog box3 k$ b( d+ Y5 x( f
1119707 CONCEPT_HDL CORE Genview does not use site colors when gen sch from block symbol- R/ v/ ]& K: K, e
1119711 F2B DESIGNSYNC Design Differences show Net Differences wrongly' y; p Y; n' v# w! I, H
1120659 CAPTURE PROJECT_MANAGER "Save project as" does not support some of Nordic characters.1 u$ t9 C! f, K( b
1120660 CONCEPT_HDL CORE Save hierarchy saves pages for deleted blocks.
% D- k0 D! U6 i6 _1120817 SIP_LAYOUT SYMB_EDIT_APPMOD Rotate Pads commands not working while in the Symbol Edit App. mode: `8 p) F$ d/ c
1120985 PSPICE MODELEDITOR Unable to import attached IBIS model# R9 } H9 l% i( Z: _/ ^
1121171 CONCEPT_HDL CREFER PNN and correct property values not annotated on the Cref flat schematic' d i5 D5 \3 A$ _0 ~7 G% E0 P
1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.
# m T/ @5 q% S' H& [; s( U1121382 ALLEGRO_EDITOR INTERACTIV Undo command is limited to two for this design. L+ Q4 Z( P3 ^0 N
1121540 F2B PACKAGERXL pxl.chg keeps deleting and adding changes on subsequent packager runs
% W; y8 B/ F& U& _1121558 ALLEGRO_EDITOR MODULES Unrouted net and unrouted connection when module is placed of completely routed board file.
2 M' }. p1 [. k/ {/ c. r3 }1121585 ALLEGRO_EDITOR OTHER Drill Hole to Shape Same Net Spacing with Dynamic Shapes shows wrong result.& \% F, p, w6 d6 K: k6 ?: R
1121651 CAPTURE SCHEMATIC_EDITOR "PCB editor select" menu option is missing2 @, \; J U0 z2 U j% X4 V
1122136 SIP_LAYOUT PLACEMENT Moving a component results in the components outline going to bottom side of the design.
( A( g' s$ }4 i1122340 CAPTURE NETLIST_ALLEGRO Cross probe of net within a bus makes Capture to hang.$ S0 {# J' U, R
1122489 CONCEPT_HDL OTHER Save _Hierarchy causing baseline to brd files
: `: f7 S: f* C' |1 h& O$ I. K, v% ^1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically( ^3 R! p& N9 R/ L# L8 E7 r# X) a: |
1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one
& q% F' {0 M; t# X3 F# |1123150 CONCEPT_HDL CORE property on y axis in symbol view was moved by visibility change to None.
. X& f) D7 |6 O' i! G' w: W6 u8 X1123176 ALLEGRO_EDITOR UI_FORMS Negative values for pop-up location is not retained with multiple monitors (more than 2)
- Z5 \8 G/ A7 N' ?$ g0 X F) |& N1123815 ALLEGRO_EDITOR GRAPHICS Embedded netname changes to a different netname
2 I+ I! X7 X) T1124369 ALLEGRO_EDITOR INTERACTIV Sliding a shape using iy coordinate does not work indepedent of grid.
5 w$ T2 l5 ~0 S1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5) l( s9 x1 _* }+ C p3 `
1124570 APD IMPORT_DATA When importing Stream adding the option to change the point
3 h% p' Z' b1 \, x b" `1125201 CONCEPT_HDL CORE Connectivity edits in NEW block not saved( lost) if block is created using block add
+ v1 P) q6 j# k1 g3 n+ ], y1125314 ALLEGRO_EDITOR INTERACTIV Enved crash during setting of library paths in user preference
8 }' x: L, `1 h( R3 K' T4 Q1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux/ e" P, A. w* p* R! C
1125628 CONCEPT_HDL CORE Crash on doing save hierarchy0 E3 j* f! p- p! @( D
1130555 APD WIREBOND Wirebond Import should connect to pins of the die specified on the UI., K, X) }' j$ e' Q7 o, H6 s9 @) Q
1131030 PSPICE ENVIRONMENT Unregistered icon of Simulation setting in taskbar
& \8 s" F! ~. C1 d2 L1131083 ALLEGRO_EDITOR INTERACTIV Bug: 16.6 crash in changing the mode in Find filter window/ |9 l) x% }( O; O |. i( X
1131226 ALLEGRO_EDITOR PLACEMENT When Angle is set in design parameters while placement component is rotated but outline is not.# _1 A# b" O- p; [) S0 B2 u5 ]
1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.1 N1 f3 r5 [: H4 u5 l' ~) i9 P
1131699 PSPICE PROBE Probe window crash on trying to view simulation message7 P( c+ C0 d: w; h% Y( M& n x
1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.
+ s+ o" Z5 A& r7 [8 M1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.6 Y1 b: l8 |: @. X8 s$ i5 ^
1132698 ALLEGRO_EDITOR EDIT_ETCH Slide Via with Segment option with new Slide command* F& T' \5 u- f, ~! z4 t* f
1132964 ALLEGRO_EDITOR SHAPE Same net "B&B via to shape" errors created when adding shape
8 m2 s/ s5 ~: i+ O( E$ \) |# \1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top
2 j4 t& S: \4 a- K7 {1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.
; x7 l. r% t2 i. r1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property
) M: W/ x X: b1135118 ALLEGRO_EDITOR INTERACTIV Mirror and other editing commands are missing for testpoint label text in general edit mode.
7 p/ N# [2 A& S C2 [% s% Q1136420 CAPTURE GENERAL Registration issue when CDSROOT has a space in its path
/ k- R/ Y; u4 r' j5 d1136808 PSPICE STABILITY Pspice crash marker server has quite unexpectedly
' a! k' Q, u/ I- Z6 L8 w1 U, ~- o1136840 CAPTURE SCHEMATICS Enh: Alignment of text placed on schematic page
: f- z& M0 t. b- J4 S1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs
x" a3 _1 ]9 w, C$ {5 e9 v1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness+ r; f1 x4 [. h) K
1140819 APD GRAPHICS Bbvia does not retain temp highlight color on all layers when selected.0 h& d6 e5 L. D
1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped
7 Y6 x4 \8 D8 i% g; f1141723 ADW PURGE purge command crashes with an MFC application failure message, K) F3 X4 P, d6 } g/ D4 ~2 y
1143448 CAPTURE GENERAL About copy & paste to Powerpoint from CIS- a7 R* T7 N- k% N) L- {, ]! }% u$ B2 g
1143670 SIP_LAYOUT OTHER Cross Probing between SiP and DEHDL not working in 16.6 release
* p, s1 C/ n# |" g; N1143902 ALLEGRO_EDITOR DATABASE when the shape is rotated 45 degrees the void is moved.4 l8 v+ U+ c) V# R
1144990 PCB_LIBRARIAN CORE PDV expand & collapse vector pins resizes symbol outline to maximum height$ T# a- b: v! x n
1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed6 Y7 B, ?4 r; N2 `( G
1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case& d4 B7 C* h" H$ _1 h: R/ ?" H2 {
1146386 ALLEGRO_EDITOR INTERACTIV Place Replicate Create add Static shape with Fillet shape- K% Y' \$ S- R' h, G# D' G: B1 }% c- [
1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail
4 B! V$ h7 t" W2 t. L" @# M1146783 ALLEGRO_EDITOR INTERFACES Highlighted component is missing from exported IPF file.
. V' |6 d( n+ K! W1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block
9 n) {5 |& M; k. N- x1148337 CAPTURE ANNOTATE Checking "refdes control" is not giving the proper annotation result) T `/ ]( ` g4 N( t
1148633 SIP_LAYOUT INTERACTIVE Add "%" to the optical shrink option in the co-design die and compose symbol placement forms2 s( v* [# w8 N* {
1149778 CAPTURE SCHEMATICS Rotation of pspice marker before placement is not appropriate3 k% X1 a4 c, c- O3 `
1149987 PCB_LIBRARIAN PTF_EDITOR Save As pushing the part name suffix into vendor_part_number value
( n+ Z/ @2 G- D* f: p) i+ F+ D0 z1151748 ALLEGRO_EDITOR OTHER If the pad and cline are the same width don't report a missing Dynamic Fillet.2 V1 k- M, t# X
1152206 CONCEPT_HDL CORE ROOM Property value changes when saving another Page
% [* g9 l% v5 p3 D1152755 CONCEPT_HDL COPY_PROJECT Copy project hangs if library or design name has an underscore5 b/ v; E/ Y" B- _5 P" K
1152769 PSPICE ENCRYPTION Unable to simulate Encrypted Models in 16.6
- _. e' D @5 j" E1 L' I1153308 ALLEGRO_EDITOR DRC_CONSTR Creating Artwork Getting Warning "DRC is out of Date" even when DRC is up to date$ J# o) }2 R* f
1153893 F2B DESIGNVARI 16.6 Variant Editor not supporting - in name
/ `3 E' X/ Q" @9 P3 H0 ]+ V3 Y3 z/ f1154185 SIG_INTEGRITY SIGNOISE Signoise didn't do the Rise edge time adjustment.
0 S+ I! F* [. k0 O9 V+ {1 F, C* f1154860 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend! ?5 d( W( T0 q1 h: r+ \5 n; ?
1155167 ALLEGRO_EDITOR EDIT_ETCH Via structure placed in Create Fanout has incorrect rotation.
( _2 q) w& ^/ j/ V9 d" @1155728 CONCEPT_HDL CORE Unable to uprev packaged 16.3 design in 16.5 due to memory
5 g1 G% C- ]8 [4 I" P3 c1155855 SCM SCHGEN A newly user-defined net property is not transferred from SCM to DEHDL in Preserved Mode8 f9 U, j5 l! j! U
1156274 ALLEGRO_EDITOR INTERFACES Exported Step file from Allegro is wrong
+ ?% Q: Z2 P/ _! a: ?1156316 CONSTRAINT_MGR OTHER Break in functionality while creation of pin-pairs under Xnet in Constraint Manager, E& I/ R+ ?/ y' U1 m; s3 F% d8 s. m
1156351 CONCEPT_HDL CONSTRAINT_MGR Loose members in Physical Net Class between DEHDL and Allegro7 \( c% d. {- d% c, N
1156547 ALLEGRO_EDITOR DRC_CONSTR Etch Turn under SMD pin rule check through pin Etch makes confused.
* }# m( O8 X/ y, p0 [( b" D& L2 y1156779 CONSTRAINT_MGR OTHER Electrical Cset References in CM not working correctly
8 G) J1 y5 b4 w9 w6 z1 f5 _1157167 ALLEGRO_EDITOR SKILL axlPolyFromDB with ?line2poly is broken
% `$ A& p) y4 ~, I7 v1158042 ALLEGRO_EDITOR DFA DFA_DLG writes the dra file name in uppercase.
6 Z% a% T! A1 b1158718 CONCEPT_HDL CHECKPLUS Customer could not get $PN property values on logical rule of CheckPlus16.6." R4 u- C# ?/ Y$ P$ a4 x' ?
1158970 ALLEGRO_EDITOR SCHEM_FTB Changing LOCATION to $LOCATION in DEHDL does not update the .brd file
. T3 Q( q( I' `$ y6 p) T. H1158989 ALLEGRO_EDITOR INTERFACES pdf_out -l creates a PDF' n& v1 K- t/ y. h3 d" x# x
1159285 APD DXF_IF DXF_OUT fails; some figures are not exported
! k! c2 @8 w+ H2 s! V7 x; Y% ?- K1 Y+ Z1159432 ALLEGRO_EDITOR SHOW_ELEM http:// in the Show Element in 166 do not have HTML link to open the Website
7 U3 U" ~, Q5 q8 s: L1159483 PCB_LIBRARIAN SETUP part developer crashing with
) y# M2 `4 S% Y& a9 Z; _1159516 ALLEGRO_EDITOR EDIT_ETCH Unable to slide cline segment with new slide.* i4 g" a6 m2 O, R8 ~. }! T
1159959 ALLEGRO_EDITOR GRAPHICS 3D viewer displays clines arcs incorrectly% \7 |# @# B, I3 [* |
1160004 SCM UI The RMB->Paste does not insert signal names.
) l7 K) h; Q" _1 a) u2 d1160410 ALLEGRO_EDITOR DATABASE Lock databse with View Lock option is misleading: R+ p. @! L5 r0 J
1160529 SCM SCHGEN Schematic generation stopped because the tool was unable to create an appropriate internal symbol structure# f9 q9 D% z% _+ g7 ? H
1160537 SPIF OTHER Cannot start PCB Router+ E# c& c) c5 Y% n, J G2 r# r
1161363 ALLEGRO_EDITOR SYMBOL Getting error SPMHGE-73 when trying to mirror symbol6 D: v3 n1 B- Z6 t
1161781 CONSTRAINT_MGR CONCEPT_HDL SigXp crash when selecting ECset in design
0 H! j' n2 {2 ?$ `8 w1161896 ALLEGRO_EDITOR DRAFTING Tolerance value added for Dimensions is not working correctly (HF11-12)
" K# R: W& n" p2 ~# s1162193 SIP_LAYOUT DIE_ABSTRACT_IF shapes in dia file not linked to the die after edit co-design die& O+ `' K8 v3 w5 m. J0 K
1162754 APD VIA_STRUCTURE Replace Via Structure command selecting dummy nets./ j! o5 h8 W% M/ h0 P
- w0 }, l% ]3 a
DATE: 06-28-2013 HOTFIX VERSION: 012
1 h/ G4 o$ s4 j+ i3 l! v9 N===================================================================================================================================0 j* Z5 G! u' p" {* V; D* u3 W
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 _' L2 u) W J3 D# @- e9 g* D===================================================================================================================================
& W( b% Y9 ~: s/ [9 N914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD5 ^! ^. Y5 C% ]2 n- B
1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files y. w: o4 `* Z2 d
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
: P) n/ C) A+ k6 s8 C& F2 T1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.5 B4 ?! n2 }- p' V; X7 N1 ^# J
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line4 M' d1 e# @) r6 D) U1 O* D
1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command./ Z/ D& I5 |! w* y( ]
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.
! c: r, u6 k3 z1151458 GRE CORE GRE crashes on Plan Spatial
( p" Q" [! p: e, f1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy8 T) k4 _& p: w
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]! L s7 [" v( e' g
1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design
3 k+ V% w3 i. M6 H- [: F3 ]1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger
# N* X" _8 S1 v8 O2 ?( h" C1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6. v" y9 O/ Q' E6 Z* e
1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places
+ s3 {6 P9 S4 J0 g. h1 B0 Q1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
! c# G; x0 @' O8 N1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.
! O* c1 c( F+ r* y1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer
# {: v1 y& j% }7 M1 ~9 b8 o9 p) I2 Q a- Z S& U
DATE: 06-14-2013 HOTFIX VERSION: 011
4 V' [- y* M2 L* u2 y! ]===================================================================================================================================7 w$ @$ ]3 I1 C! D6 y
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 J2 j) T# L# U& S; }===================================================================================================================================0 A8 M! [ b, o! s- i, h: a
982306 CONCEPT_HDL OTHER When plotting a PDF publisher output the page coming out half inch bigger in pdf3 O6 E" ]- Y; A- X5 g
1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers
' @* O: V) P7 p% \1093375 ALLEGRO_EDITOR PLACEMENT Align Module with Zero spacing value space the modules further away the modules should be nearer
; _3 v/ Z4 Y4 i H0 ?' k1103201 RF_PCB FE_IFF_IMPORT Wrong permissions to map file during IFF import# {+ e4 S& l& U2 X
1106900 CONCEPT_HDL COMP_BROWSER Component Browser performance utility should honor CPM directives for include and exclude PPT
3 h4 o# |1 ?$ L. l( B; q1110178 ALLEGRO_EDITOR EDIT_ETCH Line Width Retention should be controlled via setting% f+ t% n/ C: f- o+ q
1110323 APD DXF_IF DXF out is offsetting square discrete pads.
. X- T5 ?6 }# p' X: B- t1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board* M2 J- D0 D) D5 n
1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.+ P8 p/ u& Q1 R9 J a8 g
1139338 ALLEGRO_EDITOR DRC_CONSTR The total etch length does not seem to work for Xnets after setting the variable "retain_electrical_constraints_on_nets"9 x- u) C/ V% u) S' M
1139361 ALLEGRO_EDITOR DRAFTING Angular dimension tolerance is incorrect when plus minus tolerances are equal.
+ }4 ^' [8 _, t% X4 P& l' p1141882 ALLEGRO_EDITOR EDIT_ETCH Allegro Crashes during diffpair slide
1 G1 F/ S: ~: T( q7 n0 `1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero
$ d" L7 J* D* V" N6 k1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP
" V! K$ W7 j m# {4 O& ~. \1145243 ALLEGRO_EDITOR NC Duplicate drills found in the NC Drill output! X- H% ]. _& m: _3 ~
1145260 SIP_LAYOUT DIE_EDITOR Enable "Copy" in die editor$ z0 H: A9 H8 m8 N0 K+ M# \3 e
1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL P6 @6 [ s; X+ B/ j X2 c
1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.
; z" y& W! M' X% W1 m1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added0 x: r6 `, S. H3 o& F' ^' q4 V
1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps! Z% a1 G2 F9 g; c2 H ]
1146865 ALLEGRO_EDITOR DATABASE Allegro crashes when trying to place mechanical symbol$ y, D% e- D9 ~9 r
1148513 ALLEGRO_EDITOR OTHER Importing a subdrawing file causes incorrect net name assignment.
+ M1 S* }9 z& ]9 _/ G1148734 CONCEPT_HDL OTHER Logical Symbol Text is turned upside down after extracting PDF by Publish PDF
) C7 b5 x9 y1 w5 P0 x5 D2 c2 J1149025 ALLEGRO_EDITOR INTERFACES IPC-2581 imports cross-hatched shapes as solid
9 @* ^( `" S. z# H- N6 h1 F6 G; }1149948 APD OTHER Stream_out hangs on this design -- hang processing merge of overlapping shapes using poly_deletecolinear_only()
3 X4 Z2 j1 ]: K, H& L% M1150274 CONCEPT_HDL CORE Uprev from 16.3 to 16.6 is not preserving RefDes
, ^9 d3 P4 l8 ?* g6 l& Q# W: Y1151450 SIP_LAYOUT DXF_IF DXF export from CDNSIP missing symbols
- O4 _' C$ s- P( D7 R6 |) v; u3 I
DATE: 05-25-2013 HOTFIX VERSION: 010" ?# o$ `. |" b2 c8 ~
===================================================================================================================================* F% o! K. V( H' L1 ?
CCRID PRODUCT PRODUCTLEVEL2 TITLE
% m7 T: K% G& C$ x8 c===================================================================================================================================
V! B, ?4 |0 d( s1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer8 s+ k* f3 M% N% c
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border! g0 Z# f- E* {3 Z. n _* j# g6 d4 [
1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files. i. q! ~2 D. G5 I
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
; w+ j! I$ c7 z/ h9 r) d1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6
4 i5 n& E- f9 k% v- a3 c4 T1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border! n- U) c& M0 ?0 ]/ q1 B6 ?
1131775 ADW LRM LRM error with local libs & TDA" h" m9 j* i/ D5 e$ |# M6 y+ |" w
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
1 T7 h9 O6 u- n2 r1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo- f7 i! `7 B5 s" u& ^
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
; R9 T4 N0 f) f; J0 F1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur" v2 C; h2 k6 p* n
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
, o; ?* r$ P; G$ p8 y$ B2 {% S1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
, z" N5 d# }' E. q- V0 V1 Q1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor1 f7 v; Z3 e3 \& Z4 T
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro7 U2 G0 M7 x; y# w4 k6 e
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.) @" g2 U; m5 P& V2 C
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
9 C: z8 n: E( A% g1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
8 [) R3 n! K+ N a3 i" ]% M1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
/ N. h8 T+ v) I4 N R) D1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
9 s1 W$ L* o' b1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor
+ d: b p) Z! o8 R+ A5 J3 a+ F; w$ y) u- i
DATE: 05-9-2013 HOTFIX VERSION: 009 j& @, A. H$ g' J& ?$ N
===================================================================================================================================6 ~6 ?5 H; m1 z; `+ d4 [" \
CCRID PRODUCT PRODUCTLEVEL2 TITLE: }( H$ y" z! v, t
===================================================================================================================================
) Y. |$ l1 Z! X( @' x' [7 s7 ]961420 ALLEGRO_EDITOR PLACEMENT Regardless of the aspect ratio for room of side The QuickPlace by room command could be placed comp
/ a ~: ~& `/ I( U9 N! R1079862 ALLEGRO_EDITOR SKILL Ability to create IPC2581 layer mapping file by Allegro Skill function
* s- Z+ K% W. M0 O1080734 CONCEPT_HDL CORE Repainting of grid lines during pan or by moving window show as solid white lines instead of gray da% m' k, d6 q7 C$ @
1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB
; [; u" d4 l5 X* @& g2 Q4 Q" p1107547 SCM OTHER v15.5.1 tcl/tk code not recognised in 16.6
" g: K: D7 l: W0 V" {; F1110209 CONCEPT_HDL OTHER We can move symbols and wires off grid despite the site.cpm grid lock" F9 n& L, C; ^- K: T
1117825 CONCEPT_HDL OTHER SHOW_CONSOLE_ON_LAUNCH throws an unrecognized directive warning in the schematic editor M* m) u+ c/ S: r, ^% W5 m
1118874 ALLEGRO_EDITOR INTERFACES Oblong pad shapes are not shown with correct orientation after DXF export from Allegro
( `$ A8 X4 ~0 }2 m% @6 T1121873 ALLEGRO_EDITOR INTERFACE_DESIGN Importing Bundles from Net Groups does not allow any further editing.
; A; a' z( M, x& f& c% a/ \0 r" D1122933 CONCEPT_HDL CORE Newly added Toolbars are getting invisible after re-staring Concepthdl7 @, U3 o/ w- p' I9 o! U7 l& A
1124587 ALLEGRO_EDITOR INTERACTIV The Shape Expansion/Contraction command should also be available in EE mode.: d( I2 B7 l' P. ?% \
1125895 SIP_LAYOUT LEFDEF_IF Tool crash while moving the slider in the Filter options Macro tab form of the co-design die library manager
8 t. y) T! D1 H/ V6 v! f! {1125962 F2B DESIGNVARI Custom Text in Variant Details dialog box is inconsistent/ x* r1 A0 Q9 n; K3 ^7 u) I, @
1126096 SCM REPORTS Two nets missing in report, c5 e1 A6 q0 ^3 |1 {9 O
1126134 SIG_INTEGRITY GEOMETRY_EXTRACT Attempting to extract topology hangs APD
5 t. o( ~8 _5 _7 A8 { X$ G( c- r1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.
" M" B' H; f* l0 x% q0 j1130280 ALLEGRO_EDITOR MANUFACT stream_out command in 16.6 seems hard coded to look for a design called stream_out.brd) V6 `: w8 I' |2 c( U7 }6 e% N
1130737 F2B PACKAGERXL Error - pxl.exe has stopped working
: i6 N8 n: ]; O; T6 O1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters
/ q4 q8 v! y' v& j1131764 ALLEGRO_EDITOR EDIT_ETCH Line segment will not slide using the New Slide.
$ l6 c& I5 ~# i! j ~1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.
1 K# _) j1 o% n. U, g* y* X1133311 ALLEGRO_EDITOR SKILL ?origin switch is not working correctly with axlTransformObject while rotating shapes
# t7 v4 X* I0 {1133893 SIP_LAYOUT IMPORT_DATA netlist-In Wizard crashes
+ }5 G. n/ _/ [
6 G9 T5 h/ C0 M0 N( cDATE: 04-26-2013 HOTFIX VERSION: 0082 D! B8 S9 |) j) J; }
===================================================================================================================================
8 z% C; G; d7 @* u D. m7 UCCRID PRODUCT PRODUCTLEVEL2 TITLE' {* X% |: D8 ?9 u
===================================================================================================================================) h$ [7 I+ G9 x, D7 U
876711 ALLEGRO_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit
+ H2 F, P* q" ~* _1 _5 {, }( b1080386 CONCEPT_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation2 W6 A+ n% V8 I2 h
1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device( H& g+ f! V6 n+ ~
1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
4 a" @5 V2 Y4 d5 I5 f1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section
" p- g7 r- u2 h1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running$ l a- K" a- _( i% f
1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.
, `: t" P \5 U4 D# \5 X7 a) U1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence6 P3 j$ \$ L# t% X) C
1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.' [6 ?- X* F2 Z
1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason; Z! N( w- v/ H) C" B! t; t
1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.3 u& }! d5 [' }) \6 l8 @" ~
1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?
9 x( Z" l$ v3 O! b$ ? `5 N# C1120414 ADW LRM TDO Cache design issue
' d- J! L8 Q9 {7 Y2 P7 Q1121044 SIP_LAYOUT SKILL axlDBAssignNet returns t even when no net name is assigned to via
8 q" q9 A5 \# x3 W% b% W1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups1 q( ^& C% Q! x( @$ v, R3 h& R
1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it6 t% D" o, M- n5 ~: y) x1 @8 [
1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.
0 v; m Z( l$ C1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced
! Q$ h; u' Y/ D/ s4 g1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file. D* x9 |6 I2 I, Y9 C6 N; e
1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable1 Z1 v$ ?0 |( Q- v, C( {( i" C. \; r
1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file5 u- j, F- D4 C6 K* p
1123816 CAPTURE PART_EDITOR Movement of pin in part editor7 T% s7 M" r) S7 m: `
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 508 W9 _* ]2 ~* Z4 R4 m$ N, I/ W7 a; @
' m8 Q* w& F3 O6 z
DATE: 04-13-2013 HOTFIX VERSION: 0073 D. I2 O. y/ m9 w) U
===================================================================================================================================
4 E5 C- b# j% j/ u% F* JCCRID PRODUCT PRODUCTLEVEL2 TITLE
2 o5 `1 m9 Y/ J2 S y' N H===================================================================================================================================$ b! v! j" j( v5 x1 e2 x
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die
, x$ S7 @! z1 C2 {1 l1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6
" k7 R3 v+ m: ~1112295 APD DXF_IF Padstacks� offset Y cannot be caught by DXF.
8 T7 l4 `$ s u1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components [/ ~! D- N2 Z, }
1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
! S1 N/ V; Y& @; C: S9 L( |1115491 ALLEGRO_EDITOR SKILL telskill freezes command window0 `) h x3 a) l
1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
: j2 \# g/ z: p9 I1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.) ^9 a) S8 K2 x) d" }% e
1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear7 h- V2 J% @% V* A& c6 Q* h
1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks1 ^5 p) i% v6 W& Q& P" a' F z7 F
1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?
8 x+ n3 P$ m. k d+ {* i: \1 d( P' V1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh5 M: G6 \9 u7 U$ R# P
1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh6 D+ \- r+ b2 w! q8 h" ~& S. p/ j
1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors/ p( p d1 [; b6 _7 Y; R4 C
1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6
% n4 I- F6 K3 M8 G1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently x3 o; M3 ]) a+ J$ m" _3 F
1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps
$ D0 G/ n1 d" a1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks
+ { H* R: `' Y. c( k1 q8 l1 b4 U1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.3 k! o8 K( L% a8 s" ]
9 }' K+ a8 M" [! JDATE: 03-29-2013 HOTFIX VERSION: 006* z/ V6 \. K3 K$ c
===================================================================================================================================
2 t& p% g3 o# B4 H3 ^1 H: JCCRID PRODUCT PRODUCTLEVEL2 TITLE
# b; b8 B. | j$ @===================================================================================================================================
+ s- A8 Z+ Q" ]625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.3 y. p1 Z' r( K* ]1 F
642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep; q9 b$ u5 _) e) C* Z8 ]7 s! r
650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".8 O5 B# n1 }+ u* }4 n) R- v" o; k8 t
653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend6 t) X" R3 {$ X
687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect
( i2 G2 q' k8 p: _787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics& w+ x% V1 [0 Y, ~. G& f/ D: w' u
825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
- J. a7 V2 U; Y; u" {# s834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
) Q& I: E6 u9 M1 X$ E! e" j' q835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
, m, \" r! u, j, w4 Z' A868981 SCM SETUP SCM responds slow when trying to browse signal integrity
3 x: Y2 l' p# K: i* z871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
+ ~. t5 z8 i( Z* @873917 CONCEPT_HDL CORE Markers dialog is not refreshed
2 W: f; p, H& S! j! N887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
1 B% q6 t1 p" a( r$ @888290 APD DIE_GENERATOR Die Generation Improvement+ I6 |8 j( B' k$ M8 h: j) h. w
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
! @" W0 f0 x+ i902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice
! I/ `1 }3 A8 v908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM
( f/ Z* x9 p$ K9 G9 B- Z922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols
, ^, j( q0 q$ i. G( ?1 y4 E% Q923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences
6 m( G. A U! r8 [935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC
- x* p3 |6 O& h0 V. W3 L+ o8 O9 P( L945393 FSP OTHER group contigous pin support enhancement
9 E6 c6 [+ R7 P& T# @& v# W2 G" F969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database: U+ b0 v6 E( V; M8 p
1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes9 e1 _0 a5 y- W; P6 d: @
1005812 F2B BOM bomhdl fails on bigger SCM Projects
' f2 n; e6 j2 p7 E4 L3 O/ x6 H: {5 F1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture
. h9 J9 a$ N; u; J) ~1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names& ?2 l3 c. L. h6 x
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net
* V4 a) N; y# b( T* G7 u1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical8 O( u5 r% G1 @ Y- G) q- J, w& d- {
1032387 FSP OTHER Pointer to set Mapping file for project based library.2 H" ^7 i3 Z0 w( O1 U
1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with 縋LL PLL_3 does not exist in device instance�
6 W% ]0 s; I7 V! ?$ M$ } T4 J& U1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
& _, f0 R5 h: X/ J6 X1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding
* t& G0 R B2 {* D, L1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.
& _% k7 Y5 ]# u. V4 R/ v1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type
& j7 `% o. W7 Y7 X# e6 E1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll
8 b2 R' _" C- }1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation) A$ Z+ u# J4 R3 P# i/ v. `
1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects
$ Z( U- Z* v; I r* A1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus
; ~' V2 S) u4 @; c/ x( }+ V1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts
" y) N$ q1 m4 E, Y6 w. Z/ p9 F1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs
- I; l4 v) n2 S1065636 CONCEPT_HDL OTHER Text not visible in published pdf
$ K& F0 _1 R' B* c' t9 j1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings
% h: R/ \9 D* R3 I# K" f2 q+ t1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary% X6 j- X' n, _$ b% {% U9 H; h/ A
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts3 y: ^' N) s) @; b. T6 {
1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic
& B6 N: B( L! e2 r4 K1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down4 J' T ]; h, y( l# N1 d" k
1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45
: }# h ^4 ~7 r* K( G( M$ X1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal/ |5 \. h& F1 I" G0 } P
1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
' i7 w: @, X+ M1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.4 j* n1 V+ z' R! j# S3 E
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)* s( q( j) |" L! y6 {, m
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die4 p: D2 N( U/ {" f c$ D
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic g; c5 d: L% s0 | m, v
1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut
. }$ R6 L. f6 r8 j& e( J+ G/ d1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects5 }' {; A3 R2 b2 X3 x
1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format
+ t7 E; h8 K! y/ Q1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net( T1 y+ Y! V8 u e7 r" `
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic: M( L8 n6 W2 S3 a
1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
" o) ^0 X$ A& C' Q1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.0 R# M$ ]$ b: w3 W
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.
. R7 \$ R' X5 K3 g9 x1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors
9 H9 @& @9 @% A- A$ A1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.( k: v! [5 }9 p& L& L
1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition
2 b1 P. F N3 {( T1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor
/ o* W6 e# o! S7 d1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options6 l- P5 x; T4 @' s# s# C
1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5$ t O, B2 |" u9 ~3 j
1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.
6 u9 g' T3 Z% [! K1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate
# W9 x) S8 C# Y% m1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3
8 G- U- g" y, l- d0 o5 k2 R1078270 SCM UI Physical net is not unique or not valid
- y; ?' Z7 V. c3 t' W8 a% }1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted
+ x6 z1 T: ^& g* V. q% Z1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle
4 N: P6 M4 s! l# G. z/ t4 e1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs7 R$ L; y; {- }% _3 T+ J$ b! W9 S$ q
1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"" \5 Y9 z2 x. M6 R1 c
1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters
7 N( X3 J( f/ v1080336 CONCEPT_HDL CORE Backannotation error message ehnancement. a) X H9 I0 [* n' u
1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license
$ M4 [. N0 q$ J/ Q8 V/ S2 b: E9 O- I: e1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd$ V# K& ^, K t. J, b# F
1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error
4 i( j! u2 o1 ?& h1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.6 C9 @# `3 Q4 s: m1 Z
1081760 FSP CONFIG_SETTINGS Content of 縁PGA Input/Output Onchip termination� columns resets after update csv command
; l- O/ K* M- D1 l& i1082220 FLOWS OTHER Error SPCOCV-353( o, Y- n r) j* T. V
1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.4 W+ u9 r' ~ x6 o
1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command
' g, O2 d4 u$ o6 b1082737 CAPTURE GENERAL The 緼rea select� icon shows wrong icon in Capture canvas.
* s0 N8 d9 u$ N Q1 v1 h$ J1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name8 r9 ^" k: K7 N; K0 ]! f1 y" ? k
1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way
4 F( V4 l/ Y3 }- h. ^+ I1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher
# ?3 U; ~* C- ~; l1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI
9 `; @5 F, S5 q5 \- o( ^4 U0 i1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file% T0 l, \& H0 J4 V& G, c; H- D
1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void., N y) e$ X! z: S
1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates
7 N7 I* x6 R2 l$ h6 x8 @1 ]$ C1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters. r9 [9 }6 V9 d+ K
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.' g8 O* ~" ?* ~. n
1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results h5 [/ r! p2 ~2 q- Y
1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.6 `* y! L3 ?2 J" p
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update) P+ \, O# b! w9 {$ X. |* S; l" x
1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO% Q8 X/ z6 W2 y
1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working
3 H- f, C7 P3 c. ?4 V- |$ `* [+ _1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.1 x6 \1 L, Y* F$ E
1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design- [2 c% R) u6 P$ M3 K
1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated
+ F6 p+ o! t. U2 G1 A" m& C- H9 V1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins: L6 A7 M) E8 ~6 _
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity
% y7 e$ c) c: m; r7 l3 r1 ?1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times./ ?8 o6 r+ j5 e
1087221 CONCEPT_HDL OTHER Part manager could not update any parts.
& Y! y' d7 |) y1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space4 M% D) `/ I. |
1087295 SIP_LAYOUT EXPORT_DATA Enable "Package Overlay File for IC" for concurrent co-design dies too
# r& K6 [3 C$ b K; o' y$ H6 u1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice8 R# o' K. b$ T; ~
1088231 F2B PACKAGERXL Design fails to package in 16.5
6 p% l7 A! }+ z1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.
# ^1 H$ O" ^! V$ K# n1 j1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor
* J9 ^, b7 C+ Q& V: k0 {4 M1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager+ C: X- S# _* ]( D5 T4 ]; _8 ]
1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?
* X0 Q4 C9 e/ m: r, }4 ]1 A1089259 SCM IMPORTS Cannot import block into ASA design
7 Z6 u9 j7 e$ K5 ~3 L4 r( i$ h+ v+ C1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form
4 q: ?& o* p d2 f5 D2 `1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project
# ^* F+ t% P- n8 U+ o! @; L1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory. l( _. c+ d1 d/ o' O- r9 U. A
1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.' c/ s: X- @4 g4 _2 O
1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165
" O" r7 n0 ^* P0 a1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.
& b# M; \5 t! c g& |3 X, V1 r1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22
0 [' d/ I }/ m0 ?# N0 E$ b1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.
9 ^1 i7 r Y% @1 N3 X( n1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
, _$ f9 j/ {4 \& x9 ^1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled+ ]5 ~5 m" t3 M2 [3 j! H& y7 u8 b
1091359 CAPTURE GENERAL Toolbar Customization missing description% [6 F/ o3 u2 i: K7 E; T
1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
* o: A5 k& `8 |9 I& c1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time/ m7 K4 R$ ]3 D& `+ k V) c) N0 O6 G
1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5$ q5 M' {6 T/ A, K1 M3 M
1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design
7 t2 y6 b: G, [* ^ I1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled
1 K4 ?( N ~2 t/ k% h0 f1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters
* A! c" z s! L; \+ v1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error
9 Z( j1 \7 |4 A. y2 s# s1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder
3 w- W* ~( m3 i. |; @' R( }" e+ g% K1093327 CONCEPT_HDL OTHER Getting error SPCODD � 369 Unable to load physical part in variant editor8 x) y0 [6 T o* J
1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.! t# n& d+ j9 H8 `3 v6 w2 Y4 x: g
1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time g7 ^" G) J# E! M$ F, |% w& {
1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.( G; w: J2 k1 m
1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
! ?% i- `; v# I) N4 j+ f1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic
+ j7 z! ~) x& P6 {- c; o: t1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5
+ X9 J0 _7 `2 h" {9 G7 s: _ }1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet, G9 N0 Y7 R& o9 z
1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die. \4 _2 t& T) M: o/ G" {+ i3 o
1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block
8 {) @9 B+ d! \+ ]' r# }1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3
3 A$ R& r8 N, a- D, |$ C& N1095861 F2B BOM Using Upper-case Input produces incorrect BOM results
; c# \5 J" t8 K2 H" F f1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import
- v8 _: l/ n i7 P2 `+ ^$ e1 X1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically) I _# h9 e$ o3 q8 O! w5 Q
1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias5 }, V+ M& e! j4 P
1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate; \( p+ |6 P# k N1 J% F' j
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
% L4 v% K6 w% H# C/ v+ y1 o1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL9 s8 k4 {3 b8 {/ o9 x) w$ J0 P. G
1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.
% j) p1 |: X# i5 g# g/ `- {1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side: R K( l! P) a! ~
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command
8 d# H: ?6 s3 g6 Y0 G5 `1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
8 i- z. R9 H8 M/ G6 J4 Q# @8 y: @1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives1 ]3 _3 T/ m9 C
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork
% s- s' B" g [, L0 j1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts
. ~- |( _, r4 P/ \% K" Y1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy
6 c3 J: {! k2 w* r) X. f$ o1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.
4 M& f Y( O$ i- g s" b! A+ L6 q1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties: O. m# O: }0 h [& P; H8 T
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6
3 C( k& ]6 t6 J( c% F) X0 M1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad
: V( \/ [& A b; }; ^2 E1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
5 N( Q8 P+ e+ e4 F U3 o1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad1 u1 T6 B) H% m2 p
1103703 F2B DESIGNSYNC Toolcrash with Design Differences
8 t3 f1 P1 m; F& m. O0 \1 w5 u" b1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view
+ U% Q0 U& j4 l s" U1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6( ^% S" h+ a8 \+ K( B9 a: z
1104121 PSPICE AA_OPT 縋arameter Selection� window not showing all the components : on WinXP
/ g5 ^# o# L4 f# T3 T$ j1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly
; l5 M8 w4 V6 u5 d; f5 K; H1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM
2 Q; o) T* D" w1 e# t p/ P1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.4 n' O4 X# W% \- f+ u
1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.' w4 W6 f8 [4 E" [* u8 t3 s3 S# |7 q
1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form! f& R( R/ a/ b) |) u. y
1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part& i& P. w3 R, \1 H
1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked
0 a+ w+ {1 }9 D* u' E1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
- b2 Q% E" d$ f* U7 y1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6
' Y, F# y) E) h: Y3 z) t/ d8 }1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only4 H* u8 G+ `" T6 _) p' D4 p
1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid+ S7 W! d6 Z5 R q
1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.* z$ _6 A" B8 F' w! P
1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param
# g R& r0 d+ o0 c$ H3 ^: K1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish% b$ G5 X9 o- C# b
1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).5 {: h; [% g; T. M$ a! l0 Y! t
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke
( j a! ]" W- H* V9 N" t1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.
; H' q' |3 H g. t# P `1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode
5 p; d% y( I! ~1 w/ s4 E. M% t1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs
- @; f X$ e8 _6 R# B1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6# Y4 U+ [2 `0 L3 u/ T' T* y
1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.8 {+ |$ h) ~1 j, w
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON3 K7 @2 V* Y0 ~0 y: O. |
1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6
" c) K. D `+ @( Y7 ^% ]& ]1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset& g- w( a! B; V. D3 @& x
1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters! N% C" U$ P* @
1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
. n0 x8 E# ^& \$ T/ L+ T; g1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP
3 R5 c' A9 |: o7 U* A6 i1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint: L# A1 z' c. o7 y9 \9 g
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan
$ V6 a1 F# [, k0 ~; x% f+ F1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.4 P/ A3 ~% h. i8 R0 a8 y
1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file
) ?7 I+ w& i v3 o! |3 t; `1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6
8 R, T4 A# P+ S3 N
0 Y& W2 r& ^+ O- H2 ZDATE: 03-7-2013 HOTFIX VERSION: 005* B! D# t: d5 |+ k
===================================================================================================================================/ q/ t n: r6 r2 }' F
CCRID PRODUCT PRODUCTLEVEL2 TITLE
, K- e& I, Y" `3 Q, [===================================================================================================================================
4 d2 S1 d4 k. j( R' p/ }1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 1102
e% `! U, J* N$ M: P' M; e5 `# y1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed
0 `3 k$ _$ x8 W7 |2 N2 X$ C1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently
" ^' G+ O$ r0 c O# q, \1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind& z D* _& _* T' u5 G4 g0 y
1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view
& O6 m8 p% y1 M# C o1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed! a ~1 Q. e! Z7 F. U4 S
1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM, @, y9 Y5 b1 v! S# P/ Q+ N
1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.6( y8 U8 | T6 w1 C* c1 r& X
1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement.
) h9 x8 i# ]7 ~2 s7 H1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design
) R; F, Q% X# x8 Z# ^2 N1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in OrCAD PCB Editor Professional
9 A; b1 G$ m( i. j* x$ \! F& B7 A8 g c) J' ^ N K- |8 s
DATE: 02-22-2013 HOTFIX VERSION: 0040 D ~( {) I7 ]8 M3 y" ]
===================================================================================================================================# O! N$ V9 m+ z. [+ H
CCRID PRODUCT PRODUCTLEVEL2 TITLE
' j, {, P1 Q! p [9 W: @===================================================================================================================================* ^2 h: q' y6 I" G7 k% n5 }* b
1081026 ALLEGRO_EDITOR GRAPHICS 3D Viewer do not show the height for the embedded component correctly
2 p! [+ y6 L* M; C% H2 S1095225 ALLEGRO_EDITOR EDIT_ETCH The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing& e5 a, A5 s% R& g
1096356 ALLEGRO_EDITOR DATABASE Cannot Analyze a Matched Group in CM
+ G* ?, t+ @0 u! q% P4 L* |' d1097481 ALLEGRO_EDITOR INTERACTIV Allow replace padstack command in design partition
. F& q: K, J2 H1 Q& S% K0 d o1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend( r1 \$ J3 y4 T/ |* J
1099958 ALLEGRO_EDITOR PAD_EDITOR Library Drill Report producing an empty report
1 }( t0 ~3 M! l2 o! U- Q1100401 ALLEGRO_EDITOR OTHER Invalid switch message for "m" for a2dxf command7 J- g& f& x s) _
1101026 ALLEGRO_EDITOR OTHER utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit.& L, W0 A( J4 J
1101064 SIP_LAYOUT SHAPE 'Shape force update creates a rat- [9 T3 A/ k4 k! Y
1102798 SIP_LAYOUT OTHER Stream out puts offset pad in wrong position if pad is mirrored but not rotated.
2 P7 o+ f* `* l8 }4 I( k& e! w/ C4 C- C5 ?3 R
DATE: 02-8-2013 HOTFIX VERSION: 003
: t( R% g4 @/ u* n4 w% D===================================================================================================================================% o' i6 ~9 T- Z* C4 H ^
CCRID PRODUCT PRODUCTLEVEL2 TITLE9 w3 _- ?3 }7 I
===================================================================================================================================
& E7 _/ Q5 D/ D$ C0 e, L2 e1077728 APD EXTRACT Extracta.exe generate the incorrect result8 h X- o% I9 b3 H F4 P
1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF" W$ W' a2 Q* H+ K) a0 b7 q
1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer
; i6 z# P5 o" N9 J s, Z* N+ ~& f; m1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.
, X" }# b8 q |1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on) H9 V7 x4 b. u, ~7 }* z5 n) T* k, P5 S
1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent
- O7 o) q) P7 @+ t0 @1094788 SIP_LAYOUT WIREBOND Wirebond edit move command
, ^5 L$ n' ^$ `: T1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor0 H7 Z0 p! D' q
1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn縯 show up after 縎uppress unconnected pads� option.
3 A' @6 }8 Q0 Z# k1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff
) k% |+ ]2 V, G# m9 K- a( Z2 p1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible: B4 i# l* {! f
1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35
; z7 q/ o3 }6 B) T& o/ z ~1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.
4 x+ p5 O( d( R5 k$ M6 m+ U1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.: u% k4 U I0 V/ I2 l& c
1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.0 Z8 ^6 g! p! Q: q6 U
9 _0 F' {8 \& F$ w8 _
DATE: 1-25-2013 HOTFIX VERSION: 002
7 H, M' l8 A5 C0 P===================================================================================================================================& G3 j/ m) i! J' x8 Q4 J; L
CCRID PRODUCT PRODUCTLEVEL2 TITLE
. x6 y) I& p& y2 @+ v% D( G===================================================================================================================================
, [ A! v2 ^1 g6 u2 h& w! S491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute( U9 t9 F$ L! m- _" w/ Q
863928 ALLEGRO_EDITOR INTERACTIV Segment over void higlights false "nets with arc"
* K0 f7 }' Z& a5 T1 i% w" N* d1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes
8 R) K- F! {- Y1 N1 Z8 k$ X2 @1074820 ALLEGRO_EDITOR GRAPHICS losing infinite cursor tracking after selecting the add text command with opengl enable
- [) C3 L0 B W! D( B1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33& C* Z1 d! ]1 |. r
1076986 APD WIREBOND Wirebond Adjust Min DRC does not maintain the finger position in the same sequence
; _$ C5 T4 A" o5 g" e1078031 SIG_INTEGRITY REPORTS Requesting improvement to progress indicator for report generator" z! Q9 M6 f) e: _# F4 T
1080213 SIP_LAYOUT WIREBOND Wrong behavior of Redistribute Fingers Command
" K2 U6 t6 g! E, I# Y+ {1080667 ALLEGRO_EDITOR GRAPHICS Allegro lines with fonts not displayed correctly in 16.6
9 J, f/ h7 ^' [& d" ?: l1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note.: v8 V* f! |2 k7 M. f6 f5 |0 X# p
1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.2 }% y4 A) p0 D' o1 G3 M/ L
1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL.
0 P( C3 }6 o! l1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.05 g9 V/ o4 o6 C( g% d! ?& x! J7 Y
1082595 ALLEGRO_EDITOR COLOR Infinite cursor remains white even we change background to white( z- n# L! h) p; p
1082704 ALLEGRO_EDITOR GRAPHICS infinite cursor disappears when using Display>Measure
6 S, t( Z; C* i0 X0 P( E1082715 SIG_EXPLORER INTERACTIV Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer
5 K/ c0 _ |/ U$ q/ w! z3 Z1 q1082774 ALLEGRO_EDITOR TECHFILE Import techfile command terminates abnormally when importing a generic techfile.
7 C& b* k6 N0 ^& U* [1082820 CONSTRAINT_MGR UI_FORMS The configure generic cross-section pull downs do not work.
9 b) l' G8 u8 S2 x+ ?1083133 SIP_LAYOUT INTERACTIVE SiP will crash when using the beta Pad Rename command to change a BGA pads name.
& d8 S3 V7 I3 L T1083158 ALLEGRO_EDITOR GRAPHICS The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.62 T$ F8 A K$ G6 a1 ^ G
1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout" y) S1 ]$ t) s& |2 Z+ D+ }7 e9 W
1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file" E- }# m* ~8 u3 N
1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing.8 A' g) B, H( @8 j
1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.
# D2 r7 B9 a; w" M* m1084166 SIP_LAYOUT DIE_ABSTRACT_IF Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties2 f+ [; Q4 M4 ~- R# e0 H0 ^, V
1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error
! N$ U }. B% i1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric: j9 n8 p, I- J8 H2 O' m0 l' O
1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol.
, L4 r% J3 Z& ?! w$ j& m( a9 j1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue$ R* A4 O# _# H0 [
1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command
- [, H% T, _: o0 i8 A+ w2 P/ Y; {1085139 ALLEGRO_EDITOR GRAPHICS Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled
5 j# c- {1 f* \) J R+ Q1085187 SIP_LAYOUT INTERFACE_PLANNE netrev with overwrite constraints fatal error
% F t" r9 v1 ^! @6 ~1086402 ALLEGRO_EDITOR GRAPHICS Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled. O, E r, A6 k; I7 O5 o f
1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function% F1 C/ P8 D) S( Q+ |7 a; `- O
1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command.; ^( h5 c1 r' V7 T3 o/ \
1088412 SCM CONCEPT_IMPORT why reimport block adds _1 to the netnames?
/ J) g4 j# Z6 x. ^4 u* k" ?+ S1088958 CONSTRAINT_MGR INTERACTIV annot create Differential Pairs out of nets that belongs to a Net Group
, ?4 f k5 y) E: ~$ C# K' {0 [1089336 ALLEGRO_EDITOR GRAPHICS infinite cursor and pcb_cursor_angle
0 `7 s1 W4 F* s4 t. i+ d1090689 ADW LRM LRM: Unable to select any Row regardless of Status& a; o' A) R) k9 [2 P5 V/ h: y
1090955 ALLEGRO_EDITOR OTHER Cancel command crashes PCB Editor when add rectangle
8 ^: X3 @$ ` _' {6 v) |: O {: f5 [1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas.
+ r/ n: z1 ?6 k0 a. P8 m) J1091218 ADW LRM LRM is not worked for the block design of included project, T) [ `! T0 b |
1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads
) _% g8 M4 c, C3 q {% r$ [1091706 ALLEGRO_EDITOR EDIT_ETCH Allegro crash while routing after setting variable acon_no_impedance_width
Z% k. g) Y$ R+ S F8 m& T1 M1092916 CAPTURE OTHER Capture crash2 G0 @5 H, @6 _# R* |
1093573 ALLEGRO_EDITOR DATABASE team design opening workflow manager crashes allegro. possibly corrupt database
% E, o9 C& F9 p
) R7 M2 g$ T* ?0 I+ N% q, b7 ~ }% QDATE: 12-18-2012 HOTFIX VERSION: 0019 z% Q( h/ z3 x* W
===================================================================================================================================
8 X5 T) x# T( T) \- \0 A9 \CCRID PRODUCT PRODUCTLEVEL2 TITLE' R, n, Q( e+ N7 C2 b
===================================================================================================================================
+ P9 B. Y" j6 f$ N: c501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap, d! s6 p' {0 b- B. K+ ~( N: W
745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched
5 R: q8 Y6 ]7 S# X* n7 B- D/ l& {825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted
- u/ `3 w/ t# ~9 ?* Y# i& @871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash
$ \) `9 q! x0 v2 k* H. b891439 ALLEGRO_EDITOR INTERACTIV moving cline segments, C& t" j% ~) \ u6 W
898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore0 l) d7 U8 T) j5 x4 }
923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties3 [6 Y5 }; E8 x5 c) l2 U- J, o- _
938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
+ _' L. L4 R9 P/ U947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.3 [' { ^* o# f* k1 n
968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing- P g- d7 j. H! f, v$ u8 r
976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor: H, @3 d% ?# E! {8 ]2 @/ u
981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected., R. S! L3 q+ s w; |5 d7 F! v% Z8 [
982273 SCM OTHER Package radio button is grayed out
; r) K& y# b8 P( T3 D! n6 U988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command8 G% {# y. B, } M6 I" Y
989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode0 [' ^! A) w$ a: r+ }
993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).& O; v j6 h% S6 ?$ X- @- }
996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections4 J# t1 r& ]' t' d2 J
997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
; C5 k; J" L+ z) ]) n0 S; n1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model; j3 d$ X6 Q$ g l% L. k
1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs i; l9 J6 _# o' h. G! D* g
1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg6 S5 r, Y6 w$ g. l3 d
1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.1 P3 o' f( c9 T. H
1016859 SCM REPORTS dsreportgen exits with %errorlevel%" L/ M4 O: i. [ [8 T7 ~6 ]
1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin0 l8 {* s$ G* o- D8 w L
1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs
, i# }+ d; u% r# S1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts( e) a. \; U0 ]& C# ^
1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
% }* {6 o* s+ U f; ~& B7 @1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.8 U C0 b, X5 c
1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button0 ~; _" [3 w' d& U% H
1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out
8 t# C" ^. Q- f$ U# m$ I1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist
- w/ z- k" u( m: C. F1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed. B0 H* ` _6 @* R' N$ ~+ f" s
1035624 CONCEPT_HDL CORE Options pre-selected when launching base product9 b% Y* V' _4 s
1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly* O6 D! \- X) r
1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.6 P( [+ F L* e, P0 V+ y
1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)7 X$ W# \' q5 a8 M9 O! b
1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol
" U o3 ~4 ^7 Q* ^0 K, u1038285 SCM UI Restore the option to launch DE-HDL after schgen.
- e; }; ?+ m" V/ ~ C6 N }& |3 t1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."# V8 I2 Q, Z& L- {1 i# z
1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro
$ T. B- ]3 ^1 \3 i1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected
; a' s7 C# _4 O: y2 P' U9 ~2 w% d1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing9 {# r& A/ `4 q+ g6 `9 Q1 f
1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found.
8 C0 A% |" g- T7 ^6 F" o+ w1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work. t5 z; J) F. A2 Q- u0 T: K( z
1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu' O4 \6 I( R; t8 p- o, X
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.
2 U4 C. u- y; l1 J0 K/ u$ i7 _1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow
) j/ K3 i, A6 R" N1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory; L0 c: j7 G4 c* r" u/ O# h3 ^, o
1043903 GRE GLOBAL This design crashes during planning phases in GRE.
2 Q$ Z O, |/ e/ u4 l* r1044029 PSPICE ENCRYPTION Encrypted lib not working for attached
2 i7 Q" z- Y. z+ G1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory' S# _! m% \( @& T
1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.( j1 x# Z) X' m( R/ b |& M
1044577 GRE CORE Plan > Topological either crashes or hangs GRE
& _8 k3 X N! b1044687 TDA CORE tda does not get launched if java is not installed! k5 Q/ L( S* F: O- X! P
1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die3 T$ _& p. e Z& V1 O9 V
1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.' k# P" J$ } v- C5 g+ w
1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?
/ Y# [7 [* Q7 k0 V/ s, S- K5 Z7 V1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.
b) F4 A; ^# z1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.% R4 q( B3 K+ M) e
1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow) ]( J* ]9 R# O* S- ?7 Q$ H
1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window. C4 [$ f, ^0 K. y# F( s
1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill6 N) S8 f! d7 z6 E% w
1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond./ V# H( @* d! R9 \; T d
1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5: }/ v/ m6 {9 J7 s- w; b
1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5* }" }3 s( O, b. R# r' M
1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value
. {2 n. S- U4 p% C4 T% Q1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version
& Y/ T! _- M7 H3 ^# R7 o p% M1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn縯.
9 x; T% o7 A6 n* c( P1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.
' J8 e4 g* y6 p: U% z1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.
" Y- S3 G1 D: m/ x- I1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes( T6 f# Y% h! l& j! p1 o$ @7 |
1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
! Z: Y2 p$ k8 n3 O! n( U7 X1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3( p4 D3 X+ P7 j$ x$ e7 k1 |
1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file
( E8 V$ s7 H! b% T1 j# T% j- ~2 D' u1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors
; f: Z3 l) P8 t, m, G1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.
- ^0 L8 m, \% b3 H2 k1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.
0 g; k- C' q9 `1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design# b1 Q* W0 e' o
1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs
/ X* L) B7 q0 g9 z7 ]4 {1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label7 s+ A: z p3 v
1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.
; o" o& p4 R0 b1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy
! T: p: m- H7 L" c" O4 {' Z* z1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down" @) v8 V2 x$ d. D \
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection
1 Q6 D, x# J$ L$ O1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.1 R5 O2 g2 t" ^9 {
1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views4 Q1 s; p9 H, E3 ?
1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline
- |; ] P) i* x5 x: ~/ {7 y1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.
9 I2 R1 ]/ u" Y: @ A0 h: M- w1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created. l/ ^( z4 {0 w4 t
1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move Q" b" }3 f9 I7 S4 W0 X! z: @' P. V
1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value" @$ w" @. j. k+ O0 i8 N
1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer
; p2 `# g$ D. j W- l9 o1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report
# t2 S& J9 Z, ~ n- [0 @9 o1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.0 A0 ]/ A! E& ?+ c
1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete
3 B7 t( T2 }2 ]2 m( [+ i1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.- X# C# k1 v0 W
1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets# B; ~$ r2 f6 }) }) \
1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?# _9 X% _- i2 _* M
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.
8 H$ `% C# I+ {3 A+ h1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished.( C ~, C) x- ?# R
1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00" z, t0 l# a Y, `
1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
5 m6 [$ X# u& X9 ^3 \: `- v1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed.$ L5 F/ w) j4 ]3 {
1063284 PCB_LIBRARIAN OTHER PDV Save As is broken
- a' n- B6 a7 M/ `7 t Z4 D1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs, Z& Q# K% _) C/ K. v
1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.' g, @$ m8 ^" H n- x) O9 _
1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.8 z0 n' U% x0 n) Z
1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design0 \7 G( F4 J3 L/ p+ R! v- U
1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV
2 _: y& ~# V6 w9 B1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green.
! l- P. q' F; M. r1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X: z: f+ h n+ }9 r
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application2 R; b: V* Y: ~3 J$ H: S! n
1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report
9 N ~6 y- A: w W/ x* }) ]+ Q1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC5 E# J! a& e7 R5 y# Z- \
1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic' |$ u; i |' X$ N* i) [
1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.
8 h4 J6 P8 I# c" R2 ]1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file
, M- r# e3 Y& Q3 M1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command9 B' h/ h" o8 G' Z! ?# t) T
1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended
. c2 M, ^& @7 N1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067& x; s; m8 Q; Q! ?7 A
1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design# k7 @* y0 a4 _, I/ ` {( Y9 @# X
1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify
0 E0 Z' ~ T2 d; W( j; ?1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids6 g+ q" h. V" o; U% |% n" W
1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes
! r0 n; V* k" G' M4 O1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow
$ o1 _& u) D& N9 A7 y) F+ U1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal3 L3 \ P/ K2 o5 i' l
1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.; V; ]- J9 k. {7 [
1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6
0 G6 R* [6 _/ Y+ L' I* E1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5
# _; H5 H+ ^+ K* l1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode.) V+ k8 f ]8 }' c; L) P9 \
1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
" f' h. f n" Q# q" Q7 }6 K) P# e1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor- f8 [* g& I8 y% t6 _; Q! V) l5 b
1073464 SCM SCHGEN Schgen never completes.
" ?& L9 N2 e9 K1 u1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory
2 J3 M0 X. {; D! ]6 v1073745 CONCEPT_HDL CORE Import design fails; [. O9 R* d' ~( Q* O8 Q! K% A
1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'
- h+ a; H& @. q: P0 S9 C4 j/ s1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE
4 h" M- ?8 S: h# \5 s1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist
% n- g8 Z: e( a# B2 l3 Z, ]8 _9 p1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter; j7 w0 c7 \, O0 W ~
1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
: n$ j, H' L: z2 I7 I1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.
7 C1 e$ w) D6 ^/ s$ ]+ v1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI
6 ]0 x$ h( ^4 T2 b1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block! K0 w) H; J" i
1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer
, G5 _9 Z' Q4 @( ^1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces
" V( Z' q% W _7 p+ M1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2
9 {7 s' l! i6 T2 r0 Q1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix
/ j" X1 o* H) r( ?3 C, c7 @+ W8 J1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
: ?& P, ?, F3 o1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top; e, Y. k* n% L3 o3 p) w9 j+ u
1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas.$ {4 ], \: V' S
1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value, T0 c9 {3 H7 f6 N
1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.6 x+ K* O' O( k0 Q. o8 r) g
1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey
k; S4 s- Z/ v5 n- }" s5 j) `+ X1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database5 G/ N/ ^3 q& x9 h4 q. N0 f" u7 q8 L
1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset$ m3 l8 Y& q/ B- J# ]' R( k
1077169 APD SHAPE Shape > Check is producing bogus results.
8 h; g( h; q0 A/ Y! ?5 p4 a1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board.
3 v, e8 ^, _( {1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim
% s& L& S! @0 C8 |: q% q1078380 SCM OTHER Custom template works in Windows but not Linux9 g9 P& p2 D6 q+ G" r) {& F
1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly." s* }5 Q; V* \4 @0 b$ s6 b" s
1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide
5 ?, O6 N, c3 G9 f1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
! n0 t% a Q" d/ m8 B. B5 }. u1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"
: U" }, C' O/ K) _) A9 G: s1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text
! R) L9 v( U; g1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control
; A, }/ E( I6 G" t1 P1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical.5 n$ m4 a7 k o: L& b0 ]
1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.
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发表于 2014-7-31 09:06
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