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9 }& {0 r# |/ f& z2 ^9 i. vDATE: 07-25-2014 HOTFIX VERSION: 032
% j' }% q* }) T3 [! I3 o===================================================================================================================================
2 m. \, b1 s/ m; B, G5 {- j. z+ yCCRID PRODUCT PRODUCTLEVEL2 TITLE7 \; r1 U. o( a9 q
===================================================================================================================================$ P+ k3 Z+ ~' f5 X$ S
381127 SPECCTRA CROSSTALK Specctra xtalk reports aren't correct4 N% B, ^: e3 B5 D2 g; q
616770 allegro_EDITOR COLOR Remove the APPLY button in the Color Dialog window.1 v4 V2 V# D4 y% ]0 u$ ^, H) C
982944 ALLEGRO_EDITOR COLOR seperate the Etch to the Shape and the the Cline in the visibility window
( R% f! {* s7 V6 O$ N982995 ALLEGRO_EDITOR INTERACTIV Shown infomation for the selected physical symbols) n. S% V! k" r( g
1024832 Pspice PROBE Shows wrong data & header when exporting trace to .txt
# s, P. A0 l1 s& I4 Z" x( c1063258 PSPICE AA_OPT curve fit fails with error same data works in 16.5 Simulation error: out of range of data4 U5 n; ~' u& A
1112360 PSPICE AA_OPT Advacne analysis gives runtime error while using Optimizer in attached design
$ h9 l/ P$ j7 Z' q5 H* S5 c- _1154323 PCB_LIBRARIAN VERIFICATION Con2con is choosing incorrect Primitive from Chips file and failing FTB Checks: @9 H- [" y8 U) N9 c% Y0 L
1184690 concept_HDL CORE Weird behavior of genview for split hierarchical blocks
6 f1 C$ i& [# M* \7 {* s1212577 PSPICE MODELEDITOR IBIS translation fails without any information in log file
1 Y, @) B$ F4 B$ e, `1 n" ?- i1 o. M1213204 ALLEGRO_EDITOR PLACEMENT Place Manually with existing fixed net behaving incorrectly$ b7 J& c! g( q2 |. x
1213837 ALLEGRO_EDITOR INTERACTIV When copying a stacked via the temp highlight does not display on the last layer of the stack./ K7 ]3 u3 R$ R
1216519 SPECCTRA ROUTE Autorouter will not add BB via between uvia within the BGA area7 v1 H( C! G/ X. ~# R
1220655 PSPICE DEHDL_NETLISTER Support for automatic addition for Power source and Ground Node for Globals in DEHDL PSpice netlisting2 T$ p: L; q; i
1223018 CAPTURE OTHER Diff pair Auto Setup not working for the buses.
; G5 M8 S1 w9 {6 M1225689 PSPICE AA_SMOKE Smoke analysis crashes with attached testcase
/ f1 E" D/ H1 H9 @ l* O1232124 CONCEPT_HDL COMP_BROWSER unable to generate ppt_options.dat file in first go
) p0 w" x; `5 F( ~1235059 PCB_LIBRARIAN IMPORT_CSV pin_delays not being imported into PDV9 @5 I- w" d! I5 h# k) B6 O
1238815 CAPTURE OTHER Capture doesn?t retain more than 191 library in add part/capture.ini under part selector configured libraries. w+ |0 M/ `" _: u" i9 X) ^) Q
1239241 ALLEGRO_EDITOR INTERACTIV Via replacement doesn't replace with correct via but right padstack name.
" u: k% \, Q- M# v1240201 ALLEGRO_EDITOR EDIT_ETCH RPD DRC unresolved evenif HUD turns Green
6 d* o/ o5 D- N! x- T1240314 PSPICE SIMULATOR Getting internal error,oveRFlow for the second run
) ~! ?" k6 r' P1242805 ALLEGRO_EDITOR DRC_CONSTR no_drc_progress_meter variable hangs allegro after running update drc
. i: x9 d' w8 q7 A( v% n1243267 ADW TDA URL to TDO-SharePoint should be defined in CPM File
+ I5 V3 M: g4 b! z1244857 ADW TDA Policy File Variables not working correctly in policy file: D! n+ t }) O
1245779 CONCEPT_HDL CONSTRAINT_MGR Obsolete objects in DEHDL CM! S/ E Z x2 y9 u9 l
1246811 CIS EXPLORER Option to keep the part type tree in CIS explorer expanded on every invoke
. _" `( M L7 @: q0 k" X% w1246964 PSPICE PROBE Simulation Crashes in 16.6 but running successfully in 16.5/ ^3 [$ q: S& l7 Q& K2 Z
1248782 CONCEPT_HDL CORE Display winning physical bus names (occurrence mode) in the the lower block of an Hierarchical design7 U6 y$ N! _# ]; m6 K
1249238 CONCEPT_HDL CORE Uprev from 16.3 splatters text around sch page
+ k* p1 T% g9 N% z1249692 ALLEGRO_EDITOR GRAPHICS 3D Viewer is wrong when resizing its window.. d, i& H6 v; W& I2 N8 |
1249850 ALLEGRO_EDITOR SHAPE With shape_rki_autoclip Route Keepin to Shape DRC is created
2 c J3 `+ _% C( Q! c6 E1250683 ALLEGRO_EDITOR INTERACTIV devpath corrupts if edited from user preferences.8 U- e2 ]9 v0 \ O
1252059 ALLEGRO_EDITOR INTERACTIV Preference Editor is unable to delete a previous path entry for library paths
9 s1 L) t1 p; @1253563 SIP_LAYOUT DEGASSING Not getting degassing voids when close to shape in center of design& {0 M. N# `7 m/ b
1254319 ALLEGRO_EDITOR GRAPHICS ENH: Functionality to change the 3D Model color for more realistic view
* r0 x1 y" C Y ^: Z1254562 ALLEGRO_EDITOR DATABASE Unable to delete a subclass that exist only on classes Package Keepout, Package Keepin and Route Keepin.
/ U5 c" ~4 v- o/ c1 ^! W1255169 CONCEPT_HDL OTHER ADW (BPc) Packager should report the specific corrupt directive in the .cpm file
+ ^5 p& C4 v5 Y" Z0 m+ _1255573 ALLEGRO_EDITOR DRC_CONSTR Need soldermask DRC checks when same net via and smd pad overlaps
+ S! W5 A: J+ E1257950 CONSTRAINT_MGR SCHEM_FTB Changing xnet name on Allegro CM.
6 p6 }4 |& x( _/ ? ?# i1 V1258165 F2B DESIGNVARI changing visibility of Probe_number in variant schematic changes it to $Porbe_number
2 I: `4 g/ }& v* U, n9 t* g1258274 PCB_LIBRARIAN VERIFICATION con2con crash with no notification or error message
6 G5 {0 _- r' L7 i3 \1258860 CAPTURE PROJECT_MANAGER Bug: Text Editor (File> New> VHDL File) filters characters from Text5 {3 V/ z8 K5 M. h, f! U$ _
1258872 CONCEPT_HDL CORE Objects are copied (instead of moved) when moved from sheet to sheet
, p) Y p9 x9 Q6 y: H5 y0 p1259284 CONCEPT_HDL PDF HDL_POWER ( global) net does not get transferred to the published pdf
9 V+ V8 }, y; {6 K/ Y4 n1259375 CONCEPT_HDL CORE Help link to cdnUsers.org needs to be changed
- Y! ^; s, E) Y- S/ M1259860 ALLEGRO_EDITOR INTERACTIV Edit > Mirror does not display asymmetrical pad correctly when the footprint is attached to cursor. ^6 U/ f! L" {! C3 t5 o1 d
1260002 ALLEGRO_EDITOR INTERACTIV Alt sym hard is not obeyed when using Edit > Move > Mirror- l8 Z: C* d* p5 n. m4 C. n
1260006 ALLEGRO_EDITOR PLACEMENT funckey r iange 90 rotation issue6 |" j7 I! | K; l) L" X3 S! |
1260667 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes when running AICC command on few Diff Pair traces.
3 P- C$ f4 b8 V& X1260763 CONCEPT_HDL CORE Export Physical fails with $TEMP entry in Setup-Tools
5 l/ P2 ~) Y- L$ N& q% k2 N1260847 SIP_LAYOUT SYMB_EDIT_APPMOD Border texts seen as triangles.
$ {/ V% K0 @4 H* D8 V1260948 ALLEGRO_EDITOR SHAPE Dynamic ground shape is shorting to via of a different net at layer 4 & 5 in this design
: w5 H3 n K$ ]2 v1262011 ALLEGRO_EDITOR PLACEMENT Key Properties on Component Instance/ Definition on available to use with Quickplace by Property: z5 A# U( C- C1 K' U$ l
1262322 ALLEGRO_EDITOR PADS_IN Pads_in can not translate route keepout which specified for the all layers.3 D3 t8 V6 I/ S7 F. m$ R6 V$ s6 n
1262626 CONCEPT_HDL CORE PROBE NUMBER attributes lost from the nets after upreving the design
& A/ r$ s# M: q V$ J5 G5 {$ H1263592 PCB_LIBRARIAN VERIFICATION Unable to check in Schematic Model due to pc.db file
& c: f4 [& w% _8 M& z7 c- z1263685 ALLEGRO_EDITOR INTERACTIV Editing Photo Width value from non zero to zero allegro gives warning- Value must be greater or greater to zero; [9 ~/ M X7 V" F: j7 z6 R A# B
1263704 ALLEGRO_EDITOR EDIT_ETCH Bug - AiTR wrongly deletes blind vias and do reroutes.' J% O; g. j9 e6 v
1265120 ALLEGRO_EDITOR SHAPE Require voids in dynamic shapes to use pad value
6 V! l+ r L3 o# R1265275 ALLEGRO_EDITOR DRC_TIMING_CHK When XNETS are dissolved by removing the Models all Physical and Spacing NetClass associations are lost& M/ \" X7 j* l4 Q) s
1265633 PSPICE SIMULATOR Bias point result is different in consecutive simulation run of the attached project* F7 `" I9 u- Q$ p3 }3 y9 Z
1266349 ALLEGRO_EDITOR PLACEMENT Rotating symbol while placement show wrong angle of rotation than the placed angle when Angle is set in Design Parameter
! A: N! T% C% y4 ?; J1267541 PSPICE PROBE pspice.exe does not exit when run from command line
) \8 P$ S) Q- X/ f# b1267707 ALLEGRO_EDITOR PLACEMENT Mirror Command - preselect/postselect bug with general edit mode- j- F: q, W6 r3 X: Z' ]
1268299 PSPICE STABILITY Pspice crash on attached design
4 _- p# ?) Z4 X* o$ Y1270879 ALLEGRO_EDITOR COLOR Color view save creates .color file using older extension" K2 G) R9 Y7 G$ ^
1271295 SIP_LAYOUT DIE_STACK_EDITOR Die stack editor support needed for large variant combination designs.- g3 S% q. V) Y" P; N: R
1271385 CONCEPT_HDL CORE Locked property can still be added
- K& r- ` L- e! y* ~) ]1271853 APD OTHER When using the beta "shape to cline" command, add improved messages and partial completion of individual segs in error.- B* C$ q9 J5 u, j* P" S
1272197 CONCEPT_HDL CORE concepthdl_menu.txt contains invalid Variants menu, N, c8 Z# D x- _5 @! }
1272318 CAPTURE GEN_BOM BOM_IGNORE not working for Capture BOM on hierarchical designs.3 x0 O: C0 g# E E. z1 r$ B
1272743 ALLEGRO_EDITOR PADS_IN PADS Library Translator does not open the Options dialog window.
7 T% A) z1 S& P, V1273517 F2B PACKAGERXL Netrev error - ERROR(40) Object not found in database5 J2 s5 V! R2 ?7 M7 \- x
1274000 ALLEGRO_EDITOR DATABASE PCB layer can't be removed, h- D' m7 ?) u7 r. ~: q
1274530 ALLEGRO_EDITOR INTERACTIV Add Circle radius value changes next time using this command6 e5 V) Z/ c, d7 B0 F
1274697 PSPICE AA_MC pspiceaa crashes when running Advanced analysis monte carlo for the attached design
3 h( {& Q& V" @: @# R1275154 CONCEPT_HDL CORE Hierarchical Blocks lose ref designators when moved to another page
, M7 h. J; B2 ~% J0 }& O1275724 GRE CORE AiDT delete another clines5 G3 V' {7 Z5 l& X. A2 }8 l
1275831 ALLEGRO_EDITOR DRC_CONSTR Waived DRCs return when using multi-thread DRC check
$ Z* `3 _& Y) {2 P% r* y! c1275834 CONCEPT_HDL CORE ERROR (SPCOCD-569) on global bus' [* E4 }! D0 `* a
1276334 ALLEGRO_EDITOR PADS_IN PADS Library Import problem with outlines4 g# ]! w- N5 ~4 ^( C' K, V# w7 @
1277062 ALLEGRO_EDITOR PLACEMENT Swapping parts from top to bottom Orientation changes
" P: ?* {4 L: }3 _1278746 ALLEGRO_EDITOR DRC_CONSTR Package to package DRC allows place_bound_top in 0 spacing has drc in 16.6 version.
1 x8 x( ]2 K# X- b* g3 O% s1278804 CONCEPT_HDL COPY_PROJECT Copy project crashes; o8 X) s+ F8 R! m& e, T) j ~9 ?
1279362 ALLEGRO_EDITOR INTERACTIV User skill file makes Allegro Icons gone away/ [' E1 ]/ e1 m5 @ c' I7 b
1279619 ALLEGRO_EDITOR DRC_CONSTR Netgroup in a Netclass doesn't inherit Spacing Cset
" P4 c% O; z' v+ R' m& Y1279815 CONCEPT_HDL CORE Text > Change and RMB Editor does not allow multiple text edits3 S$ ?& l! C6 B- N
1279876 ALLEGRO_EDITOR DATABASE Using the Curved option in Fillets results in a pad to shape DRC
u! g" ?- w0 C5 R! H8 O# Y1280435 F2B BOM BOMHDL with variant repeats the PART_NUMBER value
3 {9 i5 A# |1 F( C1281669 CONCEPT_HDL COMP_BROWSER Match Any radio button in Component Browser didn't work.. n5 c: ~& O/ C2 {
1282001 ALLEGRO_EDITOR DRC_CONSTR Updating the DRCs on this design cause the DRC count to change on every update" c! r. e. [3 Z5 w+ ~
1282480 SIP_LAYOUT WIREBOND Info on the Wire Count property needs to be updated indicating that it is a User Defined Property
4 U7 R+ j. c- H1283952 ALLEGRO_EDITOR PLOTTING Published pdf does not show dotted or phantom lines. J+ }6 ?) b: ~) X( C' F
1283957 ALLEGRO_EDITOR INTERACTIV Replace padstack in "Single Via Replace Mode" is changing netname of the vias with the latest hotfix of Allegro 16.60 T/ S: a7 ]) ?4 x: ^& N5 p& M' v
1285588 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase control has wrong analysis result when add rectangle test bead in Clines.! g% ]6 z' @ G
1286743 ALLEGRO_EDITOR SHAPE Getting copper islands in the design after running the Delete Plating Bar command# j& O/ Z+ X, M6 Y
1287215 ALLEGRO_VIEWER OTHER Allegro viewer plus does not support constraint regions
* `% J5 K9 v4 H1 ^1288808 APD LOGIC Derive Assignment stalls out or won?t finish and appears to run out of database room." C& ]& {8 s" s
1289251 ALLEGRO_EDITOR SCHEM_FTB Pin escapes (clines and vias) not inheriting new net name from a pin with a new net name.
8 _ `4 E* S9 m% a+ H! t' s, K7 E1289293 F2B DESIGNVARI Warning 04: Cannot merge the variant properties on variant instance C119 component with same canonical path not present8 A. S* ?' p) `7 k- q/ Y
1289809 SCM VERILOG_IMPORT User not able to import a verilog netlist into SCM# S5 n6 L# g1 P; \ p# e- n
1290696 CONCEPT_HDL CORE Copying a net name repeatedly causes it to go off grid
) q) Y9 p4 y6 {* h, q0 ]1291162 CONCEPT_HDL CREFER crefer crashes when selecting generate cross refernece for all nets selected) x+ Z; r5 v, O6 m5 s6 X U& k. Y
1291285 SIP_LAYOUT IMPORT_DATA Replacing a Die with the Die Text in Wizard causes some Clines to Shift, creating new DRCs.+ k' J9 x2 g* V- ~
1291658 ALLEGRO_EDITOR INTERACTIV Cannot add Frectangle to Group2 n5 ?, |/ H& V" j0 z1 ]9 F
1292180 ALLEGRO_EDITOR SKILL Allegro Crash while performing query contents of "Maximum_Cavity_Size" with the skill command 'axlDBGetPropDictEntry'
$ M. N) k K3 R8 [# L" ~1 Q1 u- i, x1292210 CONCEPT_HDL CORE DEHDL crash if design was opened with -nonetlistuprev option. [& `. I J, _2 |( D- w& n4 |
1292278 SIP_LAYOUT WIREBOND When creating Wirebonds by Importing a Wirebond File, (wbt) the wirebonds are not on the correct Die layer
# e8 Z8 H& c |; E# Q; L, p1292282 SIP_LAYOUT INTERACTIVE Getting Multiple GUIs when the Wirebond Import is open and we select outside the command GUI.* M# y/ S' [* r& F. u! J
1293381 SIP_LAYOUT IMPORT_DATA Import SPD2 error( Q+ F2 ^% ^6 g+ Y( N+ u2 t$ g
1293889 CONCEPT_HDL PAGE_MGMT page name regression result deleted by netassembler( M! b& ?3 |) M$ m" X
1294124 ALLEGRO_EDITOR INTERACTIV Samsung Mobile division wants to disappear the grids in the display window when zoom-out function executes in the allegr
' a2 }3 H3 G& ]2 p" Q1294749 ALLEGRO_EDITOR ARTWORK Null pad is flagged as an error that break Thales automatic tape out
! ]1 x, w" T1 B2 H+ X, N# l) ~" j+ m O1294777 ALLEGRO_EDITOR SYMBOL Mechanical symbols missed on STEP result! Z2 b+ U, E- s( P+ k
% H- G$ P; \; f: \8 [9 d. y! e5 \DATE: 06-20-2014 HOTFIX VERSION: 031# I% w) r8 b) k# M9 f: b y
===================================================================================================================================
3 J# I9 s% B0 v$ u" sCCRID PRODUCT PRODUCTLEVEL2 TITLE
* y0 ^, f+ p3 l2 a3 j, d2 M/ _. _===================================================================================================================================# Z( @8 H9 @; K3 o# r: ^. {! R
726553 FSP CAPTURE_SCHEMATI Method to select bus bit?s order while generating Capture design from FSP.
7 @5 x3 v* @: F* H) v7 `1257631 FSP DE-HDL_SCHEMATIC Schematic Generation selects incorrect symbol version6 I8 g# F/ F- u* q3 S4 c$ H+ z
1273456 ALLEGRO_EDITOR PLACEMENT Place module instance causes Allegro to crash
' Y! W1 \' V5 ^# Z g1277099 ALLEGRO_EDITOR INTERACTIV Clines and pins are disconnected even though they are at the same x, y coordinate.
3 X$ ^9 i# F3 {' W4 ^1280913 ALLEGRO_EDITOR EDIT_ETCH Add Connect should be able to be made by go straight even though the cursor is not exist on straight line
7 u3 e/ v2 |$ m/ I7 N4 `4 t. p; Y1282491 ADW PURGE ADW PURGE is removing Page Name data in DEHDL9 H8 S+ {' k f7 M$ C+ {
1283045 ALLEGRO_EDITOR DATABASE Ecset not getting downreved.
7 _7 _9 a; n# ?) D9 Y# j: u. _1283138 SIP_LAYOUT IC_IO_EDITING symed app mode chooses wrong text block sizes for I/O driver inst names$ Q9 E6 Y4 J0 c# E" l- y, e
1283227 PDN_ANALYSIS PCB_STATICIRDROP Enhancement request to add 32 bit files for IRdrop5 Y7 ^& B9 N$ a% X
1284656 CONCEPT_HDL CREFER Crefer fails on large design
# a+ ^& B8 `3 H% d! l9 |1285814 CONCEPT_HDL CORE DEHDL crash on opening the Design k: q/ t' D+ i' V, s
1285967 ALLEGRO_EDITOR EDIT_ETCH Slide via in circle pad1 I, u8 B" S5 _+ j" i
l' h5 z# T# P4 QDATE: 06-12-2014 HOTFIX VERSION: 030
# E, T) Y; v9 O D5 I4 b# l, F% P$ d===================================================================================================================================1 j( L. ]. a' f6 p0 D+ m6 u
CCRID PRODUCT PRODUCTLEVEL2 TITLE2 Z \5 ^! U+ T7 P- ?$ ^4 w
===================================================================================================================================
. A a; w6 O: ~0 ~' @* f9 m! l& I8 x982961 ALLEGRO_EDITOR PLACEMENT Show the Rats when one selects physical symbols to place them" x j9 B3 E2 P9 t
1138680 FSP POWER_MAPPING Ability to assign decoupling capacitors in spreadsheet like application6 P9 W! }1 A/ k, M- z H, J
1243410 SIG_EXPLORER EXTRACTTOP Circuit topology extract failed in case of CLASS, H9 D0 f7 h/ Z5 b
1262977 ALLEGRO_EDITOR TECHFILE When importing a certain tech file into an empty .brd Allegro crashes.3 M r9 v7 k8 G5 z# G" X% e! l
1267558 ALLEGRO_EDITOR INTERFACES Arc part of symbol pin missing in 3D view of step model
0 M$ J7 j. O2 C7 ^* n9 I+ p1268252 ALLEGRO_EDITOR GRAPHICS step place bound issue(3D View)
. A5 u5 P2 i8 ?7 Q. i; j4 a/ M1270450 ALLEGRO_EDITOR INTERACTIV footprint add line on line crash
2 {) ` q$ l& E! ^$ q# q; y8 Q1270962 CONCEPT_HDL PDF PDF Publisher command line does not print pdf file if double back slash is present8 \- Y4 F i( i$ X3 y0 D( u
1270964 ALLEGRO_EDITOR mentor Mentor translation crashes with no errors in log file% e8 N3 P' V% x
1270999 MODEL_INTEGRIT TRANSLATION ibis2signoise Issue
3 y" r Z: F+ H1271543 ALLEGRO_EDITOR PAD_EDITOR Library import reporting missing padstacks0 b' H0 w# q/ h1 P3 l6 Q" A
1272099 ALLEGRO_EDITOR GRAPHICS Plotting does not fill shapes6 }' [( O0 k; ^% `% ~, d6 |
1272406 ALLEGRO_EDITOR DRC_TIMING_CHK SKILL command 'axlDBTextBlockFindName' returns 1 when nil is expected
" n" F2 M5 y# O: I1272748 ALLEGRO_EDITOR GRAPHICS 3D viewer crashes on this specific testcase" m3 Q- M. J- @( @1 |
1272793 ALLEGRO_EDITOR GRAPHICS 3D view doesnot displays hole with offset correctly
3 l% Y6 W+ [- M7 D1272863 ALLEGRO_EDITOR INTERFACES Ability to find the origin of STEP File in order to place it exactly where it needs to be on footprint during mapping.
+ n& |# u2 l6 |! a, v1273264 ADW COMPONENT_BROWSE hyperlinks not recognized in the component browser
5 F5 a: i9 ]1 U' T+ }! e1273304 CONCEPT_HDL PDF Publish PDF from commandline does not work if there are spaces in the Path
6 c" f1 s$ H# X {% l+ {1274661 CONCEPT_HDL CORE I can't copy a property from one component to another+ w) Y# \8 ]2 D [
1275237 ALLEGRO_EDITOR DATABASE Allegro Crash on running DBDOCTOR for a board5 a; b9 o2 e% ]3 b+ J- |$ U
1275345 CONCEPT_HDL CREFER The Xref information page number values are incorrect. N4 v7 i# j0 Z& Y9 T; o9 N
1275748 APD IMPORT_DATA WireBond starts away from the Die Pin after importing Die using Die Text In Wizard
" a. \8 ?" ?4 a4 j0 M1276270 CONCEPT_HDL CORE DEHDL crash by Zoom In > Ctrl+A > Move
6 N* b0 Z8 I5 F& m4 ~+ W7 @ o1 G1277735 SIP_LAYOUT IMPORT_DATA sip layout spd2 translator issues with offset die and mirroring9 q: w9 Z1 ?+ H2 v8 \
1279258 CONSTRAINT_MGR OTHER Import logic stops with error4 o8 [% e0 i. f3 N
1279694 ALLEGRO_EDITOR SKILL axlCNSSpacingMin('via nil) crashes Allegro PCB Editor4 O, z! j2 }+ y! [# ~
" L5 K1 W" O! W* t0 L1 T
DATE: 05-23-2014 HOTFIX VERSION: 029% V" G( o, ^" h( s
===================================================================================================================================
6 ` y Z1 v/ e! z+ ~CCRID PRODUCT PRODUCTLEVEL2 TITLE+ G/ P$ a1 t" R( y0 I/ h+ r* M% ~
===================================================================================================================================1 |" K- G7 _% T/ c
1209461 FSP DE-HDL_SCHEMATIC Hierarchical Block Size not automatically adjusting to text needs) F' J9 B/ a8 |' [. u
1217832 SIG_EXPLORER SIMULATION S-param generated by SigXP doesn't match with HSPICE/ADS.! w8 Q( K D% q1 t% r9 l
1263575 CONCEPT_HDL CORE Copy-Pate makes Components Off-Grid
8 Q) g# l. n, ^- b, W0 g1267602 SPIF OTHER Route Automatic hangs* F9 b6 ]& K/ k! l* }& |
1268022 FSP PROCESS FSP is not respecting the use banks for attached design." M2 j0 N& \) k: K' \/ G- ?. m
1268587 ALLEGRO_EDITOR INTERFACES Enh. Preserve relation between hole and padstack in IPC-2581
a- R" I; ~ J/ J1268918 SIP_LAYOUT DIE_ABSTRACT_IF SiP - DIE export from co-design object to XDA results in missing data. ~; N# |+ D+ x. H/ h
1269232 CONCEPT_HDL INFRA While pspice uprev the design crashes- C- f/ o o }% s( _5 ?) `6 Z: Z
1269825 SIG_INTEGRITY SIGNOISE PCB SI hangs when running crosstalk simulations
5 S( Y e; x5 @* C( Q: R6 i1270963 ALLEGRO_EDITOR GRAPHICS Add Circle lint font hidden/Phantom has resolution problem
: Q# K/ X; U3 Q. c1270990 ALLEGRO_EDITOR GRAPHICS Allegro response is slow when added circle4 y2 l3 M- s9 {3 U
1271655 ALLEGRO_EDITOR MANUFACT Dimension option causes a generic crash, reproducible in any design" X, O: I! Q* H9 B8 m/ ^
1272495 ALLEGRO_EDITOR MANUFACT Filtered Part numbers in IPC-2581 still pass actual part number for references onutide of BOMItem& ]! V: s9 a* w+ E
1272839 ALLEGRO_EDITOR MANUFACT Kindly explain the drill legend behavior when padstack rotation is 45 degrees and mirrored ?
+ o* h& z- u9 p) d1 f. F' C1274518 ALLEGRO_EDITOR ARTWORK Artwork does not create void correctly.- B" _* b& ?0 q
/ s) g; t7 G% H3 ]7 |
DATE: 05-10-2014 HOTFIX VERSION: 028
# G6 J8 h6 \3 n3 z4 H$ L===================================================================================================================================4 ]; A) t) b0 w4 |: j
CCRID PRODUCT PRODUCTLEVEL2 TITLE
2 s! F, I% ^! \! h* f6 @===================================================================================================================================
2 z2 \' k+ g6 p1199256 ALLEGRO_EDITOR INTERACTIV DFA bubble does not appear when moving a symbol to within another symbols dfa bounds on specific symbols
5 E4 X8 s6 Q" J+ v4 u! b1220196 ALLEGRO_EDITOR OTHER create xsection chart results in ERROR(SPMHA1-73): Text line is outside of the extents.: A' m9 q( B ~
1259520 ALLEGRO_EDITOR EDIT_ETCH Allegro will crash when adding connections to a differential pair.
% V# w0 r K2 m- J; `; \5 I1260446 ALLEGRO_EDITOR VALOR Creating odb output the xhatch shapes where arcs are will become inverted. Difference in the geoms.out extraction?
" I0 O( C7 R9 p1 z) B4 k3 Z$ |$ X; V1261313 ALLEGRO_EDITOR INTERFACES Step mapping does not show all Available Packages6 y" q& h$ P* j8 I8 o6 c
1261356 CONCEPT_HDL CREFER crefer is crashing with generate for all nets option) |! v. M: ^% x9 D0 \
1261514 ALLEGRO_EDITOR ARTWORK Exporting raster artwork with overlaping voids fails.' C4 i2 ]1 Q* k$ u
1261735 ALLEGRO_EDITOR ARTWORK Presence of Smaller shapes inside bigger shapes is crashing artwork generation." u& G( w" @: Q% L: _/ i! J: ~
1262019 ALLEGRO_EDITOR INTERFACES Artwork control form hangs if we close PDF publisher gui
( p, G* g% t& n! ~1262246 CONSTRAINT_MGR ANALYSIS Constraint manager shows ALL PASS when Adding members to a NetClass and adding parallelism rule
S4 l. P+ `; z6 U0 Q' d4 B" v1262560 APD WIREBOND bondwire can't connect to GND ring directly
a0 u4 s% N) A) k5 ]1263275 CONSTRAINT_MGR OTHER Import of constraint file hangs in this design
/ l+ e1 t! `# E, m1263358 SIP_LAYOUT OTHER SiP Layout - Void adjacent Layer enhancement to merge voiding for PADS without changing shape params
. ?# e; Z2 I; \3 e! {7 Q0 ?* Z1264109 ADW LRM LRM error - WARNING(SPDWREV-7): Unable to read the design
- u& _/ N' ^3 Q+ j& Q1265580 APD MANUFACTURING Icp_soldermask_allow_pins cannot create correct solder mask when the pin rotate.4 q3 O: g, D9 g3 K7 b _
1266391 APD LOGIC SPB16.6 Derive assignment : want to select 1 DRC marker only.
1 Q6 Z+ c! V% \7 K8 v1266687 ALLEGRO_EDITOR SKILL The SKILL p
+ P; G2 T4 V$ v$ D6 s1267267 SIP_LAYOUT WIZARDS Attempting to create a die using the die text in wizard but the tool is not creating the correct die outline
% y) x' M, N( K6 [' |( W1267308 SIP_LAYOUT OTHER When updating a BGA with the Symbol Spreadsheet tool it will start, update a few pins then stop.
8 P4 h; X& \7 k: n1267639 ALLEGRO_EDITOR PARTITION Allegro crashes when partition is created and opened from a location that contains "!" in its path.
& x: Y; Z- `: d# [ z, C6 @/ Z1267704 SIP_LAYOUT STREAM_IF Cannot import stream file, the tool starts scanning the file and never stops.' H# ^6 C3 f3 q# _; t) S/ R6 B
1267907 CONCEPT_HDL CORE Ctrl+RMB Context Menu Option doesn't work.
% | z) w: v" j, \; \; \
( _ H& h; ~7 m3 g. q4 r$ r' KDATE: 04-25-2014 HOTFIX VERSION: 027
0 ~- K4 u. S2 A j4 G6 ]===================================================================================================================================9 q+ Y! F& P, {! ]' O" l
CCRID PRODUCT PRODUCTLEVEL2 TITLE7 F( ~* s% |( e# ?, e
=================================================================================================================================== ]$ @3 I! i9 n! t; T( I
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM
# }" Y! a: z/ e7 \) L481674 ALLEGRO_EDITOR PADS_IN No board file saved from PADS_in
; x, U5 ?7 b b0 S982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
* h5 F4 k4 P( _/ E' L- p- B: e4 _1012783 FSP OTHER Need Undo Command in FSP$ Z4 a- a4 j! h0 M' y8 n
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.' M+ e; ?: l/ R1 e% S1 v
1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
; N, Q) V# C1 z! S% I4 k. c1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
8 ^1 }8 c: g; H5 e+ n" q" K n1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups" B9 C Y$ V7 _) Q. K
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash+ M) N0 m# ^: a' X
1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
' g/ j5 z4 J3 _6 d# u! n) c- t" j' @1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
4 S* q! d& n+ t" U0 b: e0 R* P1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
{2 C( [" t( F" a& I' r+ ^1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
* d- j; ]: M# W& \, C9 j5 k' ]1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings
, B7 b+ ^/ T4 `1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
# y# }& ?; C* n. h1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV4 g! L4 K9 D3 } y; r* K
1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part." \/ e& \) Q1 ^! [9 x: V5 D
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
1 e0 B8 e3 F: j; J; m& n. s1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime8 I& r( U3 a0 E" H
1208478 PSPICE PROBE Attached project gives overflow error with marching ON.( w |" l& l$ p4 A4 W
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol
4 S8 }% s D. W9 p7 [1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed# Q0 ?& B J# a, q
1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
# A0 Q6 ]/ C* y$ j6 Y1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers
. M! o/ ] `( u% K' s& _1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?+ P4 O X2 J/ r: t
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.: T. D% r7 s" t
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values' I- R# Z# j4 y5 N# C/ n% T
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging
7 R" g- p- c; \- D) m1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information" N1 b# }+ U$ S. |, B
1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added3 ]6 F; f# Q$ L# e* d; G
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
7 s# ]; @( f3 g0 ~9 C! x9 T9 }1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes8 N3 Y; V3 w' d1 r, |8 A
1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux
: l2 H* K' w7 K" _ w2 H" F1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
5 s' O \' J* o1 }' S' w# q1221182 ADW TDA Team Design with SAMBA
5 `! U3 s& I& b2 k; q8 [, {8 m1 q1 @1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
' M% M1 y0 f; g1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
" j' v' O' h% d2 h) m1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
$ ?$ h8 B6 \1 N t* |1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
6 H6 f. l/ P' O$ t) f* w, C1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
. Z! U$ ?* A7 t; T% v [% F1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
+ `8 o) @( H* f, C+ ~/ q* g: U1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor
( t. g( v! {* e4 I1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.# s9 V9 `. R A6 x& x
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path& u7 Q6 {; N3 d1 H; U, ?
1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin
% S6 b+ [& I6 m1225494 CAPTURE DRC Different DRC results for Entire design and selection l9 j8 j/ {& K, `/ M3 }9 G2 i
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property" J' R' X+ w2 J- h. n3 Z
1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
_* y, Q' w7 r1 j+ ]" {1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
+ {. z$ N, x4 c1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts� function is inconvenient for Global Signal1 E& V s0 z. w5 f% [
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
% n. z9 j i* d+ o4 E+ S2 [1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
0 U! G$ ? n3 G2 N! o* }, B% Q1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
& S! O: \" l3 H0 l" {* i M1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration
5 O2 m+ w0 n( F- i8 ]1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part
+ ]! i& c8 X/ j5 U: `6 Q2 L( ^1 i+ _1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case j. q6 \+ {8 q s& d3 j4 M
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins, ~" u- J1 n2 t% o1 {0 V
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
, X4 V7 L" s% x7 B4 Z1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.5 G/ H6 ?8 ^, i6 ]
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.5 E( O4 S& J7 b: p
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
# ^! V# q$ x0 V( U6 I$ i0 v/ t, y1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
7 x0 M3 I. z1 L% c& l% ]6 _/ Y# H1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
$ d4 @! m( H( b# t! d/ C4 P6 o1230432 CONCEPT_HDL CORE No Description information in BOM. y5 I" x2 Y N d2 X7 r$ G
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
8 E( p$ i% ^* N; t1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files
$ E) k z* R- |2 C8 N. u1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands4 J# C% T3 A6 g: e' u, l: W) `
1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets+ m3 ~, O; Q' V+ G
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.$ z9 J4 ^; n, \ }+ k& I" u4 ^
1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode2 ~2 U$ V. c9 r' o: ^' w5 L
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical9 l6 K5 @) r w% c0 O
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode2 Y. \' C3 y' U
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files7 t7 a* ~ C2 z0 d" H9 k0 ~
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy
( R6 H8 K! s1 q9 i5 N" R1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
* K$ l& J' K1 {0 i2 m1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect( c3 R0 y/ G( q8 L% X7 ]6 R/ O
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
$ v9 F" T O5 A- Z9 F1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
; r* ]; ?8 ?3 J8 E- {: T1236161 CONCEPT_HDL CORE Import Design shows the current project pages U$ G f6 v, a ^# k4 R
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.! J3 e1 J7 N0 f+ y, u; {( V8 e
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
+ i4 R8 i- Q" }% T0 N6 O3 z8 t1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file, l/ L( p- @( d g9 y5 ]7 m3 G
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape V* X# K' O/ w
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming; c \ c8 p4 ]" i& F& g
1236781 F2B PACKAGERXL Export Physical produces empty files
7 E. X( Q! W! z1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
" D' [/ I8 h6 ^1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib� command
/ ?/ ~2 j; g c: P1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition$ a- J/ W; J, t) p
1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
% X- f: V* t9 [6 A1 r0 `1 v9 R# ?1238852 CAPTURE GENERAL signal list not updated for buses
0 m/ D" {7 ?4 ~" v1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes
5 V! B: J6 h+ a1 }) e. n W9 u4 o; I4 P1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
; m2 C( k. ]/ }8 z' |1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE
* h" Y- h# `9 B1239763 PSPICE PROBE Cannot modify text label if right y axis is active0 a9 ~3 `) j1 T- L0 ~
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images% r0 R$ r' G( N' t" R+ z
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.5 \9 x5 e4 Y5 y$ U
1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing- y) F( D+ h6 L! [) `: h% K
1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file& ]! O$ N; r g
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable& b2 D+ C: w5 ]5 |; b
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy: H" ^% s, [& F* y8 V; w$ w
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
2 ~0 m" i0 ^/ F9 O1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working
( E/ c8 |8 ]2 G& ]5 Q0 q1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
2 ^) `' ^* S. |1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
0 Q: Z5 x2 s# i- `6 w1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
+ c8 F1 u5 C2 A3 M8 v0 V1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side
1 `8 C3 z; n# ^9 e- t( p1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer
" u6 H/ e% N! Y/ @. j6 {/ X0 l. e1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
) {1 J9 V$ [, i* B1243609 CONCEPT_HDL CORE autoprop for occurrence properties
: m( B' Z7 G% V6 s6 B: i1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
; Z8 ?$ }! `4 G9 @1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
' t+ w* T2 ?/ \1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring0 l4 Q3 x! V( n( ?7 Q
1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
, r1 q* _- {# S9 m6 z; Y1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
4 x2 @7 b, R. O: z1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design& _- F" {" C) m9 E) X9 e$ x/ p
1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?) r7 ^9 y4 D: I- ]& T" }
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
$ q2 @# b' b& k. L. w' _1 q1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters1 u1 ~" z* y* K. K- G
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown8 d5 q7 A1 A. P+ r$ f
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
1 D2 d: [% R% D1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL. z1 B% q) {+ ~. K
1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained* R4 Z6 v' c" B* H- J
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box3 ]8 ^8 O' R4 u) ^+ ^/ H2 h0 P" b
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered& ?) p8 {4 t7 m1 D# o9 R
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
$ ]4 Y* r* I" p0 G/ O1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts
: a# v2 h- P' n9 S! c0 b3 a c1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
4 d+ ^" Q8 G5 M" s" ^( r1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
1 L4 z* p* a. s5 |1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly
0 Q7 m" t: O6 t {5 Y* M$ c8 M1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.& Q% N6 e0 g# N# s7 i. j% q
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
5 O: R! \: O( T8 u1253424 SCM SCHGEN Export Schematics Crashes System Architect
* C1 F7 D+ z7 r" ^9 Q1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled
+ t4 @6 l& `* m/ E+ Q9 F1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing# b; N5 x; i/ O
1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router! H9 a4 K& N$ Z/ X/ d- e1 m
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error7 p1 V/ ]4 R8 g
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.& Q6 G7 q' `& G1 H9 r4 N
1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation
, U3 }8 [$ \5 _$ K+ H F3 r1 V1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects2 {- T# ]8 ?! V8 p- K% ~
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
6 |! _4 n' c4 r) g, E! L8 p3 Q* Q1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
, W, T$ D M: @0 U; ~. s' M1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE7 T/ p0 d% d; Y3 J6 k
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
" g- ], ^' l, R1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design3 i. Y8 h! N0 }3 R
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library
; ]8 e( G s9 P* j+ J1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long+ ]( P; W% |8 k9 N% v! m
1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash
' ^3 o% p4 v) W) [1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time; E4 d. V1 E- z& e {$ @7 l* Y% q1 S
1258029 APD WIREBOND The bondwire lost after import the wire information
' P# Y9 I1 Y9 n& ?8 A- h$ e1258979 APD NC NC Drill: There is difference of number of drills.
0 _ Y7 r' H. w" S5 @1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement
+ d h. ]8 V/ X5 ?4 @, R1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
9 K+ }* w5 Q) V- h; f9 Z6 |1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"
9 h; C& Q& C, I5 }5 f1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines
4 C' i6 h4 a! j. C& Q* E1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void* a4 y9 K7 ?4 J& C( ?5 }
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss8 @5 e/ K3 Q/ _; a( w" K' Z
! r9 b4 G% C6 M' v) q$ X
DATE: 03-28-2014 HOTFIX VERSION: 026
3 g3 p) d W5 k9 ]& i===================================================================================================================================- l1 Q9 \4 y& t. X
CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ o. g4 E3 D- G$ `/ q===================================================================================================================================* U1 f: z' d/ q. b9 j1 g
1190942 CONCEPT_HDL CORE Cannot copy locked .xcon files" E4 l1 j( o% |8 G) o* S6 o5 j4 |
1226085 F2B PACKAGERXL Winning net NC shorted with loosing net due to PACK_SHORT
4 H$ j1 f) S, X# w0 ~- f8 k# _1244894 SCM SYSTEM_OBJECT Get packaging error when adding a pullup/pulldown resistor9 w/ K" a1 J: `/ l7 s& I3 X" p$ A# M
1247432 CONSTRAINT_MGR OTHER PCB Editor crash
1 U1 ~8 {/ y$ i1248560 F2B DESIGNVARI Variant Editor > Help about for S024 says unreleased ?+ r* W" {' v- V% I
1248712 SIP_LAYOUT WIREBOND Changing the charecteristics of a Bond Finger causes it to shift position1 C& L( ]2 n; O5 |3 V' v7 D
1248839 ALLEGRO_EDITOR OTHER 16.6 S023/024 crashes on Logic Change Parts command.
4 o& }5 V5 `$ |1249000 SIP_LAYOUT DIE_EDITOR unexpected shift of instances/pins by co-design die editor
, d; u1 b3 x( m1249186 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 ignores property UNUSED_PADS_IGNORE7 G9 i8 U3 W- d/ y( K
1249272 SIP_LAYOUT IMPORT_DATA film resistor pins/pads are created on the wrong layer. Always synthesized on top cond layer regardless of config file
! @0 g, k" c; {( G3 Q! U1 J; G) ?1249792 ALLEGRO_EDITOR INTERACTIV Cannot place rectangular shape as per included width and height.- }" K5 c2 m; A+ _* d4 \
1249801 ALLEGRO_EDITOR INTERFACES Bug - Arcs in IPC2581 export are corrupted
( [7 @9 h, o# o1251006 ALLEGRO_EDITOR INTERFACES IDX does not recognize PKG_PIN_ONE property
% R ^9 @2 F4 R2 f7 W1252142 ALLEGRO_EDITOR INTERFACES Remove inappropriate Conductivity specs from the dielectric layers from the IPC-2581 output
- w) b& ?9 l' W" T1253047 ALLEGRO_EDITOR SCRIPTS Bug: SAV file when creating symbol' d0 \6 `& P7 H0 }
( z1 u' O7 M9 d4 l" D7 ]DATE: 03-13-2014 HOTFIX VERSION: 025* m3 h, X( R/ {- s
===================================================================================================================================; z$ p9 K- O& {# ^5 L& ?6 A
CCRID PRODUCT PRODUCTLEVEL2 TITLE9 N1 g ]- k7 \" x
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1194646 CONCEPT_HDL GLOBALCHANGE Global Update > Global Component Change does not work" b j' O7 a1 I! b
1227843 SIG_EXPLORER EXTRACTTOP Cannot extract the topology correctly.- i' n1 w1 {$ p
1231510 ALLEGRO_EDITOR INTERFACES IDX exchanges with CREO 5.0 issues+ H! [+ H% N; N1 n4 ]: r" c
1233030 SIG_INTEGRITY GEOMETRY_EXTRACT Net Parasitic of ground Connection: w; r" t! {+ z3 E# v# `2 C
1236961 SIP_LAYOUT OTHER Moving component using Place Manual -H causes mirror_geometry., S- e( }& Q! o$ i
1241456 ALLEGRO_EDITOR EDIT_ETCH When creating Die pins or changing their attributes an oval is placed on the pin$ o2 [# Y; U+ D! F1 _5 S0 @2 }
1242461 SIP_LAYOUT OTHER SiP Layout - DIE is being mirrored when placing" e$ C l2 F0 ~0 v4 \( V" L' a
1242682 CONCEPT_HDL PDF PDF Pubisher crash DEHDL on design( a) o( D! r4 o6 J* p( n6 ~
1242685 SIG_INTEGRITY SIGNOISE Incorrect net name was displayed/output if the net include consecutive underscore.% l8 n! i7 C" ]/ f
1243357 ALLEGRO_EDITOR INTERFACES Ability to add any new name* O1 G& s/ a* p3 U, @: Y
1243758 ADW COMPONENT_BROWSE I don't see an option to switch between database and cache mode
1 K/ i7 x u8 i! v% V1244325 ALLEGRO_EDITOR INTERFACES Merge all the BOMItems with same part number into one single entry in IPC2581B.
+ s5 p0 H+ |2 ]& C* P6 Q1245363 CONCEPT_HDL CORE Design Entry HDL program crashes upon save k( L2 [& m7 I/ Q# Q# H2 R
1245790 ALLEGRO_EDITOR PADS_IN Bug: PADS Translation with 16.6s023 gives parse error, ~. W- `- `' [ W- v
1246343 ALLEGRO_EDITOR SKILL axlAirGap command is broken in s022
$ F; I+ S1 {7 W. t7 T+ J# D4 n1246419 CONSTRAINT_MGR OTHER Netrev fails with SPMHGE-268 on existing design
( Q) m( U5 b! U- J/ H* ^; v: _7 K1246878 CONCEPT_HDL CORE Changing Symbol in Variant Editor makes schematic page crash3 R6 I+ i- q3 L0 ?& t
1246884 ALLEGRO_EDITOR GRAPHICS Infinite cursor disappears from the canvas after step package mapping GUI is closed.
% A8 X) f4 E6 \/ T! r7 ?. W. \1247016 ALLEGRO_EDITOR INTERFACES STEP Model of connector cannot be zoomed sufficiently after mapping it to symbol dra file.
7 ?! [: B% d; e* t4 O- G/ s6 M1247107 ALLEGRO_EDITOR INTERFACES Incorrect Spelling in IPC-2581 EntryFillDesc field) S7 R) R/ k% q5 }
1247177 SIP_LAYOUT WIREBOND Bondfingers not aligning to wire when tack point on the other wire end is moved from center+ m6 F* v% g9 Y1 L
1247400 ALLEGRO_EDITOR INTERFACES option to Export optimized PDF in color, V. O0 r$ Y& _, `; A4 `
6 {* }' T+ a! d H. q" q6 w$ kDATE: 02-28-2014 HOTFIX VERSION: 024
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+ m3 x: `/ U" W j1207753 CONCEPT_HDL OTHER The Variant Name with a dash is represented by #2d) o, I( Y: f f& t
1234991 ADW TDA Team Design does not remove deleted page files from zip files f! n( F8 P2 Z
1235919 CONCEPT_HDL PDF DNI crosses are not printed on the correct components. g* K- g/ |% Y
1238007 ALLEGRO_EDITOR PARTITION Import partition removes properties from RKO that were on the exported partition
2 c' ?: N; W$ F' B/ c$ d+ R2 e1238140 CONCEPT_HDL CORE Design Entry HDL Crashing) p% n3 k' k8 a
1238195 ALLEGRO_EDITOR DATABASE Via's losing net idenity after being mofifed or replaced." G* T- w: A& Y' _& v- k2 C
1238478 ALLEGRO_EDITOR ARTWORK IPC-2581 negative artwork layers does not recognize shape bounding box value
, t3 t8 L! b, ?; ^8 z, Q1 A7 x1238483 ALLEGRO_EDITOR ARTWORK IPC-2581 not drawing negative artwork correctly with traces in voids.
$ O+ z- m4 k, q8 u' R' \1239070 SIP_LAYOUT WIREBOND When importing wirebond data onto a Die rotated 90 degrees the WB data is placed in the wrong locations
( ^- j R- [% y% J1239433 SIP_LAYOUT WIREBOND Need the Wirebonds to lock to the die aftter importing wirebond data0 {) p; \$ C5 j1 x" t6 }9 F3 [
1239952 ALLEGRO_EDITOR SYMBOL Allegro crashes with a component rotation of 45 or 135.
/ E: I( Z, G+ u6 l+ r' K; E1240205 SIP_LAYOUT DIE_EDITOR Crash occurs when trying to "oops" for a moved driver in co-design die editor in SiP
, o# Z$ j6 i8 D Z7 m1240288 ALLEGRO_EDITOR INTERFACES Why are some of the mechanical holes not showing up in Step output of thi design, while others are ?+ d/ {! f" r0 b
1240305 ALLEGRO_EDITOR INTERFACES STEP Export gives some errors which are not documented; O: o5 `' L) a: H
1240425 ALLEGRO_EDITOR DATABASE Export ODB is not working on 16.6 HF 22
' A1 D: m8 I. j1240879 ALLEGRO_EDITOR NC NC ROUTE file is not correct using hot fix 22 of v166# `1 K: w4 x7 f! S9 S
1241904 ALLEGRO_EDITOR INTERFACES IDX baseline import displays false DRC with Package_height Offset until DRC update is run.7 L. f% \8 w7 v& G
1242266 ALLEGRO_EDITOR INTERFACES IPC2581 crash on HF22 and HF23
$ u' C* G4 b/ `' [' C& a9 X: C1242433 ALLEGRO_EDITOR INTERFACES ipc-2581B incorrect LayerRef values in BOTTOM side RefDes elements
2 S7 i% q! W4 G9 `1242988 ALLEGRO_EDITOR SKILL Allegro crashes on skill command axlDesignFlip8 o! X1 X6 y, d0 |7 F. ?
1243845 FSP FPGA_SUPPORT FSP design created in 16.6 s018 will not open in 16.6 s021
7 L9 K$ a+ f2 p5 Z6 d
7 I% N( u: U" F, F6 C2 _- [DATE: 02-14-2014 HOTFIX VERSION: 023 x4 L. V2 T$ S
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
( ^$ H/ ]6 y0 b7 L0 M) M1202715 SPIF OTHER Objects loose module group attribute after Specctra' w7 v& \; f" z# e
1203443 ADW LRM LRM takes a long time to launch for the first time H( ~1 ]2 [6 K
1207204 CONCEPT_HDL CORE schematic tool crashed during save all& R: ?+ b0 g$ j" ~5 i
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter$ D0 d, t9 W& W7 n
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA
. I9 S# o3 K. C1 w! w1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side) o6 O0 L) o8 @3 s' T
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr n0 J+ Z, _& v
1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.) V$ M. y3 z9 B/ b4 A# Z
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
l8 g8 m5 C% G; {8 U! B' Y# h1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.* l+ N5 M& t7 a3 s
1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
5 F2 d! _2 v; P9 h. F" ?( y T1 y1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's! O# u3 }( q7 z7 |* g. [7 m7 d, Q4 t
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
- w9 ]) l, Q; ~5 s: j1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes* J) z4 ]) y& x4 J) ?
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form
8 Y6 g0 E: N$ t" i) r; x1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.' v* S# T& {: D+ x' W
1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
2 c" Q# }( w5 W+ F. Y1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
& U% F' {' Y- m: ^" a/ {2 B1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.2 t# J( m+ L- m; O; O/ B8 D9 R
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol, L/ A+ z! `; @, Q- \ f# C
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
2 b) [1 E" N/ v7 v/ G3 k, A5 x/ I4 H1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File, A f8 ~4 f. J1 G# X
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat
( [' ~1 }# o$ l! v3 ?8 _0 W5 X b f* E6 u$ ~: z. `
DATE: 02-7-2014 HOTFIX VERSION: 022
5 B. w& ^( |6 ?( L! J===================================================================================================================================
: ?5 r) h) r2 p9 J8 JCCRID PRODUCT PRODUCTLEVEL2 TITLE
9 o) `3 v1 _! l2 M9 S& p$ C* z===================================================================================================================================5 f) F' G2 p. e, A$ W7 B
192358 ALLEGRO_EDITOR PADS_IN Pad_in does not translate some copper shapes- g; n) `! C5 n/ a( a% z
222141 ALLEGRO_EDITOR PADS_IN PADS_IN: Extra shapes are created when importing PADS design9 d; g, G5 \/ k3 j# @, ?0 T
274314 ALLEGRO_EDITOR PADS_IN PAD_in boundary defined for flooded area be translated DYN8 L8 ?( i# L! A" H' j2 u
413919 ALLEGRO_EDITOR PADS_IN pads_in cannot import width of refdes.
. I& j2 H8 q$ f/ _7 k3 y3 C609053 ALLEGRO_EDITOR PADS_IN "Mils to oversize" of "pads in" did not work correctly for MM data.6 J7 h. d" P% W N
666214 CONCEPT_HDL OTHER Option to increase Line thickness in publishpdf utility/ y, r" d" a2 ^$ ^7 x
738482 ALLEGRO_EDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphics card6 d2 l: g) h; d7 G* E* X
982950 CONCEPT_HDL OTHER change the mouse button for the stroke to have same function with in pcb editor7 A# Y7 C! v/ P- M& F1 ]% L% h3 U
1020886 SIP_LAYOUT LEFDEF_IF a quicker way to promote die pins (by importing macro_pin list)
, @! e) V7 {5 I1032678 CIS VIEW_DATABASE_PA View Database Part gives incorrect result in complex design with variants.* u1 b) V* j/ x( p1 _
1033864 ALLEGRO_EDITOR PADS_IN pads_in doesnot translates teardrops present in design" E/ Q7 ]1 }+ z+ `5 J+ Y
1054862 CONCEPT_HDL OTHER Option to increase Line thickness in publishpdf utility
( l+ x: ^3 p8 H( \: W& a" x1055252 FSP PROCESS Add a synthesis option to target a group to contiguous or consecutive banks
' Z2 o. R9 R- O1 z; n1100772 CONSTRAINT_MGR OTHER In Constraint Manager > DRC > Spacing the Show Element DRC totals are wrong., J2 B% W6 ~# ^& J2 b# O8 b4 K
1135020 CIS DESIGN_VARIANT Variant list is showing wrong results for hierarchical designs
4 Z/ m, c2 {" Q! [! R1138951 SIP_LAYOUT DIE_ABSTRACT_IF Fix die abstract r/w to properly support pinnumbers on ports3 ?5 G% s2 B4 J+ { }6 w# v( ~! n9 J
1140042 CONSTRAINT_MGR OTHER Diff_Pair lengths and analysis are lost after closing and opening Constraint Manager." h( U4 O# D k8 K+ k1 S
1143662 ALLEGRO_EDITOR INTERACTIV Enhancement Request for RMB - Snap Pick to options increased to include Pin edge
, Z. g. p1 n; ]5 c* u1147961 PSPICE SIMULATOR Simulation produces no output data
, B2 {$ A8 O9 p2 t5 `1150874 ALLEGRO_EDITOR PADS_IN Dimensions in PADS are not translated correctly during pads_in translation
3 m+ k- B) K O; `: @6 b1154184 CONSTRAINT_MGR CONCEPT_HDL Difference in the way topology is extracted in 16.3 versus 16.6
% u0 s6 {- M% F- J1154770 CAPTURE PROPERTY_EDITOR Variant Name property doesn't show value in Variant View mode, W* D+ m% K# l7 g, @1 d+ z
1158350 CONCEPT_HDL CORE Need a warning Message while importing a 16.3 sub-design in a 16.6 Design
5 j5 F* X7 S$ e/ p- | D! u/ P4 D1162347 ALLEGRO_EDITOR EDIT_ETCH Enh- Allow new option in Move command such that it allows stretching etch using only 45/90 degree segments directly5 Q4 Z7 M' l5 }
1165553 ALLEGRO_EDITOR INTERACTIV Subclass list invoked from the status window does not represent correct colors.' a; s0 ?. V' w+ G. c4 J
1168079 FSP MODEL_EDITOR Clicking OK or Save As in rules editor allows user to overwrite the master with no warning
+ q; W" [, k6 \. l4 D1172043 SCM OTHER : in pin name causes SCM to crash1 Z f+ l# D, @, L2 F3 w/ {5 t7 @
1172207 CAPTURE STABILITY Capture crash while adding new part from Spreadsheet
& L( ? f; b% f. p m0 d1172743 ADW TDA Allowed character set for the check-in comments is too limited
8 e9 C4 ]$ }/ k1 G# k2 j2 S1174099 SIP_LAYOUT WIREBOND Option to reconnect wire based on 縫in name� in the Wire Bond Replace
; y& u, o& v# d/ C- e1177672 APD IMPORT_DATA Netlist-in wizard didn縯 provide detail information about what columns have been ignored by import process
* c/ z4 b! |0 W+ C' B2 d, o7 ]% _1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATION property can not be set to invisible
4 |$ Y# h, G u2 b- \. z1177820 CONSTRAINT_MGR INTERACTIV Done the Allegro command when attempting to launch CM/ o8 ]' r4 _0 c3 ^& Y- E8 K2 \
1178586 ALLEGRO_EDITOR EDIT_SHAPE Number of digits displayed after the decimal point of Shape Creation function does not match the Accuracy of BRD
% c7 C' N2 u+ G9 @1179688 PSPICE STABILITY pspice crash for particular HOME variable vlaue
) K& w- r0 C, Z0 i2 L& w1179827 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to Symbol export - enable field to add Keywords for data fields to excell cells7 t6 n! \3 J8 F
1179879 SIP_LAYOUT STREAM_IF Data file corrupt when exporting Stream data from SiP database.
- E5 a1 e4 w1 I- q1180164 F2B BOM BOM csv data format converts to excel formats
B5 [$ h a0 f6 G2 |1180477 ALLEGRO_EDITOR INTERFACES IPC-356 output is listing a duplicate location in the comment section( b" f& y i- C/ k- k
1180932 SIP_LAYOUT OTHER SiP Layout - Symbol to Spreadsheet add option for writing to existing spreadsheet5 k0 L- h; J; \ S/ C1 I
1181377 ALLEGRO_EDITOR INTERACTIV Pick Releative does not work correctly with RMB-Move Vertex
w; i4 A4 i v6 o1 n1181516 ALLEGRO_EDITOR DRC_CONSTR Getting a "Thru Pin to Route Keepout Spacing" when there should not be one.7 Y# b/ \5 |9 K
1181739 GRE CORE Running Plan > Spatial crashes GRE0 Y# B5 u5 q2 b+ z& C. k
1181935 ALLEGRO_EDITOR DATABASE Enh. Property that allows internal C-C DRC errors$ s( F5 W j4 d5 x3 U# T
1182185 SIP_LAYOUT OTHER SiP Layout - Import symbol spreadsheet - suppress Family for the font in the XML spreadsheet! h" |. e3 K. t. G& N
1182566 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to symbol - Enhance ability of spreadsheet exchange to allow for a portion of a full pin map
- w3 i& Y/ M" C. c1182599 CONSTRAINT_MGR DATABASE CM Prop Delay Actuals do not update after Z Axis option is turned ON or OFF and Analyze is run.
! ]; N& p! k2 D7 A) y5 g# [5 x1182892 CAPTURE SCHEMATIC_EDITOR Pspice marker rotation before placement
. w" K( T5 o- r3 x7 v% ~$ b1183682 ALLEGRO_EDITOR DRC_CONSTR Implement Nodrc_Sym_Pin_Soldermask & Nodrc_Sym_Pin_Pastemask to symbol level
$ X# _% h8 G0 K. [1185445 SIP_LAYOUT DIE_ABSTRACT_IF Die abstract export needs to be able to select xda file type when browsing/ s% U8 r3 `/ M9 n; N* f* C
1185932 ALLEGRO_EDITOR SHAPE Soldermask in solder mask void DRC
3 ?: v4 D" B* N0 K5 ]/ q6 |- t1185946 CONCEPT_HDL CORE Ericsson perfomance testing report 5 sept 20132 G* s3 M; F4 W( r+ Z9 o
1187213 FLOWS PROJMGR Unable to lock the directive: backannotate_forward
/ {* T( d- @: O- e% [& M& s; B1187444 ALLEGRO_EDITOR DRC_CONSTR With this design Database check prompts error "SPMHGE-47: Error in call to batch DRC"( ]& p8 p; n9 }# I. ?% J( J* ~
1187597 ALLEGRO_EDITOR DRC_CONSTR No Package to Package Spacing DRC error, when symbol overlap sideways at 45 degree.
d T) z6 }. g) J# n/ }' n1187723 FSP PROCESS Synthesis can fail depending on component placement
2 Z( ~6 J. v- A/ R9 i9 {1188164 SIP_LAYOUT OTHER SiP Layout - Spreadsheet interfaces Import Export and Add Component - include Keyword for NET_GROUP8 n$ T2 f& r' q8 w2 e+ n
1188245 CONCEPT_HDL CORE INFO(SPCOCN-2055): You cannot run the CHANGE command in a read only schematic
/ G. M+ ]& _. m3 |1190927 CONCEPT_HDL CORE Check sheet does not report shorted signal/power nets if power symbol is connected to a pin- f9 \4 P9 x# u
1191497 ALLEGRO_EDITOR INTERACTIV ENH: Adding names to the text block parameters numbers
1 _0 k* j( k: l+ s1192005 SIP_LAYOUT IMPORT_DATA Import SPD2 is missing 1 smart metal shape from file
: l/ M8 I0 e7 ?% T$ G' }1192204 ALLEGRO_EDITOR EXTRACT Need ability to extract vias that are labeled as microvia
% b8 Y! h( ~5 G8 j5 W; L1193063 ALLEGRO_EDITOR MANUFACT TestPrep log displays "Pin is not accessible from bottom". The component is through hole.
/ G" A! p; ]- n: y# n) r1193418 ALLEGRO_EDITOR GRAPHICS 3D Viewer can`t export image in both SPB166S015 and SPB165S047
/ `) l7 o# ~# @5 k0 O% r6 r1194305 SIP_LAYOUT EXPORT_DATA export package overlay creates file with no package info$ n) ?2 o1 x% [$ U5 Y$ u
1194418 APD IMPORT_DATA issue when do File->import->netlist-in wizard* b- L9 Q+ O7 \. b, p) Q# _$ H
1195279 F2B PACKAGERXL Ptf files are not being read when packaging with Cache
/ m+ X/ G3 T* o! D8 @. a& s1195374 ALLEGRO_EDITOR INTERACTIV Modules are not showing up in Tools > Module reports3 \# k9 w8 [+ M- ~
1196603 SIP_LAYOUT EXPORT_DATA Change form for "Write Package Overlay..." to better support longer lists of routing layers
2 f: Z" g4 ]- C; Q8 S1197302 CONSTRAINT_MGR UI_FORMS Inconsistancy in selection of object for Spacing Constraint Worksheet$ v" P3 |7 d$ V0 f3 n9 Y$ r
1197399 CAPTURE OTHER Draw toolbar disappears when using Print Preview
! g% k! P. j9 _: Q. I) C* i1 T) o1197543 ADW TDA TDO does not correctly show deleted pages
" t5 p/ w2 _+ d+ v G1 T1198033 CONCEPT_HDL CORE Signals do not get highlighted when Show Physical Net Name is option enabled$ Y w- m8 o/ s7 F8 \0 d! }& j- r
1198468 ALLEGRO_EDITOR GRAPHICS 3D_step model does not show the correct view in 3D_Viewer when symbols have multiple place_bounds. Q) y! z4 O5 F5 t( m2 G
1198617 CIS GEN_BOM Mech parts are showing with Part reference in CIS BOM! W) L; g0 @, C9 ]4 R7 Q8 @$ H7 g' Y5 O
1199764 ALLEGRO_EDITOR SHAPE Allegro crashes when trying to delete small island on POWER layer.4 Y( ?2 y" D" e4 g
1200232 ALLEGRO_EDITOR INTERACTIV Moving all items including board outline which is made of lines does not move the board outline in General Edit Mode.! v6 |; ? L" O- {. Y
1200748 ALLEGRO_EDITOR INTERACTIV Additional pin edge vertex object to snap pick4 n% Y+ L( D4 e5 I8 X; m! ?3 Z
1201056 ALLEGRO_EDITOR DATABASE Unsupported functionality strip design creates a .SAV file, [- [3 J/ X6 `, X; |) A
1201638 CIS PART_MANAGER Part retains previous linking inside the subgroup
0 q2 B6 E: g- y1201834 ALLEGRO_EDITOR PLOTTING Bug: Import Logo command changes resulting imported object' V2 U! z6 I$ j- g1 u
1202406 SIP_LAYOUT OTHER enable the dynamic display of component pin names for co-design dies in Sip Layout
% d% ^0 T K, K2 w2 A9 A9 E7 ^1202431 CONCEPT_HDL PDF The publishpdf -variant option should have a "no graphics" option
9 g' m$ i$ M% o. m. X1202717 ALLEGRO_EDITOR DATABASE About Warning(SPMHA1-108):Illegal line segment ... end points.
+ Z" O1 j" c' a2 f% L) S1203459 CONSTRAINT_MGR INTERACTIV Object Report has no mechanism to output information for a specific design.5 L- u5 l. F0 F9 r" _
1204544 F2B DESIGNVARI Variant Editor does not warn on save if no write permissions are on the file/ ~! N' C# `5 D' r5 z
1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDL syntax* a0 h, Z! \5 G1 O
1205952 ALLEGRO_EDITOR GRAPHICS Step Model for Mechanical Part is visible in 3D viewer only when Etch Top Subclass is enabled# {" R) ^# i- S, p
1206103 SIP_LAYOUT IC_IO_EDITING add port name property to pins, and add Skill access I/O driver cell data- u5 {6 ^9 [+ U" [& J; A5 M" K
1206546 CAPTURE ANNOTATE User assigned refdes are resetting when 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�
/ W& w) d ? h8 I/ w1206561 ALLEGRO_EDITOR GRAPHICS Not all mechanical symbols made with Step files are displayed in the 3D View" X1 b, t n; Z6 r2 c' L9 ]
1207125 SIG_INTEGRITY ASSIGN_TOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus
1 p$ P1 b( p: n9 G% Z, j1207386 CAPTURE GENERATE_PART Altera pin file not generating the part properly8 u3 c5 N5 o9 ]. P
1207629 CAPTURE TCL_INTERFACE Bug: GetMACAddresses tcl command not working+ e9 i2 j6 r& B* p. h
1207994 CAPTURE TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pins with black color/ X( S4 ?; A4 v7 z
1208017 F2B DESIGNVARI sch name is not same when updating Schematic View while backannotating Variant& O2 B4 x; N! I& r7 H0 @& X8 U
1209363 ALLEGRO_EDITOR INTERFACES When placing pins using the polar command the tool returns 4500.00 for 45 degrees.
4 t/ z* D% e$ _& I. ?3 c4 Z1209769 CONCEPT_HDL CORE Top DCF gate information missing }) Y8 c& S+ K! o
1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box
3 x P X) R1 T) Z5 s4 \/ x) C1210442 CONCEPT_HDL INFRA Save design gives ERROR(SPCOCN-1995): Non synchronized constraint property found in schematic page
- u U* H& {- d G9 L7 B9 s1210685 ASI_PI GUI User can't edit padstack in PowerDC-lite' |" T/ X7 ~4 t7 Z0 c
1210744 SIG_INTEGRITY SIGWAVE SigWave: FFT Mode Display unit seems not to be correct
' L5 Z5 p2 p! Y6 {, y5 k1210829 CAPTURE NETLIST_VERILOG Shorted port is missing from verilog file
3 o! }! T ^) Q9 g1 \/ o) a- c1210850 CONCEPT_HDL CORE DE-HDL backannotation crashing after instantiating specific cell from Ericsson BPc Library
( w- q9 e, }! W j$ Y1211620 ADW COMPONENT_BROWSE Component Browser Performance# T6 S! a$ C& {( x2 ^( ~2 P* C
1212102 ALLEGRO_EDITOR INTERACTIV Shape edit boundary adds arc mirrored to the highlighted preview.
& Q- j3 `! z1 n/ D1213294 CONCEPT_HDL SECTION DE-HDL windows mode multiple section fails to section first contactor pin from column of individual pins
V( F+ N; a! }' o. ^' G$ S1213402 APD DATABASE The old "ix 0 0" fix is now causing the features to lose nets entirely.
3 l/ M' Y; x$ C8 @! p1213694 ALLEGRO_EDITOR PARTITION Via connected to Dummy Net pin in Partition gets connected to shape on the board after importing partition- N Y, E1 b7 e- Q8 o
1214247 CONSTRAINT_MGR UI_FORMS Selecting the "All" folder in Spacing Constraints in CM does not automatically select the first column for editing9 `( I M" ^2 N+ L+ g- v
1214320 SIG_INTEGRITY SIGNOISE signoise command with -L and -k option0 I2 ?% J" I1 H! l, d8 p+ H7 s
1214433 CONCEPT_HDL CORE Genview does not update sym_1 with ports added to the schematic# r! x9 p6 m; A
1214909 ALLEGRO_EDITOR NC NC Drill Legend show extra rows for drills9 n9 @" K1 U0 K. [9 L0 O+ @
1214916 SIP_LAYOUT OTHER package design integrity check for via-pin alignment with fix enabled hangs
# R( G v4 j% E% t1 \5 }1215954 SIG_INTEGRITY SIMULATION Cycle.msm does not exist error when simulating extracted net5 o, m0 I! e# M( X
1216328 CAPTURE STABILITY Capture crash
1 G/ l C a9 u0 a$ `1 g* h8 S3 k- k1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.049' x i1 W8 I; i! X: e# `
1217450 F2B BOM ERROR 233: Output file path does not exist
. X" P. S+ g$ `: }1217612 ALLEGRO_EDITOR INTERACTIV Replace padstack will not replace padstacks that have multiple alphabetic characters in the pin name - AB21-AB37
# x0 n @! ^) {3 K& q) J" O) ?1217823 ALLEGRO_EDITOR INTERACTIV Compose shape fails with SPMHIS-473; P( G! K n/ P: |$ _
1217887 ALLEGRO_EDITOR INTERFACES An undo option to be made available in the STEP Package Mapping window! C2 k- P+ u3 @; V$ p9 U
1218665 ALLEGRO_EDITOR INTERFACES In step viewer, the bottom side parts are placed above the pcb board surface1 U8 ?% o+ N' }+ J- i
1219053 PSPICE PROBE PSpice crash with the attached Design
! l0 J2 J( p( O. m0 y1219067 ALLEGRO_EDITOR EDIT_ETCH dynamic fillets behavior is unstable
! d8 o+ f: W% I/ Z$ N1219095 ALLEGRO_EDITOR MANUFACT Design Cross section chart is tapered for two layer board
5 ^% D# N) l! H" @ u. u1219126 ALLEGRO_EDITOR SKILL Skill issue with axlRefreshSymbol()
! {% v2 D3 ~# B* u' s. T1220701 ALLEGRO_EDITOR INTERACTIV View > Windows > Worldview (showhide view command) fails with command not found/ H, |' X# ?* T! S4 P# \1 s2 _! l4 ]
1221057 ALLEGRO_EDITOR REPORTS Units in Cross section report for spacing is not synced with the design
* b! C3 H, w- v- j, s1221139 ALLEGRO_EDITOR EDIT_ETCH Delay tune is not tuning differential pair, W( B0 a. i1 r+ U" b A# S( B$ @
1221157 SIP_LAYOUT IMPORT_DATA import spd2/na2 file is not importing data correctly into sip$ b1 [; \+ j: C7 P- Z
1221163 SIG_INTEGRITY GEOMETRY_EXTRACT Simulation aborts with severe convergence issue when coupled vias is enabled.
: A- x' b0 ^5 v9 M5 b+ W) h2 @$ Q# D1221416 ALLEGRO_EDITOR DATABASE strip design for function type
* s. J& V, w2 C$ d0 i" {& k, T1221931 ALLEGRO_EDITOR DATABASE Fatal software error when embedding component& K/ k, P8 o1 ]6 g
1222105 CONCEPT_HDL CORE Moving Pins around the edge of a Block causes the text of the pin to change its text size.! c6 `" q' F b, w" F' h
1222124 APD DATABASE Same Net DRC's exhibiting inconsistent behavior.0 m# F f1 y% p2 A& V
1222272 SIG_EXPLORER EXTRACTTOP Cannot extract net or open SigXplorer after selecting a netgroup o$ {5 n/ V3 A/ y
1222329 ALLEGRO_EDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top$ ?. ~- l" U8 ^- {# i
1223183 SIP_LAYOUT BGA_GENERATOR Getting an incorrect error message when using the BGA generator with a long BGA name.
+ q: V* r! h4 p7 H4 U5 o4 o1223662 ALLEGRO_EDITOR REFRESH Allegro crashes when trying to refresh symbol% { S- h- ~2 E
1223932 CONCEPT_HDL CORE DEHDL block desend does not find 1st page if its not page19 x& z7 j+ e% u& K( a7 D
1223940 CONSTRAINT_MGR UI_FORMS Unable to change CLOCK name in Setup/Hold Worksheet under Timing in CM.. T5 t h9 z$ `* S9 @6 Y& B$ I
1224127 SIG_INTEGRITY IRDROP Is the old static IRDrop in 16.6 officially supported?9 ]+ S3 \$ M. V( c q1 x# |- V; X
1225492 PCB_LIBRARIAN CORE PDV expand vector pins resizes symbol outline to maximum height again
3 @+ v! s% J1 V& s- }! r% I; m1225546 CONSTRAINT_MGR ECS_APPLY nets where the referenced ECS maps correctly in constraints manager for front end but not in back end
/ w- Y0 S1 F& X! p# P3 g% ?# ^: c1226405 ALLEGRO_EDITOR INTERFACES File > Export > IDF ask for filter config file eventhough it is created in same session and stored in parent folder; f0 A$ ~- P1 F( x
1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDN Analysis with XL and GXL2 u2 V2 p6 r$ }! W. A
1228721 SIP_LAYOUT OTHER File Export Netlist Spreadsheet enhance sort to be a natural method per Jedec according to customer
; e# ~ c% n6 k1 w! n( x
7 w: E3 W: z6 u3 g+ }DATE: 12-20-2013 HOTFIX VERSION: 021% D" n3 e0 d3 ^; N$ W' A4 k. O1 h
===================================================================================================================================0 A9 o2 K% C6 n/ i
CCRID PRODUCT PRODUCTLEVEL2 TITLE' U6 {; C, ]2 O) {; E# [7 \ x
===================================================================================================================================
; A* L, n+ i' v0 o6 I" L1214932 ALLEGRO_EDITOR OTHER Allegro will crash when performing show dimension on linear dimensions.
& H& e; Q+ D$ u) y+ K1215045 ALLEGRO_EDITOR SKILL Successive file open / ipc calls crashes Allegro 16.66 g/ C8 Y7 h. p" ^4 q7 O2 O+ _, |
1215115 ALLEGRO_EDITOR NC drawing name doesn't display in the ncdrill.log file+ y- Q7 G; |- x+ w; M4 \2 m
1216028 SIP_LAYOUT PLACEMENT Design will not update embedded component symbols.
$ x7 R0 b- _7 O1 ^1218451 ALLEGRO_EDITOR DRC_CONSTR Route Keepout to Pin DRC created even after adding Void in RKO shape
4 N& C- k/ u. A7 n% J1218636 ALLEGRO_EDITOR SCHEM_FTB netin process will rotate embedded symbols: |* S3 Y& Y& U# N' J
1218706 CONSTRAINT_MGR CONCEPT_HDL NCC associations get deleted from FE CM- }! ^0 i' f; i1 [
+ n7 K3 q! W! o3 i/ z$ o/ C
DATE: 12-4-2013 HOTFIX VERSION: 020
' g- y3 s' {: s( [) F! ]===================================================================================================================================
. T4 w, Q8 _+ {& n7 o) d# ACCRID PRODUCT PRODUCTLEVEL2 TITLE: @% p1 y( x; `3 k1 M
===================================================================================================================================; |# K8 [% `4 N. {9 W
1116426 F2B PACKAGERXL Packaging in 16.6 increased by 3 folds compared to 16.3" X3 ^& F% H; @- a0 B5 Q( {
1190095 CONCEPT_HDL CORE In Windows mode select the part and click on version placed selected version +1.
) e2 P' c0 Q5 z9 k" M1199410 CONSTRAINT_MGR CONCEPT_HDL Constraint Differences Report window hangs in 16.6-s016
2 N4 L4 q, m3 \/ j3 [- a1 i# E- g1199425 CONSTRAINT_MGR CONCEPT_HDL Import Physical fails (the cmfeeback.exe has stopped working) in 16.6-s016
9 s3 t4 V5 R# K9 f( q8 d: Q; A1199700 PSPICE NETLISTER Netlist fails on addition of netgroup; d5 u# d* W& }0 }
1200936 CONCEPT_HDL PDF publishpdf fails if UNC paths are provided from the command line
J+ D8 S% f9 x0 S, U1202391 CONSTRAINT_MGR OTHER Getting 'An Invalid argument was encountered' when generating Net Class-Class report in CM
/ S p' s" E1 j M1202587 CONCEPT_HDL CREFER Crefer schematic reports cannot be deleted on Linux.
7 L$ V' g; [, i# F3 Y1203143 GRE CORE GRE crashes on running Plan > Spatial) v* F8 C; r2 q" z
1206019 ALLEGRO_EDITOR INTERACTIV Allegro needs to be restrated to read steppath with 16.6 S017
. O i% a* S7 |. Q2 t, l1207050 ALLEGRO_EDITOR INTERACTIV Refresh Padstack fails on Warning
/ Y/ T! P2 {) j/ O# J0 x- Y8 h1207178 CONCEPT_HDL CORE Aqua color on wire does not matches icon color8 U' p8 S" Z" f6 A1 e1 s5 d+ b/ U: D
1208152 F2B DESIGNASSC ERROR: Dictionary File: cmdict.l could not be found
1 h4 ~5 S% y: @' S* N5 F# b! S1208276 APD STREAM_IF Stream in fails to import what Allegro exported
# K" m2 D# ?/ w4 h1208345 ALLEGRO_EDITOR SKILL Why axlChangeLayer not working for shapes on this attached skill file?
! B0 B1 n8 v5 i8 L* n1208351 ALLEGRO_EDITOR SKILL axlFilmCreate do not define the IPC2581 domain correctly.
/ S' s7 Z- @' T: T4 W$ w+ r# M1208467 PCB_LIBRARIAN VERIFICATION con2con mangles cell data after checking cell having syntax errors on part_table* S' F; S( d2 J- q3 w1 C
1208579 SIG_INTEGRITY GEOMETRY_EXTRACT Incorrect traces are extracted when void area is less than anl_min_void_area setting
: J7 C; S. p/ A/ r+ c! u9 E+ _( X1209347 ALLEGRO_EDITOR PARTITION Import partition that has diametral dimensions will crash Allegro' U: a1 l% ~- R$ `! x, ^
1209897 ALLEGRO_EDITOR PADS_IN Pads_in will not translate design.
; H' ~! H: l1 N- E1209902 PCB_LIBRARIAN CORE PDV crashes reading part
! r: e0 k; b" z* B: J3 A- M( s9 j1210183 PSPICE SIMULATOR SimSrvr crash with ORPROBE-3211 RPC Server unavailable Message+ \9 u# x- M/ w
1210408 ALLEGRO_EDITOR EDIT_ETCH AiBT hangs when doing interactive breakout on bundles using latest hotfix.# v! ^/ ^; ]1 Q1 l: E5 _$ ~" {
1210443 ALLEGRO_EDITOR INTERFACES Allegro Design Publisher does not create fully searchable PDF for some of the text that are present or certain layers
# t; u/ q7 n5 B$ j* Y; y. p1210876 CONCEPT_HDL ARCHIVER Archiver wrongfully deletes directories.& P4 i+ o. K8 r; c! `
1211839 CONSTRAINT_MGR DATABASE Topology can't be extracted correctly.
; M0 z% `( Y" U( `7 s2 m' E# P( \0 n, o1212709 ALLEGRO_EDITOR DATABASE No connect can`t be detected in SPB165S048
# v8 S# z. X1 ^- E1 l0 q1213752 CONSTRAINT_MGR OTHER "Show Constraint Difference Report" option at File > Import > Logic does not retain the last setting
% A7 H1 h2 h# D8 p: X8 \* C
! @, y) h' {1 }6 VDATE: 11-15-2013 HOTFIX VERSION: 0192 t, x' b, m1 J6 q
===================================================================================================================================$ n+ F4 b" f \/ B- D% ~
CCRID PRODUCT PRODUCTLEVEL2 TITLE
, Y. V% @/ M/ [3 @4 s/ I3 h1 G# Y===================================================================================================================================# e9 a- |. y# l' y- L" V$ n
1176155 CONCEPT_HDL CORE Graphics remnants with 16.6 QIR 33 b8 c. a( w# h/ b& J. J, K6 b
1178272 CONCEPT_HDL OTHER Verilog netlist does not include split blocks correctly
! [& K6 s: a0 R$ {. I) C8 F+ ^1190782 FSP FPGA_SUPPORT Support for Altera > 5SGXEA9N2F45 device.
5 G0 P8 ~( b, }/ N. h1194140 ADW LRM SYNC_PROPERTIES is not resolving issues a based sync_properties settings+ }0 V0 Y8 A; o/ Q) m- D
1195744 APD EDIT_ETCH Diff_Pair routing fails on certain Uvias in the pair./ s5 f+ i7 `& t! T" o' R
1196704 ALLEGRO_EDITOR INTERFACES ENH: During ipc2581 export checkboxes corresponding to 縈iscellaneous Image Layers� should automatically get selected
3 L4 N6 o5 O8 r, S; N1198340 ALLEGRO_EDITOR OTHER Multiple -product option on the Allegro command line does not access the second -product
4 L H. h7 P$ c, S7 n1198596 ALLEGRO_EDITOR INTERFACES When copper thickness is increased for the outer layers, step Viewer does not show correct component position.% M9 P. H# H2 }, n
1199673 PCB_LIBRARIAN OTHER Component Browser fails to load footrpints if they are set with UNC path# I) b/ |6 F; N& f; G; g7 D! ^( ]
1199889 ALLEGRO_EDITOR DATABASE Allegro crashing with latest hotfix.
+ s! W2 T+ R9 |2 [1200303 ALLEGRO_EDITOR GRAPHICS 3D Viewer does not update after changing STEP model mapping! h7 t' m( e8 x* |
1200449 ALLEGRO_EDITOR REPORTS Allegro crashes when generating Net Loop Report.
, o; H) g/ n* j1200915 ALLEGRO_EDITOR DATABASE Reducing accuracy of this specific design crashes Allegro0 P- @8 l: h+ x4 J& F; o
1201011 ADW COMPONENT_BROWSE Component Browser crashes in DB mode* N$ N" c1 j2 k6 x4 }
1201376 ALLEGRO_EDITOR INTERFACES Allegro hangs when trying to map a specific STEP model to a package drawing.. H! d& k# A. p e1 V
1201897 SIP_LAYOUT IMPORT_DATA BGA Pin Colors not matching the Colors defined in the Symbol Spreadsheet after updating.
" Y2 n: D/ e/ ~" d: g# d# Q1202709 ALLEGRO_EDITOR INTERFACES STEP File generated from Allegro is not overwritten when the variable "set ads_textrevs
8 v" q+ F# h; j6 q, K1202820 ALLEGRO_EDITOR INTERFACES Different xml generation for same step model on S106 and S017
- i% V7 _5 H( v, H1202842 ALLEGRO_EDITOR INTERFACES Step model invisible for one pin dra in allegro 16.6 symbol editor1 X3 S" F7 U! i U; s
1202983 ALLEGRO_EDITOR SHAPE Shape voiding creates DRC with Route Keepout$ f) s- Q% r$ o. }. Q: t5 X
1203125 ALLEGRO_EDITOR OTHER Exporting STEP file with External copper enabled does not show all copper when viewed with Solid Edge or Inventor4 k( r+ f0 v' `* x
1203236 ALLEGRO_EDITOR INTERFACES IPC2581 output with crosshatched shape is not correct+ L x9 S: a8 ?0 Y9 u1 P9 G* d2 c2 l
1203995 CONCEPT_HDL CHECKPLUS CheckPlus rule, local_signal_no_offpage_body, getting an incorrect failure.
+ L5 I' T. T. q" C" [! y5 m1204629 ALLEGRO_EDITOR SKILL axlUIDataBrowse crashes the editor or returns error
) o: n3 d4 k N# x/ D1204640 SIP_LAYOUT DIE_EDITOR Concurrent co-design update fails/ Y: _% V# ~7 V+ d( ~3 ^7 i
1204881 SIP_LAYOUT BGA_GENERATOR Pin numbers are messed up after deleting a pin at a staggered bga3 d9 Z) `, L. J
1204885 CONCEPT_HDL CONSTRAINT_MGR Cant assign discrete models after the wrong model was removed.8 j5 x7 q. T0 d8 V' `, N- Y1 y
1205374 ALLEGRO_EDITOR OTHER pdf out command creates incorrect drill Symbol Characters placement in pdf file when setting film mirrored.
- @0 y% J. \; {9 K3 l( U1 ]1205729 SIP_LAYOUT DIE_EDITOR update of codesign db fails on exit from die editor
6 ?% n4 G" B, B( j9 H4 M) _9 p1205801 ALLEGRO_EDITOR OTHER Tool crash when do export IPF.0 N9 J! [( \- ^+ j$ ~0 j8 \
1205881 CONSTRAINT_MGR OTHER In CMGR , Objects > Create crashes Allegro
6 B& P) ^4 M0 o; C8 V4 m! H s! o( X; h. t
DATE: 10-25-2013 HOTFIX VERSION: 018
0 ~( y5 r7 J) \! \8 U$ q0 B===================================================================================================================================4 J) c$ r+ |8 A1 B! ]+ y
CCRID PRODUCT PRODUCTLEVEL2 TITLE
, H! ^; ^5 ^& w( q }===================================================================================================================================
! P3 B( @ m! v: P: ]3 j8 [1118303 CONCEPT_HDL CONSTRAINT_MGR can not prdefine default units in HDL$ Y+ J2 X" _0 k" H. P4 N' C8 g
1174901 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl
. ~* h( U- K' a- r" L$ T1176990 CONCEPT_HDL OTHER DEHDL BOM tool doesn縯 see similar names.
8 N! Z7 d; U6 f9 F, `+ S1179665 GRE CORE Plan Topological Crashes after around 8 hours of routing.0 l- F! d7 W5 t8 }" F
1188193 CONCEPT_HDL CHECKPLUS CheckPlus not recognizing PIN as a base object./ h$ }+ S0 L* f8 F( g
1189100 SCM OTHER Replace part in SCM using ADW as library fails- O, ]2 I0 }% O" d I2 j2 T6 ~6 ~
1189507 SCM SCHGEN ERROR(SPCOCN-2009): Package error after second schgen run with Preserve mode.
, ~! ]: ^! l& m0 \& O1192391 CONSTRAINT_MGR CONCEPT_HDL Restore from definition deletes local objects in other blocks: t' O! [3 m" Q" f1 l# ]+ T/ j Q3 {
1194597 FSP OTHER Pin definition problem' r# y# P1 x3 k1 m4 Y8 S
1195202 SIP_LAYOUT LEFDEF_IF Cannot add .lef files in IC Library Manager. Getting warning message WARNING(SPMHLD-52)
+ E/ L2 j0 q' N( D1195309 GRE CORE GRE crashing during Plan Spatial.
; b. R$ e2 k3 F& C0 }1197262 ALLEGRO_EDITOR MANUFACT Angular Dimension created in symbol is placed w.r.t. board origin and angle is blank
' l/ ?; \. m& ` Y2 F2 X- {2 V E1198521 CONCEPT_HDL OTHER cadence DEHDL issue - Note for Hotfix_SPB16.60.016_wint_1of11 o* J+ J& a; ^
1199219 ALLEGRO_EDITOR INTERFACES Question on STEP Model export which uses PLACE_BOUND layer for any symbols that do not have STEP model mapped
; A) B+ }9 ~: ]1199235 ALLEGRO_EDITOR SCHEM_FTB capture's behavior is redundant while creating pcb editor netlist
8 l7 u6 T7 Q# u* t2 Q" ]1199323 GRE IFP_INTERACTIVE Crash when importing logic: H% m# T3 n2 |* V2 m. y
1199368 SIP_LAYOUT DIE_EDITOR Refresh of die abstract in die editor with this design takes over two hours4 \' T. |! U, \% M$ i- z
1199760 ALLEGRO_EDITOR DATABASE Allegr won't display Soldermask Top layer
` E: }/ M: G1 Y) z$ U; Q: z
4 D; ^! j, n& S: WDATE: 10-10-2013 HOTFIX VERSION: 017
/ t! R7 v" p! v===================================================================================================================================
* v4 K& o+ c, O0 r1 f8 u- o# ACCRID PRODUCT PRODUCTLEVEL2 TITLE/ E p( f' p' ], C
===================================================================================================================================( L2 }) }: Y" \9 p* x
735992 ADW LIB_FLOW Create Test Schematic does not use the correct package type
# F: j; b1 X6 `/ ]( ?. Z4 v1121403 FSP PROCESS "Assign to Pin" not getting obeyed by Synthesis.
( b2 x5 m. E/ X6 c/ e1141844 RF_PCB DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing
! Y5 q8 K. O$ `) S& @1 C1169269 ALLEGRO_EDITOR DRAFTING Dimension placed on package symbol moves to different place when it is placed on brd file.4 @: u, v8 J/ {1 j& l7 E1 G8 t
1170488 ALLEGRO_EDITOR MANUFACT Dimension text(on .psm) move to different position, when it is placed on .brd.$ y: b8 q; ?, q; S x5 ]) ^# S
1173345 CIS CRYSTAL_REPORTS Crystal Report - Display Parameter dialog for export option: t4 `4 p5 E7 ?# s5 F' v p+ j2 W
1181759 SCM LVS SCM Crash when doing update all that executing import physical command.
$ J p" O' w# V- T. o1182499 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks (all pins and via) drill.& \9 b5 e) M. @% @0 {6 z
1184682 CONCEPT_HDL CONSTRAINT_MGR Net Constraint not transferring to layout from schematic& x$ u7 a2 C( j
1185524 F2B PACKAGERXL Enhancement User would like notification of pack_short in pxl.log
) Y, [ I9 B' r$ a) O1185902 ALLEGRO_EDITOR SHAPE Update shapes dont clear some diffpairs in HF156 S; {# _, J1 Q# U( A6 m
1186152 ADW LRM Part Status for Deleted Part in LRM is distinguished with other part status
) y# c, T0 @5 f0 e1186387 ALLEGRO_EDITOR OTHER DXF cannot catch offset value in s047 hotfix.
! M; h8 @! a! j3 s1186805 ALLEGRO_EDITOR OTHER Exported STEP file missing multiple components placed on board
' T& W+ T) E6 k$ N3 w! n5 N1186818 ALLEGRO_EDITOR COLOR Custom color not retained during dehilight
2 F6 M' ?* h" }* v1 `& v1187196 CONCEPT_HDL CORE TOC not populating (page 1)
4 y6 r8 @; J L$ O! u g: o1187667 F2B PACKAGERXL Existing hard LOCATION property in drawing was left unchanged
' ~/ U- ]3 W: ~" s1188264 ALLEGRO_EDITOR MODULES Some fillets not regenerated in module created from a board file.
: P5 @7 {4 X8 S1190144 ALLEGRO_EDITOR OTHER Fillet shape is not genrated around cline$ A" J2 }9 Q" ]8 Q, {2 n
1190210 F2B BOM The bomhdl.exe fails - MFC Application has Stopped Working
0 Y8 S4 F1 N* t" T8 k1190618 ALLEGRO_EDITOR GRAPHICS Enhancement for Visible grid3 a% q& f4 d9 q/ V- F3 T
1190813 ALLEGRO_EDITOR INTERFACES 3rd party netlist file in TEL format fails syntax check but imports successfully, k8 V) u: Q0 k* M( T* p2 |% L
1190895 ALLEGRO_EDITOR EDIT_ETCH Route delay meter displays violation when sliding diff pair
: h3 [9 m) w. O( B# h. N1190908 F2B OTHER DE-HDL aborts if dummy net is being cross-probed from PCB Editor
/ X* C( i+ L' h* i. _) K1190990 CONCEPT_HDL CORE Mismatch in .csa and .csb files
6 I4 U9 \/ @6 h5 Y' b |1191008 CONCEPT_HDL CORE Remove Binary File feature doesn't work
" s0 _3 H9 g" h& p, `% v/ z1191514 SCM PACKAGER Packaging error PKG-1001 S2 P3 X) g3 a1 O4 S C: j4 N
1191517 ALLEGRO_EDITOR DRAFTING Metric +tolerance when using dual dimensions is not displayed correctly
, s2 h+ j" v& l: j1192561 ALLEGRO_EDITOR GRAPHICS Padstack with offset is not showing correctly in the 3D Viewer.
* v) S" o4 Q/ M! O* a9 p1192916 ALLEGRO_EDITOR EDIT_ETCH Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.9 v# G; g; @. n5 j5 C0 z N5 t: u
1194197 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks.6 r! f0 m& [% S8 `: r! v& j
1194239 PSPICE DEHDL Associate Model does not launch from DE-HDL
/ o0 Q! [4 c6 n3 K: V# n1194736 PSPICE SIMULATOR Design causes RPC failure when run consectively
! q3 M- B) c, R4 n( u) O5 |9 O1195139 ALLEGRO_EDITOR PLACEMENT Components disappears from board file once they moved
; @! K0 `6 x7 X! @
' F# ^5 l: C9 j0 YDATE: 09-27-2013 HOTFIX VERSION: 016
2 v3 |3 R6 B) ?===================================================================================================================================
2 D4 G0 ^5 U$ ?CCRID PRODUCT PRODUCTLEVEL2 TITLE
, B7 S/ D% n. x% D% j===================================================================================================================================
H& J. C& f+ I; m+ q/ g548538 CAPTURE NETLIST_ALLEGRO Enhancement:Include mechanical parts in Allegro netlist
8 D+ `! i1 Y+ p# |+ U" k1076579 CAPTURE GENERAL Display value only if value exists
, z1 k1 x6 W X, U4 O! P# s( j& I+ Y1083904 FSP GUI Need Filter in Change FPGA dialog to select desire FPGA from the long list.$ U8 K: k# h% S0 x. L, P
1089313 ALLEGRO_EDITOR INTERFACES Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility
2 h$ s- h, n7 a5 Z6 P" Y1 n6 z/ f1095728 ALLEGRO_EDITOR EDIT_ETCH Slide to grab adjacent elements when extend selection is enabled/ w8 c+ J: G O; I( @$ `- j
1102698 SIG_INTEGRITY ASSIGN_TOPOLOGY ECset will map on single ended nets but fails when the two nets are define as a diff pair.
' h' ~. Y: p& s( S( H1104071 SIG_INTEGRITY REPORTS Shape Parasitic value changes for bottom shape for changes in top shape+ b/ i9 {- a& @8 P! x3 t' u9 P
1117731 FSP POWER_MAPPING Ability to sort in Power Regulator forms
7 k# ] o) J: t# J) o! T* z( k( Z1121539 FSP CONFIG_SETTINGS Cannot configure special FPGA pins (temperature diodes)
, o. s3 s: g' Z p0 ?) s* j0 I9 v1122721 FSP MODEL_EDITOR Partial copy-paste overwrites the complete cell in XML Editor
: |' H. o2 E7 H% H% k1123238 FSP TERMINATIONS Report functionality for terminations defined in the complete design.
5 [' Z& ^+ G% E% z& E4 z1123364 FSP GUI Clicking on column header should sort the column.. d3 S/ y! B9 _# ^. o
1123403 FSP EXTERNAL_PORTS Improper checkbox selection for 緿o Not Connect� or 縀xternal Port� column
7 g) z# y/ v, s* x) c7 ?2 D- Z9 d1125611 CONCEPT_HDL OTHER display unconnected pin in schematic pdf.& U5 R- o; {3 \& W y i# D2 H
1129871 ALLEGRO_EDITOR INTERACTIV Wire Profile Editor can't read mcmmat.dat in working directory.
" w0 B. o- T$ q3 a4 Y, v- Z1 e1133688 ALLEGRO_EDITOR GRAPHICS Enhancement request to enable 3D Viewer to show STEP model from .dra file.% p+ J2 b; |1 i
1141747 ALLEGRO_EDITOR GRAPHICS 3D view dooesnot displays height if step_unsupported_prototype variable set
) n6 [! v: }/ O6 W2 z: W) Q' k1142215 SIG_INTEGRITY SIMULATION PULSE_PARAM set on DiffPair wasn't used for designlink simulation.
! ]: S7 Q' Y+ k" Y# u. d7 X1142798 ALLEGRO_EDITOR INTERFACES Step file output is incorrect in step viewer when composed of arcs and line.# h: [+ l+ ?4 f" \8 F! i% ~
1142894 FSP GUI Ability to RMB on a header and select `Hide Column�
( p. [$ J( K4 G. r1142940 FSP EXTERNAL_PORTS Issue with checking/unchecking "Do not connect" and "External port" cells
+ @( X8 m& r9 f: k' x+ n: L1142949 CONCEPT_HDL SKILL Usage of "Preferences > License Settings� in FSP# S% C0 c* \& h$ D1 p; k" A
1143091 SIP_LAYOUT SYMB_EDIT_APPMOD symed: When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract5 j8 y; t* _: n. _
1144371 CONCEPT_HDL COMP_BROWSER Component Browser search results are inaccurate% ?- H/ a: i* F$ m2 f
1145033 ALLEGRO_EDITOR PLACEMENT When aligning components with options in Placement mode displays no busy indicator
3 a: C7 [ {$ c& @3 X& o# L1145286 CONCEPT_HDL CORE Directive required for switching off the console1 J I1 I8 O6 }" o7 v$ R, r
1145800 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl.+ O/ W/ r: T6 |! M' d! Z4 T8 ~
1147899 ALLEGRO_EDITOR SHAPE Autovoid two overlapping shapes that share the same net
! R1 }/ f2 c2 p% |1149996 ALLEGRO_EDITOR EDIT_ETCH Routing does not follow the ratsnest 'pin to pin'.
- c- ]9 _. b: j- D1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.' b- H' `0 e0 O/ z# A
1152577 ALLEGRO_EDITOR DATABASE slide removes cline seg
M6 \$ w2 _ i9 ^" ]1152751 CONCEPT_HDL CORE Option to double-click and copy the Netname
2 U( \* ?% D, x: Z# j; T, P1153220 ALLEGRO_EDITOR INTERFACES ENH: option to supress header/footer during PDF Export
" p5 R& b* d) y$ ]: S+ H$ Y! s1153625 ALLEGRO_EDITOR INTERFACES If Symbol has place bound bottom, the step model shows incorrect placement.. |" w+ S c3 N
1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form7 ?, ^) p$ }% n1 A: J) F$ j
1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties.
5 L4 e/ S+ P6 p: X6 M _0 h1155161 CONCEPT_HDL CORE Add Signal name: Suggestion box overlaps with the typed signal name that is typed' ~" Y" R! W) w% T
1155922 CONCEPT_HDL OTHER How can I use the batch mode for PDF Publisher and print a variant overlay?7 Y) o# Z& o% x, o
1156858 ALLEGRO_EDITOR PADS_IN PADS Translator: Missing drill on square PTH padstack2 \1 s- f# N) i0 n5 L
1157362 APD 3D_VIEWER Need a way to color multiple nets in 3D viewer from APD/SiP.
4 H- w; S0 ?" B- `- j3 i5 O1158130 CONSTRAINT_MGR ANALYSIS Constraint Manager do not display the Cumulative Result in Reflection Simulation
/ ~9 V+ c# h( G9 q+ Z( v1 N1158210 ALLEGRO_EDITOR SHAPE SIP Layout happens crash while users move the shape with route keep-out" K' O' Q# i6 {# _+ ]
1158452 SIG_INTEGRITY GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle
) I6 f2 a+ B5 M1158827 ALLEGRO_EDITOR EDIT_ETCH Slide a via in pad automatically add cline back to via to pin.
( N& O0 C% k$ _1 V5 I1158871 PCB_LIBRARIAN IMPORT_CSV PIN TEXT is not automatically added when importing the .csv file
( Z, h/ N& o; C6 Q1159738 ALLEGRO_EDITOR INTERACTIV Selecting the Cancel button in the Text Edit command does not cancel the text.
2 o& x9 A! x q1159878 SIG_EXPLORER OTHER Ecset mapping dont follow topology template
( ]) w. I+ b+ ?1159971 ALLEGRO_EDITOR MANUFACT Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file" a, q1 j7 Y/ v8 c' k2 w
1160017 SIP_LAYOUT DIE_ABSTRACT_IF Add text to clarify shrink operation
9 W+ w0 m8 b- D, }1160507 APD EDIT_ETCH Script not playing back what was recorded when sliding lines
& B% q; z& L2 {6 m: W1161261 ADW TDO-SHAREPOINT Schema for TDO-SP fails on Japanese OS; {- o1 l% h6 s9 Z7 {3 }
1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro1 w& U6 W2 Z) r) l* ?( o
1161636 ALLEGRO_EDITOR DRAFTING need new function for PDFout : hatching shape# E( p5 C% H- w8 x" H3 ?5 ?
1161777 ALLEGRO_EDITOR OTHER default line width for PDF output$ ?( `' M% ^' p- j( f+ V
1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
% |! x& r3 B- E* Z* I! D" A$ u1162562 CAPTURE STABILITY Capture crash on second attempt of pspice netlist creation in 16.6: o4 v- o6 q: ?" S
1162629 FSP PROCESS "Load Process Option" under Run does not work properly8 Z6 ]: p: ]( V$ Z" F1 o {) W
1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE2 b$ D! e) e. |* v ~3 |, f
1163149 ALLEGRO_EDITOR DATABASE Autosilk creates Illegal arc to corrupt database
: J/ a/ [1 N4 Q' x! ~% o# |5 E8 g1163439 ALLEGRO_EDITOR COLOR Duplicate Views Listed in Visibility Tab. B7 o7 T) d, w* h% q
1163521 CONCEPT_HDL COMP_BROWSER System Architect crahes on replace8 `$ q3 D, h8 p Z- y
1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin) a- I, I1 r* T3 f. n2 _7 m
1163902 APD EXPORT_DATA Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?
+ M# B4 ? h, k6 }1164337 CONCEPT_HDL CORE Cannot delete attribute filter value in PDF > General > Attribute Filter list
5 |7 R3 `/ Q$ h/ I+ w/ ~/ ]3 d1164365 ALLEGRO_EDITOR INTERACTIV Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol% h: l k8 U) }$ w" ~+ A
1164769 APD VIA_STRUCTURE The replace via structure command does not accept a single canvas pick.( x& Q7 W' K* P4 g
1165026 ASI_SI GUI EMS3D exist in Via Model Setup of SI base. Z. e! ]8 h9 j/ }6 K* Y
1165561 CAPTURE DRC File > Check and Save clears waived DRCs
3 L8 l! b6 j2 a) N' @, X! K1165631 CAPTURE STABILITY Capture crash in the hierarchy tab of Project Manager window
9 `! u' G* g/ \$ X- ]1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)6 ^: U% P. `5 b0 s3 z5 e
1165911 FSP PROCESS Editing group name in protocol causes incorrect Process option checked
4 X: f; r3 `% R; r. Y4 V# Z1 c: {1166026 ALLEGRO_EDITOR DATABASE Running DB Doctor removes net name from vias
* S" @" ]- ^- C5 O2 g1166034 SIP_LAYOUT OTHER SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle
+ m) u; ?" P) M1166074 GRE CORE GRE crashes during planning phases" h% |# G7 p1 i
1166319 ALLEGRO_EDITOR PLACEMENT Swap not succeed8 |9 O' t- ]1 W2 E6 P( X j
1166484 SIP_LAYOUT WIREBOND Bondfinger "Align With Wire" problem during move8 Q) D/ o. t a4 t% A% D
1166530 ALLEGRO_EDITOR INTERACTIV Bug: Mirror in Placement Edit resets the options tab for Edit > Move
Q) ?4 R9 v7 G; d2 n" i1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue/ B6 N0 m* p% Z2 T$ s; E
1167847 CAPTURE PROPERTY_EDITOR Implementation name length greater than 31 character causes capture crash
" J, \+ o2 ^: D( b# J- p1167887 F2B OTHER Improve message on symbol to schematic generation
# A; T4 V7 a) p% A1168369 F2B DESIGNVARI Variant don縯 appear in increasing order while Annotate.. w0 h; m1 m" n* ^5 K
1168629 APD OTHER Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD
7 c% C. }% ]3 ?" c, I1168678 ALLEGRO_EDITOR NC Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.
2 Y# D/ @% `' l5 c$ p! ~# L( b1168798 ALLEGRO_EDITOR INTERACTIV Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk
: ^) n' J: R; i3 K; P1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check( ?2 _: f2 Y4 G, I% r
1168864 ALLEGRO_EDITOR CREATE_SYM Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty# M5 |) \ |* B
1169213 PSPICE SIMULATOR Parametric sweep is giving incorrect reuslts
: D, F" N% v4 ~1169436 FSP FPGA_SUPPORT Add support for Cyclone V CSX and CST parts4 I9 H4 T8 r R K7 q6 U# g% s
1170108 ALLEGRO_EDITOR INTERACTIV Enhancement to preserve Rat T location for Topology assigned schedule8 k+ I0 `( Y; r
1170313 SIP_LAYOUT LOGIC scm adding additional pin names and unassigned property to codesign die chips file* ^ V) `7 {$ l/ p) y7 u0 i
1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window.
. Q: x: Z- z7 x" N1171747 ALLEGRO_EDITOR PLACEMENT Allegro crashes when doing a gate swap between components
; @$ F0 ~ N+ J U* J1172183 ALLEGRO_EDITOR INTERACTIV Alignment modules fails on equal spacing1 _) F. f- }; l5 v0 h
1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via
$ l1 Z! o1 t' Q! X) C# V4 H/ M( Z1174067 ALLEGRO_EDITOR DRC_CONSTR Soldermask to shape drc does not show if the layer is a PLANE.
$ A: I% D5 ]+ D- B! V1174338 ALLEGRO_EDITOR PLACEMENT preview has rotated pads0 x' z( k0 x# R, N$ u5 f4 o
1175307 CONSTRAINT_MGR ANALYSIS CMGR fails to report RPD DRC for accuracy 4 - mm- \8 H( _/ }3 l* [& |! L- a( u
1175537 ALLEGRO_EDITOR REPORTS net loop report crashes Allegro. Design specific |/ J5 K# W8 K$ z2 {! `3 P9 K
1176126 ALLEGRO_EDITOR INTERFACES 3D viewer doesnot change models units dynamically
6 l' Y: V% p, S1176281 CONCEPT_HDL CORE Option to Auto-hide excluded modules" w' ^: q! q3 a) w
1176413 ALLEGRO_EDITOR MANUFACT Q - testprep parameter settings is not retained, what could be the cause..
5 H# v! U& z; }% p8 h+ k0 a% x) v1176791 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl
" C1 y5 n( n# D* k* A1178052 ALLEGRO_EDITOR SHAPE SIP crashes during shape degassing.
# _) Y! a+ m5 s0 l9 {+ q- S# s1178158 ALLEGRO_EDITOR INTERFACES Export step file creates step file of same height
' Q& W' x; `7 C8 V: _' d1178201 ALLEGRO_EDITOR GRAPHICS Large oval pads rendered as oblong hexagons in the 3D viewer7 G8 V2 \; {+ {
1178671 ALLEGRO_EDITOR GRAPHICS 3D Viewer in package symbol editor not displaying correct place bound shapes.
. D m9 K/ l; W$ b5 N1178725 ALLEGRO_EDITOR OTHER With fillets present, rat lines do not point to the closest endpoint.
/ a- M( ?; m) S3 B. v1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.2 o1 ], e# X( \, T$ o( G, s9 Z
1179093 ALLEGRO_EDITOR SHAPE Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.5 ?5 s) P6 }& t- h2 k0 Q5 Z2 y
1179109 ALLEGRO_EDITOR OTHER DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version- B7 u: [8 y& p, w
1179571 ALLEGRO_EDITOR ARTWORK Artwork crash and artwork log report Aparture missing
( d5 J$ \, W9 A9 E. Z. e1179636 SPECCTRA ROUTE Route Automatic will not start if NET_SHORT are attached to a mec-pin
c1 l* v/ H [% v( K' U1179659 SIP_LAYOUT DIE_EDITOR die edit on co-design die losing c4 bumps' X/ y5 b8 u" P
1180306 ALLEGRO_EDITOR ARTWORK When trying to create Artwork the tool crashes with no error messages just a little X box' b! Y1 p; y; v6 }: X# X
1180573 ALLEGRO_EDITOR ARTWORK If one layer has warning, all artwork films are "created with warning".
& }& ]0 W, v" Y1180960 SIP_LAYOUT PLACEMENT swap function is not swapping logical paths in sip layout!3 p z5 i2 J" b( B
1182534 ALLEGRO_EDITOR SKILL axlLayerPrioritySet() not working with v166 s013 and up* V+ R1 _, m" d; D7 N4 n0 t3 w
1182560 ALLEGRO_EDITOR PLOTTING Creating plot 2nd time casues Allegro to crash0 W- h# y8 T! T, c2 I/ b* v7 b- R% ]
1182616 ALLEGRO_EDITOR PLACEMENT Application crashes when attempting to place a high pin count BGA# i( O0 \+ _* Q6 P
1183752 CONCEPT_HDL CORE Unable to modify location properties within a read-only hierarchical block
5 W+ t2 g% T( ?2 U7 O! n1183774 SIP_LAYOUT DIE_EDITOR Die Refresh hangs" @* z# ?/ M9 O7 ^" E6 }9 p
1184178 CONCEPT_HDL CONSTRAINT_MGR Ecset xnet members lost from electrical class when restore from definition of subblocks
7 V* C; E* G- q7 A1 P4 @5 g1184787 ALLEGRO_EDITOR EDIT_ETCH Allegro SPB166 s 015 crashes during normal add connect function.. i; _# |, R! r6 g8 a' m! L4 Y1 F
- P- g$ @( t+ c9 { S
DATE: 08-22-2013 HOTFIX VERSION: 0154 S' K4 H" h4 H; c `1 d
===================================================================================================================================- N N4 l& ^$ |: F
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 [9 j/ p' {0 w1 O+ Z; y===================================================================================================================================
, ~6 x) D) x/ p+ m1156102 PCB_LIBRARIAN CORE PDV severe performance degradation on Linux platform makes PDV counter productive after some time; l3 {% e2 b5 A+ d5 ?
1165756 CONCEPT_HDL CORE DE HDL 16.6 adding ASCII character to properties1 Y. f a7 x$ `7 @0 {; f% B
1169896 ADW LRM Library Revision Manager makes updates but the interface never returns to the user
+ ?" T. `7 P3 `. d2 Z% q1170635 SIP_LAYOUT WIZARDS BGA PIN NAME doesn't sync with PIN Number
% }: `5 P7 @2 {+ w. y, n/ C: v( z1171061 ALLEGRO_EDITOR PLACEMENT Place Replicate Apply cannot place module; O0 A2 S% u0 i8 U' f* x8 y* `+ k& P) p
1171415 CONCEPT_HDL CORE Mismatch in the interface ports in design bw_hybrid for block a38410_scsp
! N+ q0 [- a3 n9 h: P1171598 APD WIREBOND Cannot load xml over 65 profiles defined in file.
+ ]" e+ q1 C! b7 B B1171713 ADW LRM Blank lines appear in the LRM - RM-Clicking causes LRM to crash
' Z& t6 b! G/ P, ^' t, R8 G+ r1172576 SIP_LAYOUT IMPORT_DATA AIF import fails with Error: symbol is missing refdes
2 L9 S- f, K, P5 c4 E* z. M" C1172938 ALLEGRO_EDITOR PLOTTING Export IPF probrem+ k) b+ s, Z* C$ s
1173190 ALLEGRO_EDITOR ARTWORK Not able to Add/ Replace film_setup.txt file in Artwork control file.6 p) P1 ]4 ]9 V; h0 y) r; D* Z4 c
1173750 ALLEGRO_EDITOR REPORTS SIP tool crash when clicking report "Net Loop Report"
' Z1 p1 Q( F |! \0 L, {/ O0 f8 C7 ]1175582 ALLEGRO_EDITOR SKILL axlDBCreateFilmRec error undifined function
& U: Z: L6 z# v4 W/ o+ s6 O
8 `2 S" Q2 ?# H) `DATE: 08-9-2013 HOTFIX VERSION: 014# s3 V" P! i1 j6 x% ]# d" z6 N
===================================================================================================================================
4 u0 X' e( @/ m2 H. d/ MCCRID PRODUCT PRODUCTLEVEL2 TITLE
- a; O; M- M! L5 N' S# w===================================================================================================================================
% L% F; D6 A: t* `; I/ R8 ]1155569 APD MODULES P1_U1 and P1_U3 Die pins are missing after Place Module.* W" u+ U% q0 V7 t! S9 R
1158528 CONCEPT_HDL OTHER Dual Monitor issue: Retain Hard Packaging option is missing and attribute test distorted( F8 j0 S7 U& [9 Q
1160968 ALLEGRO_EDITOR SKILL Text Subclass change difference in Edit > Change and axlChangeLayer Skill command
& `7 `) b3 h. N) @7 u1161986 SIG_INTEGRITY SIMULATION Flatline waveform seen when via model is set to detailed closed form or analytical solution
2 L/ S3 M' }' o A4 `1162323 SIP_LAYOUT DIE_EDITOR Die Editor is incorrectly leaving an unassigned function pin in the die during refresh from die abstract/ L2 Y: U k+ ]3 e8 \# R1 c" z
1162752 ALLEGRO_EDITOR SKILL axlDBChangeText doesnt recognize ?layer as a valid argument as documented! M5 v+ N# ?6 \- R2 p
1165002 GRE CORE GRE Crashes during Plan Spatial giving "Memory Allocation Failure" Error.3 Y; `" A! v* o* R' G, q& i
1165469 CONCEPT_HDL CORE Import Design loses design library name: V0 R6 n+ |3 S- H j; I: }/ {
1165708 ALLEGRO_EDITOR TESTPREP Test point router failing when attempting to insert new TP via's
: i% T+ P7 ]/ D+ l8 p. z- a. `. H1 l1165801 CONCEPT_HDL PDF Pin texts of spun symbol overlap in publish PDF.* ^2 M- ]9 \% w( a: F
1166020 SIP_LAYOUT WIREBOND Bondpads created with shapes do not follow the orthogonal pattern when adding wirebonds.$ s; B, t1 g4 i9 G
1166371 ALLEGRO_EDITOR DATABASE File locked for writing in 16.5 cannot be unlocked in 16.6$ W2 c0 X# b# T4 |/ P
1166482 ALLEGRO_EDITOR INTERFACES Step orientation for y-rotated component is not exported correctly.% v$ Z" T/ W# u0 C5 Y+ F
1167519 ALLEGRO_EDITOR DATABASE Uprev dbdoctor does not log warnings about renaming properties.
3 h, l! r& m2 r) B& G% ~- x1167588 SIP_LAYOUT DIE_ABSTRACT_IF do not create a new pad stack for each I/O pad1 l! x. s; ?$ |+ `; \1 P5 ~0 p4 y4 T, [
1168496 ALLEGRO_EDITOR SCHEM_FTB Export Physical Crashes when netreving the board3 ]+ V* C. @- j/ Q+ G4 `
1169510 SIP_LAYOUT WIZARDS Netlist in Wizard is crashing with this text file where the Net Name for one of the assignments is blank, meaning dummy/ H B. H* y7 |+ {- @. V( C. _: }
1169593 CONCEPT_HDL PDF Published PDF file's hyperlinks do not work fine when user click 1D10 or 2A10./ W, A, B+ }5 g2 N+ p3 R" |6 ~
1169984 F2B PACKAGERXL Error Mapping cset when packaging but not in CM Audit
7 `5 k% P; O+ G& p, ~& s9 d, f1171008 SIP_LAYOUT OTHER SiP Layout - Beta feature Void Adjacent Layer Shapes - changes or modifies "priority" of other/all shapes
! q V) l3 L6 C) r) h" N; x$ W- U1171411 ALLEGRO_EDITOR OTHER Enh - Break in Step 3D view in latest hotfix v16.6s013
$ J! p; K* |$ w1 B8 o% S; W8 h
4 m- D R7 a6 EDATE: 07-26-2013 HOTFIX VERSION: 013
: V; O! t" N4 h, Q, j===================================================================================================================================, m: R# Y6 ~) C. H
CCRID PRODUCT PRODUCTLEVEL2 TITLE
* r, f2 X: u% ?% m: H5 R===================================================================================================================================
% P! W# u; w7 J5 l111368 CAPTURE CORRUPT_DESIGN Capture - will not produce allegro netlist with 10.0
9 y1 M# a6 q/ c8 K7 [) X134439 PD-COMPILE USERDATA caCell terminals should be top-level terminals
: O y; }) B9 I* ]1 w8 x186074 CIS EXPLORER refresh symbols from lib requires you to close CIS; i# |) U% n0 O5 x0 Q0 X0 z- r, d
583221 CAPTURE SCHEMATIC_EDITOR Option to have the Schematic Page Name as a Property in the Titleblock
9 m$ h. J# y2 O- V591140 CONCEPT_HDL OTHER Scale overall output size in PublishPDF from command line
. f! x& r; G! n1 x. m' a801901 CONCEPT_HDL CORE Concept Menus use the same key "R" for the Wire and RF-PCB menus" D3 `7 }# g' K4 Z6 e1 |8 F
813614 APD DRC_CONSTRAINTS With Fillets present the "cline to shape" spacing is wrong.
$ A& N- p& m `0 Z% T" f881796 ALLEGRO_EDITOR GRAPHICS Enhancement request for Panning with Middle Mouse Button% z$ y! y) s; T+ j f4 Z
887191 CONCEPT_HDL CORE Cannot add/edit the locked property
+ [( ~) Q" o& Y- M( v911292 CONCEPT_HDL CORE Property command on editing symbol attaches property to ORIGIN immediately, N( ?3 }* k6 O% X
987766 APD SHAPE Void all command gets result as no voids being generated on specific env.
, O: f( ^7 V3 H' X+ I) F1 x3 [3 b j1001395 SIP_LAYOUT ASSY_RULE_CHECK Shape Minimum void check reports lots of DRCs which are not necessary to check out.3 E+ t5 I+ l: D& s/ H- j4 A% ^0 O
1030696 ALLEGRO_EDITOR INTERACTIV Enh - Allow another behavior of PAN movement using middle mouse in Allegro0 ]0 K. w0 ]5 \: ?! i
1043856 ADW TDA Diff between TDO and DE-HDL Hierarchy Viewer is confusing to the user
* F4 {0 E4 z2 W9 I, H1046440 ADW PCBCACHE ADW: ImportSheet is not caching libraries under flatlib/model_sym when the source design is not an ADW project
5 V& m$ V0 @0 j$ x( |. r1077552 F2B PACKAGERXL Diff Pairs get removed when packing with backannotation turned on
i2 F+ M: c3 ]+ j5 ]1079538 F2B PACKAGERXL Ability to block all 縮ingle noded nets� to the board while packaging.
% y' E. f& W1 B. S/ O- T1 i1086362 ALLEGRO_EDITOR SHAPE Enhancement request to autovoid a via if shape cannot cover the center of the via.
7 V& k1 G8 e3 }1087958 PSPICE MODELEDITOR Is there any limitation for pin name definition?
" N1 {. A0 M5 b1087967 CIS UPDATE_PART_STAT Update part status window shows incorrect differences
" p- a. X% P( L7 J2 Q0 r1090693 ADW LRM LRM auto_load_instances does not gray out Load instances Button
% a) V, B9 b5 i' s+ g: o1097246 CONCEPT_HDL CORE ConceptHDL - assign hotkeys to alpha-numerical keys% R% `; t; B; q' z) K# T+ B$ l0 G# C' r
1099773 CONCEPT_HDL CORE DE HDL goes into recursive loop if a custom text locked at site level is deleted from Tools > Option$ t7 F: }3 s3 }
1100945 SCM SCHGEN SCM generated DE-HDL has $PN placement issue
; ^/ J" I* x8 A5 e2 H6 g& W1100951 PSPICE SIMULATOR Increasing the resolution of fourier transform results in out file9 h: h* j: e: S- Z
1103117 RF_PCB FE_IFF_IMPORT Enh- Allow the Allegro_Discrete_Library_to_ADS_Library_Translator to output in its original unit
: Q6 U$ C! O% j1 V* ?1105473 PSPICE PROBE Getting error messages while running bias point analysis.
5 T' S8 @) E+ f1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.% c: E+ K4 g* U" U, W: E( V5 B6 d
1106298 ALLEGRO_EDITOR INTERACTIV Copy Shape uses last menu pick location as origin and not the Symbol Origin as specified in Options./ L$ n4 t) V7 i( F3 P, n* Q
1106626 CONCEPT_HDL CORE Concept HDL crashes when saving pages
( a% h$ f8 w- u9 Z# M2 I1107086 ALLEGRO_EDITOR INTERACTIV manual void with arc's goes in wrong direction during arc creation
i1 _# c/ D0 R2 j- S* Y1107172 CONCEPT_HDL OTHER Project Manager Packager does not report errors on missing symbol l$ T0 H" j2 L2 `* F O0 n' T$ }
1108193 CONCEPT_HDL CORE Using the left/right keys do not move the cursor within the text you're editing! l( ] Z( y9 D G" T4 Q: t0 H6 U; N
1108603 PCB_LIBRARIAN VERIFICATION PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm6 O4 n0 O! Q, E1 s5 [+ L
1109024 CIS OTHER orcad performance issue from Asus.
" I1 x3 l2 y6 }& s5 H W5 n1109109 CAPTURE NETLIST_ALLEGRO B1: Netlist missing pins when Pack_short property pins connected2 A% j# H+ L f+ D7 D8 E
1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerber lines for fillet.
7 }: X1 R1 T3 W- a$ j1109647 SIP_LAYOUT DEGASSING Shape degassing command enhancement - control over what layers are counted in even/odd layer sets.6 N( a+ L" H" E2 P* w9 A/ ^
1109926 CONCEPT_HDL CORE viewing a design disables console window" Q9 n% W: n4 E+ Z* M8 Z% a
1110194 SIP_LAYOUT WIREBOND If OpenGL settings for display of dynamic net names is enabled, should be visible while push/shove wirebonds.
2 O0 P' G+ j# q, |/ w1112357 SIP_LAYOUT WIREBOND wirebond command crashes the application) ^1 m5 X: d! g& \* ?( P: L0 K
1112395 CONCEPT_HDL CORE 縗BASE\G� for global signal is not obeyed after upreving the design to 1650.7 T- ^$ J* R6 ?- Q
1112658 CAPTURE PROPERTY_EDITOR Changing Part 縂raphic� value from property Editor Changes Occ refdes values to instance
1 N# T# E; l+ r- j0 b1112662 CAPTURE PROJECT_MANAGER Capture crashes after moving the library file and then doing Edit> Cut
7 D4 _, j0 W A" ?) P9 R: r1113177 PCB_LIBRARIAN CORE Pin Shapes are not getting imported properly
2 d) v0 f9 N* f: @; O) K1113380 ALLEGRO_EDITOR INTERACTIV Change layer to - option for package type .dra is not available in 16.6 release t/ T i4 W1 D- n5 X
1113656 SIP_LAYOUT WIREBOND Enable Change characteristic to work without unfixing its Tack point.
5 C6 g' P% A; v: W8 D" A3 a& Q1113838 SIP_LAYOUT DIE_ABSTRACT_IF probe pins defined in XDA die abstract file are added with wrong location
7 \4 r4 f+ R# f( [1113991 CAPTURE GENERAL Save Project As is not working if destination is a linux machine8 q3 A d- A8 i4 g
1114073 APD DRC_CONSTRAINTS Shape voiding differently if there are Fillets present in the design.
% p( |) H0 J! E4 A3 J1114241 CAPTURE SCHEMATIC_EDITOR Port not retaining assigned color, when moved on the schematic- K$ l* @8 s4 O, S4 _
1114442 PSPICE PROBE Getting Internal error - Overflow Convert with marching waveform on
. }0 B- W$ T' A/ y; A' x9 [# O1114630 CONCEPT_HDL ARCHIVER Archcore fails because the project directory on Linux has a space in the name) ?2 E# ^! P8 a" y; M
1114689 CONCEPT_HDL CORE Unknown project directive : text_editor4 d* l. {, `, _1 b2 C
1114928 F2B PACKAGERXL 縀rror (SPCODD - 5) while Export Physical even after change pin from A<0> to A- j7 ?+ v2 u+ O% b6 S
1116886 CONCEPT_HDL CORE Crefer hyperlinks do not work fine when user use double digits partitions for page Border.
8 k0 R8 }5 d: U+ i4 J+ E1118088 ALLEGRO_EDITOR EDIT_ETCH Should Plan accurate and Optimize be removed in 16.6?5 l* C; F1 V8 ?
1118734 APD EDIT_ETCH Multiline routing with Clines on Null Net cannot route in downward direction
+ L. B, }( S9 }5 d8 ~1118756 ALLEGRO_EDITOR SHAPE Shape clearance parameter oversize values getting applied to Keepouts$ d% G" ^2 O% C2 Z
1119606 CONCEPT_HDL MARKERS Filtering two or more words in Filter dialog box5 o, h+ n/ |& m6 I* Q( G
1119707 CONCEPT_HDL CORE Genview does not use site colors when gen sch from block symbol
/ r1 \) g4 T$ V Q2 t$ @1119711 F2B DESIGNSYNC Design Differences show Net Differences wrongly
- u9 J" [& j6 Q- K' Y8 T$ |1120659 CAPTURE PROJECT_MANAGER "Save project as" does not support some of Nordic characters.
! i2 E: r& C) H4 L1120660 CONCEPT_HDL CORE Save hierarchy saves pages for deleted blocks.; W4 V: r B" n/ l9 I- \
1120817 SIP_LAYOUT SYMB_EDIT_APPMOD Rotate Pads commands not working while in the Symbol Edit App. mode
% O" |! L2 o7 H2 M9 O/ ?1120985 PSPICE MODELEDITOR Unable to import attached IBIS model1 v M4 o# @5 M% X; N
1121171 CONCEPT_HDL CREFER PNN and correct property values not annotated on the Cref flat schematic
2 e% T+ F) f9 a- p" Q' \2 _2 K1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.
3 X( T" g! X- c1121382 ALLEGRO_EDITOR INTERACTIV Undo command is limited to two for this design
; S6 h+ a4 I; i5 [5 P1121540 F2B PACKAGERXL pxl.chg keeps deleting and adding changes on subsequent packager runs
- L& U2 z; E) e# L+ ^6 J: Y$ w2 I* p1121558 ALLEGRO_EDITOR MODULES Unrouted net and unrouted connection when module is placed of completely routed board file.
* R/ b& G" }+ d- U6 w1121585 ALLEGRO_EDITOR OTHER Drill Hole to Shape Same Net Spacing with Dynamic Shapes shows wrong result.3 j4 G5 @+ I, }) E; X( S$ ?
1121651 CAPTURE SCHEMATIC_EDITOR "PCB editor select" menu option is missing
1 R8 ?& w# ^& s1122136 SIP_LAYOUT PLACEMENT Moving a component results in the components outline going to bottom side of the design.' Y Z" I* m0 s9 D* h
1122340 CAPTURE NETLIST_ALLEGRO Cross probe of net within a bus makes Capture to hang.
" D1 s" B8 L( x+ w4 w3 n2 @1122489 CONCEPT_HDL OTHER Save _Hierarchy causing baseline to brd files% }/ |5 s# ?- Z- Y D0 y# W; U* L/ ?' ]
1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically
2 C4 D) Q# e; h/ O5 w0 L1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one7 m8 M. \! m! h- }/ q' g
1123150 CONCEPT_HDL CORE property on y axis in symbol view was moved by visibility change to None.
. Q/ Y. v" t: m3 s8 D1123176 ALLEGRO_EDITOR UI_FORMS Negative values for pop-up location is not retained with multiple monitors (more than 2)
/ F3 ^+ Z0 m9 P1123815 ALLEGRO_EDITOR GRAPHICS Embedded netname changes to a different netname6 ?. L `& R6 \# _% R
1124369 ALLEGRO_EDITOR INTERACTIV Sliding a shape using iy coordinate does not work indepedent of grid.3 s6 |" x; t/ L0 a. u& Y1 }
1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5" {, q& }: h$ k$ S: T8 U, `
1124570 APD IMPORT_DATA When importing Stream adding the option to change the point2 k$ b- h) F2 z4 z% q
1125201 CONCEPT_HDL CORE Connectivity edits in NEW block not saved( lost) if block is created using block add
- B' K8 h. K* e# a' c, }' w& V' Q1125314 ALLEGRO_EDITOR INTERACTIV Enved crash during setting of library paths in user preference
3 {( K. u8 a) T5 ~5 q9 \1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux) L. i) _2 @- u5 P5 t9 ^
1125628 CONCEPT_HDL CORE Crash on doing save hierarchy
, h+ i+ U8 p/ E% Y' Z/ E: O+ o1130555 APD WIREBOND Wirebond Import should connect to pins of the die specified on the UI.% h) t' G1 y$ K6 T
1131030 PSPICE ENVIRONMENT Unregistered icon of Simulation setting in taskbar
! p4 K+ g- u5 `+ R' c$ K1131083 ALLEGRO_EDITOR INTERACTIV Bug: 16.6 crash in changing the mode in Find filter window' g, G- c* D( f
1131226 ALLEGRO_EDITOR PLACEMENT When Angle is set in design parameters while placement component is rotated but outline is not.: o8 ?1 F! o8 c& `9 v
1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.
2 H3 I( ^# v3 ]% J% B" {1131699 PSPICE PROBE Probe window crash on trying to view simulation message: v3 e3 m0 c0 y# \ {( M
1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.
. b, b5 b" @+ K- r, W. ~) W- H1 b1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.% Y, I, E+ k" |7 _5 U2 Z# B% a
1132698 ALLEGRO_EDITOR EDIT_ETCH Slide Via with Segment option with new Slide command5 C. Y L4 V$ x3 K, F5 p v8 U
1132964 ALLEGRO_EDITOR SHAPE Same net "B&B via to shape" errors created when adding shape1 m2 h7 Q7 q+ v* \# f
1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top
! X5 Q4 X7 r5 i1 e2 _; }1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.
: A0 V+ ?6 ^( V, D6 m2 R& O1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property. d) r; t% Y7 q. K( o
1135118 ALLEGRO_EDITOR INTERACTIV Mirror and other editing commands are missing for testpoint label text in general edit mode.
6 m5 o/ C& X3 {. ]0 C! n7 w: ]1136420 CAPTURE GENERAL Registration issue when CDSROOT has a space in its path! e9 E( r- x- E9 N3 h& t3 R
1136808 PSPICE STABILITY Pspice crash marker server has quite unexpectedly2 v/ [* k$ ~' M" L3 h" ]" H
1136840 CAPTURE SCHEMATICS Enh: Alignment of text placed on schematic page& C# R7 q! k, ^: ?5 e
1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs' ~' C1 ~# B z u3 l
1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness
0 x: E, a- t. F1140819 APD GRAPHICS Bbvia does not retain temp highlight color on all layers when selected.
/ Y. {9 m3 J9 T1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped
6 R: p% U5 i s0 k% R7 }1141723 ADW PURGE purge command crashes with an MFC application failure message+ w* O% F, B* P. S% v
1143448 CAPTURE GENERAL About copy & paste to Powerpoint from CIS
' g2 T+ L- |: g) W! l1143670 SIP_LAYOUT OTHER Cross Probing between SiP and DEHDL not working in 16.6 release
) C7 s/ H( e& a/ u; S1143902 ALLEGRO_EDITOR DATABASE when the shape is rotated 45 degrees the void is moved.' g% E. V+ ?$ E( C4 O; H; p$ E
1144990 PCB_LIBRARIAN CORE PDV expand & collapse vector pins resizes symbol outline to maximum height
! o$ u, I% H$ j! ~1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed
8 w2 J6 }: C' b$ J1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case
' s# Y: W1 D0 t2 a% Z \% ^1146386 ALLEGRO_EDITOR INTERACTIV Place Replicate Create add Static shape with Fillet shape2 s6 \4 d5 E) S. d
1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail, M4 g: r, K: q5 z( i) n# {
1146783 ALLEGRO_EDITOR INTERFACES Highlighted component is missing from exported IPF file.
7 P$ x' K1 c" D9 Q2 r9 Y1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block7 Q6 I% [' c+ K5 L6 u
1148337 CAPTURE ANNOTATE Checking "refdes control" is not giving the proper annotation result) A0 [! p8 g8 y, {
1148633 SIP_LAYOUT INTERACTIVE Add "%" to the optical shrink option in the co-design die and compose symbol placement forms |! G$ G% D8 i8 b, B i2 t
1149778 CAPTURE SCHEMATICS Rotation of pspice marker before placement is not appropriate% N1 O0 q) `+ B v
1149987 PCB_LIBRARIAN PTF_EDITOR Save As pushing the part name suffix into vendor_part_number value
& M- |! K& D4 m/ C1151748 ALLEGRO_EDITOR OTHER If the pad and cline are the same width don't report a missing Dynamic Fillet.! G; y; f9 a5 C! [$ }! @# r
1152206 CONCEPT_HDL CORE ROOM Property value changes when saving another Page
5 C/ W8 ^- T7 g- e1152755 CONCEPT_HDL COPY_PROJECT Copy project hangs if library or design name has an underscore
6 T7 Z1 H1 m6 C$ B1152769 PSPICE ENCRYPTION Unable to simulate Encrypted Models in 16.6
2 Z) o6 U/ u. e: P0 V, Y; ~5 R1153308 ALLEGRO_EDITOR DRC_CONSTR Creating Artwork Getting Warning "DRC is out of Date" even when DRC is up to date
2 {# J: R! T1 }4 m1153893 F2B DESIGNVARI 16.6 Variant Editor not supporting - in name0 g: N! |! O) i @ h5 Q2 R
1154185 SIG_INTEGRITY SIGNOISE Signoise didn't do the Rise edge time adjustment.
, |. }; C3 X$ b. ?2 |. M1154860 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
) F0 a$ i; w2 k( w9 l1155167 ALLEGRO_EDITOR EDIT_ETCH Via structure placed in Create Fanout has incorrect rotation.1 ~) b' p; a; _+ o& [$ q
1155728 CONCEPT_HDL CORE Unable to uprev packaged 16.3 design in 16.5 due to memory# N; o9 w$ s1 P/ B( h
1155855 SCM SCHGEN A newly user-defined net property is not transferred from SCM to DEHDL in Preserved Mode
3 ]1 B* r3 H& K; \' Y$ l" n3 }1156274 ALLEGRO_EDITOR INTERFACES Exported Step file from Allegro is wrong+ k, C, W, O% a( M! x
1156316 CONSTRAINT_MGR OTHER Break in functionality while creation of pin-pairs under Xnet in Constraint Manager
; _4 V" e) m, Y0 u1156351 CONCEPT_HDL CONSTRAINT_MGR Loose members in Physical Net Class between DEHDL and Allegro
/ @2 ?9 m$ s7 @ o# r8 Z1156547 ALLEGRO_EDITOR DRC_CONSTR Etch Turn under SMD pin rule check through pin Etch makes confused.# C0 Z7 V0 i3 b3 J3 z |3 `
1156779 CONSTRAINT_MGR OTHER Electrical Cset References in CM not working correctly
2 t1 E* p: c7 k; W' }1157167 ALLEGRO_EDITOR SKILL axlPolyFromDB with ?line2poly is broken( Q2 M* M$ w9 R2 W& \0 Y
1158042 ALLEGRO_EDITOR DFA DFA_DLG writes the dra file name in uppercase.
7 ?7 @; }: Y+ }0 V1158718 CONCEPT_HDL CHECKPLUS Customer could not get $PN property values on logical rule of CheckPlus16.6.. Q* k& E( f. g
1158970 ALLEGRO_EDITOR SCHEM_FTB Changing LOCATION to $LOCATION in DEHDL does not update the .brd file
~$ P. f6 w# N" U: C, R8 ?1158989 ALLEGRO_EDITOR INTERFACES pdf_out -l creates a PDF
b7 s9 s" `7 A& G1159285 APD DXF_IF DXF_OUT fails; some figures are not exported: ]" ]6 b6 M6 f* z a, i, F% I
1159432 ALLEGRO_EDITOR SHOW_ELEM http:// in the Show Element in 166 do not have HTML link to open the Website2 D) X7 g: a ^4 F
1159483 PCB_LIBRARIAN SETUP part developer crashing with
( s) K( W9 I- k) ^3 D1159516 ALLEGRO_EDITOR EDIT_ETCH Unable to slide cline segment with new slide.; o1 h) R. e# z
1159959 ALLEGRO_EDITOR GRAPHICS 3D viewer displays clines arcs incorrectly
6 {' d& K- K5 `1 j1160004 SCM UI The RMB->Paste does not insert signal names.: Y+ ]( W [6 `( J' K. @: o
1160410 ALLEGRO_EDITOR DATABASE Lock databse with View Lock option is misleading% C8 F! b8 A" c
1160529 SCM SCHGEN Schematic generation stopped because the tool was unable to create an appropriate internal symbol structure6 W* X: C4 f, d0 E8 c( v
1160537 SPIF OTHER Cannot start PCB Router
& m$ x, P) d I6 @1161363 ALLEGRO_EDITOR SYMBOL Getting error SPMHGE-73 when trying to mirror symbol V- _/ g3 w9 w/ C* Z/ L/ j
1161781 CONSTRAINT_MGR CONCEPT_HDL SigXp crash when selecting ECset in design
7 {- S4 F" c+ Y+ e# m1161896 ALLEGRO_EDITOR DRAFTING Tolerance value added for Dimensions is not working correctly (HF11-12)2 w1 H3 h# ^' l) L& F5 c* @; }
1162193 SIP_LAYOUT DIE_ABSTRACT_IF shapes in dia file not linked to the die after edit co-design die5 T, Q% o( ^' p
1162754 APD VIA_STRUCTURE Replace Via Structure command selecting dummy nets.6 T: k. }* i" Q T$ u, {# n$ X
6 L8 b6 `4 |' {+ wDATE: 06-28-2013 HOTFIX VERSION: 0128 y) \8 B6 L, p5 C
===================================================================================================================================
0 ^4 q& }! g* Y) J' BCCRID PRODUCT PRODUCTLEVEL2 TITLE
i' @$ r6 _6 J; H3 D+ S===================================================================================================================================
- u# r) T% }* I `8 Z0 j914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD8 ]4 V0 ~# f% ?# w' b% f$ f
1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files% l1 ?' K: u0 b* U" S
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
) c: I* O* `1 _1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.% x& j5 l b7 Y* V* C* ] x
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line
8 z) W. X" y& K* K8 q; L3 z6 N1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.$ G# f+ W/ G: Y/ {. z3 D) x
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.
8 ^3 E: b: }8 p5 S3 K+ [) n! N1151458 GRE CORE GRE crashes on Plan Spatial
8 @7 D- e1 _. t$ L: f# E$ j c1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy* \ }) ~. F! V0 a s
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]
g7 E6 U! v1 r/ ?+ y1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design
* u4 t) N. J+ P; y$ o1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger
: ]5 c7 [4 k( p, ]: w, v1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.
& H z0 I7 @$ X6 N9 p+ O, ?1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places
2 K* g% |9 E2 M0 L5 a1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail% W- G. }* W1 y- H3 }
1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.
5 i% T% e& b; T; V3 }) w3 r1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer0 q& `8 a: h5 q7 D9 u8 ?) @
! X8 w, i5 g* t8 t7 }* YDATE: 06-14-2013 HOTFIX VERSION: 0119 d& s) \' L1 J$ G/ T
===================================================================================================================================, x S# r4 l* }, l0 N
CCRID PRODUCT PRODUCTLEVEL2 TITLE
( X8 R u3 V3 ^# @" ^===================================================================================================================================8 u% c! D7 ~" d1 \0 l8 Y+ A
982306 CONCEPT_HDL OTHER When plotting a PDF publisher output the page coming out half inch bigger in pdf
1 Q/ B1 h- i, B$ }- d2 r# f2 k U# L1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers
0 s- R* c) Z1 I+ F0 v1093375 ALLEGRO_EDITOR PLACEMENT Align Module with Zero spacing value space the modules further away the modules should be nearer
0 v2 ?+ B. v! P- L: l* f+ }1103201 RF_PCB FE_IFF_IMPORT Wrong permissions to map file during IFF import7 p, [' j" F3 M7 U& ^# v* X# f
1106900 CONCEPT_HDL COMP_BROWSER Component Browser performance utility should honor CPM directives for include and exclude PPT
2 s; D/ z4 c. M7 l2 D& @7 q1110178 ALLEGRO_EDITOR EDIT_ETCH Line Width Retention should be controlled via setting" Y R) C2 d8 P/ I. Y2 p4 P8 V: I4 F
1110323 APD DXF_IF DXF out is offsetting square discrete pads.) D; ]- g* X7 R* g& G3 S
1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board
5 L# [) [: n- w6 V9 H$ q$ t! G1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.& F4 S: H- u# f1 y
1139338 ALLEGRO_EDITOR DRC_CONSTR The total etch length does not seem to work for Xnets after setting the variable "retain_electrical_constraints_on_nets"& r5 D8 A: M" v. x
1139361 ALLEGRO_EDITOR DRAFTING Angular dimension tolerance is incorrect when plus minus tolerances are equal.2 a5 _; s% [" m* `
1141882 ALLEGRO_EDITOR EDIT_ETCH Allegro Crashes during diffpair slide+ f E' O0 T& c4 _- v9 ^. e
1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero
& @2 _. ]+ A) V. {$ _; M1 s1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP/ T. v1 h8 M) f! z- k
1145243 ALLEGRO_EDITOR NC Duplicate drills found in the NC Drill output
" h' E' S" f8 B) A! A2 g1145260 SIP_LAYOUT DIE_EDITOR Enable "Copy" in die editor
6 T% s7 i! ]- ?5 T1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL
5 t& J$ ]6 @0 `/ }2 j: E1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.) e1 x; {1 u6 w/ m3 v" [1 G- |& V
1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added0 Y5 q1 t$ x, x- p7 J k6 }
1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps: W' t f m% _
1146865 ALLEGRO_EDITOR DATABASE Allegro crashes when trying to place mechanical symbol
; X. o ?4 Z9 R% @9 @1148513 ALLEGRO_EDITOR OTHER Importing a subdrawing file causes incorrect net name assignment.
$ ~' w8 r4 Y6 d# H+ P2 [1148734 CONCEPT_HDL OTHER Logical Symbol Text is turned upside down after extracting PDF by Publish PDF2 k6 W }/ v" [/ S, j2 B" N/ J4 C
1149025 ALLEGRO_EDITOR INTERFACES IPC-2581 imports cross-hatched shapes as solid' I1 @' O8 j1 [, F3 B1 J
1149948 APD OTHER Stream_out hangs on this design -- hang processing merge of overlapping shapes using poly_deletecolinear_only()
X7 W; L1 S: F6 z3 W1150274 CONCEPT_HDL CORE Uprev from 16.3 to 16.6 is not preserving RefDes
0 p" A- q, f6 U2 [, @% p1151450 SIP_LAYOUT DXF_IF DXF export from CDNSIP missing symbols
. x3 _/ g- l# x8 k- e6 ^. ~" c9 l9 C( H3 m0 N% U
DATE: 05-25-2013 HOTFIX VERSION: 0109 f) i9 _! A# i F8 h l; O( o; H
===================================================================================================================================' |; G0 f" c' F! d: r
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 D. p7 p2 j: f& ~/ k/ \' L+ J===================================================================================================================================) M0 N8 X* |5 T1 L2 @9 v) L
1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
6 K- {# v3 A* i- m1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border+ \2 H: p" N* D8 u* J
1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files' {- ~. V2 P3 |7 ~: I
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
% D* M4 a. T* \6 P& L2 ~1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6$ O) T3 P& ]' g6 Y- E, ] h
1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border
7 O/ d; p8 |0 d, G$ h1131775 ADW LRM LRM error with local libs & TDA
* ]5 a4 z6 S* h" ?" \1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP45 ~6 _1 |3 W/ c9 C7 I3 B' Z
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
& n1 f: ]) W2 k$ \& G2 b1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.0 f1 s, \; l1 z1 c4 {
1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur
+ y* M4 b# s0 r7 w& ]! M1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?% L7 s! S* X7 H+ l2 t& z- {
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
+ @% ^, z7 b# g; k) \4 j2 }) g1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor6 g5 M1 C; ]' I5 w% p3 E/ l. ^/ P
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
, {" ?- X& @1 h4 V2 Q# u1 }1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.! s8 i* s7 F" U4 o2 f3 z
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581." {: Q( L9 @: v- B* _
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
0 b" Q5 b0 A4 W# v7 D& ^1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF3 s3 x2 W( e" @ z9 F
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
5 Z6 Y& L+ D3 g3 l$ P y1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor# g2 N$ K9 P. P7 J& J
& |, Y6 g2 m5 \$ `
DATE: 05-9-2013 HOTFIX VERSION: 009
2 W: T. `& P) ]===================================================================================================================================: e ~+ [, I+ I. R B- _8 ?% X
CCRID PRODUCT PRODUCTLEVEL2 TITLE
, {; Q" _8 N# J/ k6 m4 p) m' t- V" ?===================================================================================================================================' M/ I& F# Q1 \) k3 C6 A: }
961420 ALLEGRO_EDITOR PLACEMENT Regardless of the aspect ratio for room of side The QuickPlace by room command could be placed comp7 m! F* Z. i5 O, ?9 ~* f4 h% k: @
1079862 ALLEGRO_EDITOR SKILL Ability to create IPC2581 layer mapping file by Allegro Skill function# B) x, B: s! O2 n- l2 u
1080734 CONCEPT_HDL CORE Repainting of grid lines during pan or by moving window show as solid white lines instead of gray da
% j! Q s9 z. X7 S! P; v# ?1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB
: q0 H2 E3 i. N, g1107547 SCM OTHER v15.5.1 tcl/tk code not recognised in 16.66 t, a8 Q: K% l' P4 d5 @6 a x
1110209 CONCEPT_HDL OTHER We can move symbols and wires off grid despite the site.cpm grid lock: ^# C7 B9 M2 L) @
1117825 CONCEPT_HDL OTHER SHOW_CONSOLE_ON_LAUNCH throws an unrecognized directive warning in the schematic editor; Y- q" ]; ]) b* H2 _( _ C. b
1118874 ALLEGRO_EDITOR INTERFACES Oblong pad shapes are not shown with correct orientation after DXF export from Allegro3 E+ m1 ?* V* G
1121873 ALLEGRO_EDITOR INTERFACE_DESIGN Importing Bundles from Net Groups does not allow any further editing.
6 @$ _, D @% F* x# T7 U- ~5 L1122933 CONCEPT_HDL CORE Newly added Toolbars are getting invisible after re-staring Concepthdl$ q9 b& ?1 t8 B4 C
1124587 ALLEGRO_EDITOR INTERACTIV The Shape Expansion/Contraction command should also be available in EE mode.0 k6 f |6 u6 U5 T; [
1125895 SIP_LAYOUT LEFDEF_IF Tool crash while moving the slider in the Filter options Macro tab form of the co-design die library manager. T. W- w5 V2 z% s8 Z/ s) e
1125962 F2B DESIGNVARI Custom Text in Variant Details dialog box is inconsistent9 D1 L8 d% t3 U% X
1126096 SCM REPORTS Two nets missing in report
* i3 ]. E. B5 L, F- W+ ?) m1126134 SIG_INTEGRITY GEOMETRY_EXTRACT Attempting to extract topology hangs APD8 O4 \. p: ^- f
1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.
& T! O' S, q( \! a4 m- k& T9 Y2 M1130280 ALLEGRO_EDITOR MANUFACT stream_out command in 16.6 seems hard coded to look for a design called stream_out.brd
) A0 j. ^7 c9 |/ |7 z1130737 F2B PACKAGERXL Error - pxl.exe has stopped working
4 w" G" i' _# |$ ~1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters, D7 x/ k- v. D
1131764 ALLEGRO_EDITOR EDIT_ETCH Line segment will not slide using the New Slide.
" h; q2 _ S3 b$ {. Q/ s1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.
* W9 G: z& q: R: B1133311 ALLEGRO_EDITOR SKILL ?origin switch is not working correctly with axlTransformObject while rotating shapes
5 z$ Y) h( |/ y" }2 q% X1133893 SIP_LAYOUT IMPORT_DATA netlist-In Wizard crashes& P; Q; v' `: c3 w, c+ j/ F3 R
8 x. [! g3 i3 X* a3 l* J* P+ lDATE: 04-26-2013 HOTFIX VERSION: 008
% j8 t6 M8 y6 B5 z4 E5 M, W) T3 w/ g# \===================================================================================================================================
" l! F2 d9 u% c) L7 zCCRID PRODUCT PRODUCTLEVEL2 TITLE- D/ Z% u9 {' ^8 z7 s
===================================================================================================================================- V3 l9 `' c% c5 u6 n! o8 Q
876711 ALLEGRO_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit
% n5 Y9 r F" L: y9 G, z1 H, A1080386 CONCEPT_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation
2 x: S% a2 E Q( y% H1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device
7 ^+ P- K x2 ?5 A9 ~# y5 q; e1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.( a. ?: y7 M, ]% D! r% b! A
1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section* k5 P) T- M3 _, H6 C
1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running
) U8 w3 z0 O* `1 \1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.6 N5 m' N5 F- U$ s+ l- D' j
1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence
( i' L E7 m2 G' H) e6 a1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.
; a, z& Q' ?0 z1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason8 o0 A2 f" L$ n5 ]* ^. u; G2 [4 S' |
1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations." p& [3 h* W! L" i: ]
1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?
* y9 w3 p% G( v) Y1120414 ADW LRM TDO Cache design issue$ J! x5 |4 _7 v
1121044 SIP_LAYOUT SKILL axlDBAssignNet returns t even when no net name is assigned to via" [' z. w$ ^2 Z( e! ]
1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups1 J5 R. X# {6 L5 e7 A7 x% z
1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it0 ]" X' v y4 z- J
1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM., g9 g' Z+ s5 {* Q+ p0 z* v x! g& [ b! U
1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced
9 h' y+ o8 J; l. p& ?4 `1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.( O* ^0 P' M3 |( |) C9 Y
1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable7 e( [, k6 C" c7 ~
1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file
# W2 I: [0 ~* j1123816 CAPTURE PART_EDITOR Movement of pin in part editor6 e2 r( [7 P6 @
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50
; ^. _1 N8 W1 i. v* Q5 b( E8 o* ~; S m
DATE: 04-13-2013 HOTFIX VERSION: 007; g; Q% z* [8 u( u4 Z5 W: K0 q* e
===================================================================================================================================- K/ w! K& ?+ w! h. ?
CCRID PRODUCT PRODUCTLEVEL2 TITLE+ u' o, v V f/ v
===================================================================================================================================8 C, v, k$ i! b" g# H
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die Y& `8 c( T4 K6 I# C
1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.62 O( I3 ^% K }( S6 B8 @7 D7 L8 V
1112295 APD DXF_IF Padstacks� offset Y cannot be caught by DXF.
, X3 [% Z N2 z8 f9 H! D1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components0 [5 t! B+ Z; B( j! m' j9 Q
1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
4 ~9 J3 x" h/ k* Q7 R1115491 ALLEGRO_EDITOR SKILL telskill freezes command window
2 T$ ~5 q/ C- w* R" w0 |5 a1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
3 l, E# ?7 N! }: O8 S1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.7 ~- B4 l/ U4 @! Z5 U( q, U
1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear
: a$ [+ q3 v6 e. w! ]1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks
8 W; y3 L/ U( _( ^, ?( \3 S( t1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?
- ^+ D/ J2 k4 f5 o$ E3 N1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh! f2 k5 [7 I7 V
1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh
M1 v) a$ G9 P1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors' g, q% w% {, n+ ~$ L
1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.65 W1 a- O6 j& N I& K& t
1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently) |) q$ ~0 W7 f- { r9 w3 c, L
1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps
' o, L" `4 V* q2 i9 y2 u1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks
: C- q5 | [- z1 t1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.
. k+ L A8 [, `7 N0 @' u0 f. `! s6 @# F$ }, M4 B9 U
DATE: 03-29-2013 HOTFIX VERSION: 006% w* h5 p5 s) X/ A
===================================================================================================================================3 b, I5 V+ k/ M7 r5 H0 b, b* g V- c
CCRID PRODUCT PRODUCTLEVEL2 TITLE
& Y% S; e* p: W7 |% n===================================================================================================================================
( r% B h: y# C2 M! c: o; C( R9 W625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.
) f5 b$ o. Q1 W( O) ?# m* E. d642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep! c: C- u$ G8 N
650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".
) \4 r% |& F# g* O4 S! Z7 W- ?653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend( K. F3 K3 d0 Y# C
687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect$ a( \% b. d2 M; f# T
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
2 D; g9 ~4 H5 P. N- y( Q825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
$ a+ F/ F3 G+ S1 R# q* @8 p- B4 V834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming' c3 N- P( w E2 g/ @
835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.* x& t1 R( i; U
868981 SCM SETUP SCM responds slow when trying to browse signal integrity
1 }( d6 E$ v$ Z4 i871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
. Y ~& _* f2 h+ ~" U/ \/ m873917 CONCEPT_HDL CORE Markers dialog is not refreshed
5 N* w' w# \: I: L0 L, V/ p887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
/ L: f$ F# N0 ]! n6 f$ d4 L888290 APD DIE_GENERATOR Die Generation Improvement3 n! D h9 {7 W8 g" `7 u
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator. A' {4 g1 A# [; n4 F* K5 G9 W% [% m
902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice- O6 R; {/ \6 U) X) y* G
908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM# ~: a; k V& _
922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols4 n) q* i3 k+ r) `/ `2 ~
923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences
) \! \8 k! s1 P& [4 m, @935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC& t9 v$ j; l3 i& D; i
945393 FSP OTHER group contigous pin support enhancement
- O7 }1 \ \0 l% O. X; }969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database* n, Y( z6 E; V# _9 e+ x; |3 M
1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes& P1 d) x4 z8 i6 r& f8 X- ~! i, c" s: |
1005812 F2B BOM bomhdl fails on bigger SCM Projects: F2 K% m7 ]0 k1 e% H. C+ O
1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture* k: J; f: i2 N* s$ m7 b: O8 I+ Z6 l- ?
1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names% N7 { Q. Y0 Q" T* J) t
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net1 ]2 e. C" p6 B6 p
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical, C( }3 w4 W* ]6 l. I$ R$ F1 a
1032387 FSP OTHER Pointer to set Mapping file for project based library. C b, i4 U1 V, Z z5 k6 B
1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with 縋LL PLL_3 does not exist in device instance�6 v8 b- m8 _, T" m9 z$ _! x
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
# M1 v( ~) i, m7 v6 n$ L# y4 d1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding r" s- F" ]7 `) r2 I
1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.
2 M' v4 j& _: |# ^1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type
* D- E( x0 m. j* l1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll' i% u8 z+ I: P& h# g" F. {* z0 b
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation1 M& `9 n2 ^( [ d6 j, R( Y2 c( [
1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects1 \0 T5 b6 i/ g! E' ^6 t/ J8 k
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus
6 A7 Z% L, u' B J1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts) P3 [4 P0 f$ B# r
1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs
* @; ^. b8 J3 I x1065636 CONCEPT_HDL OTHER Text not visible in published pdf
& u2 K8 j5 p* i0 @4 x. }, R1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings8 Z# f/ F& L4 E7 f9 d3 m6 a
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary( d" v4 e$ R6 G \3 s/ H
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts2 B# z! K; E2 ?% b/ |7 c$ T6 I: C" S
1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic( B ]3 g9 v4 @) s- O$ c: M
1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down
# w' r8 U4 y5 z1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45
4 Y1 `( I E+ h5 P/ p$ _1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal
( s7 m. \, U+ q' G1 k9 m% L* y1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
2 @$ M$ b4 E: X: T6 p" Z1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.
" m* \' |: N# j* h% [9 P7 v1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)
% z8 E% O% M9 {) W- f1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die& k E5 G1 |" z6 L) g4 L# P6 ~
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic& O3 |" L/ l, ^
1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut
7 a1 Y) {) c7 V6 V5 {8 N5 {1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects) v4 s( N) d+ t3 x( g8 l
1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format; S' \% Q# \: V
1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net! U9 [: L/ X. k" g* e
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
3 q9 t& G0 B3 m4 G0 m; ]& s8 J4 d' y1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
0 J+ W) W( ~" G4 w# r1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.( t# P4 H# C+ D+ N; k
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.
7 \( h& K" N. ^ J4 e( d0 D1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors
! d, ]& e' c" a! |, s/ q1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.6 g7 W* s4 e2 K: O+ O& f; b( {
1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition
; R: x' D: M, N2 f/ O4 ]1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor- q+ ^' s c7 s* R. }
1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
2 P, a6 ~% B" v- _# ^# ?1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5$ E( M1 _5 v9 Y
1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.
J- R, n+ ~9 d* i1 o* d4 w1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate, }3 T/ A4 B1 T# {7 p
1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3* v! h& j5 o! b( X" @% p2 D2 ^$ T5 A
1078270 SCM UI Physical net is not unique or not valid
$ d0 l, |7 Y$ V+ C. C+ H0 [. z1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted
5 x( h* F% a/ {( h9 E1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle
; s2 g* u& x1 {* r7 [6 X1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs
* Y) a" c( p2 d$ H9 y o8 R: p1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"" K6 H* k* H2 x
1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters! k. Y% ?: H2 t1 Z
1080336 CONCEPT_HDL CORE Backannotation error message ehnancement
3 }+ c. e7 a4 {" S4 M& F1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license
( x! G- i; R' x4 O! a$ m4 G1 {1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd- E1 l4 T- c: G" |% p( v
1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error
/ y* H/ m G8 a1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.
4 ~ e0 H( e$ u. R1081760 FSP CONFIG_SETTINGS Content of 縁PGA Input/Output Onchip termination� columns resets after update csv command
& A$ Y& _3 O8 [' W. l: C1082220 FLOWS OTHER Error SPCOCV-353
7 {3 g. c+ g! ~- l" g+ M1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.
0 _; d3 M+ V' C3 `) ]8 q1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command
: _3 C3 n: J' R1 R$ C1082737 CAPTURE GENERAL The 緼rea select� icon shows wrong icon in Capture canvas.
1 l# w! H, k2 _& j9 Q* g1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name
+ b" F6 Z0 B7 x- i9 k5 A2 Y- N1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way1 |3 I, c) u z
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher) M# h$ ^5 a( M7 j' ?. P
1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI
: _+ W; V7 p* h* C- R2 P1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
3 A; u. c) n! b4 H3 ]1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.1 x2 \- P9 l0 a2 u$ g! e8 G0 | y. j
1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates! C6 h9 h$ u" q. u
1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters' [( u, S& ]; R8 _9 J, R L3 P) |
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.6 A0 G) P5 j* E0 a
1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results! W/ P# e8 ?8 y5 w
1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file. k, X* L! y0 w3 `% Y2 f; s9 Z
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update) \6 _$ ?: m5 F% t; g o+ X; O1 c5 s
1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO% N; e4 E/ L. v- z- i3 l4 ?
1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working
: w% Z, `4 o% i8 |7 b1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.3 A. t* M. \, @3 @* h/ f
1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design, f; B/ s% ^! E3 Y
1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated- a$ A) J+ Z6 u# I9 j
1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins
: `2 @( n8 [# _* g( I: p. _0 @1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity
/ Q' k5 |* G# J% B2 S1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.
/ ] L4 L7 v8 c1087221 CONCEPT_HDL OTHER Part manager could not update any parts.
/ M Q: c% h1 C) `1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space" w/ E F, L: S6 O/ L: U+ _# d
1087295 SIP_LAYOUT EXPORT_DATA Enable "Package Overlay File for IC" for concurrent co-design dies too
9 ?$ e& G% }* X; b5 P3 a" D! t1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice
* ? k4 A. C5 S8 L: N+ s1088231 F2B PACKAGERXL Design fails to package in 16.5
, @4 k4 P! b8 @- h% d3 O8 j1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.
; m: I6 ^! P7 |! j1 Z* b1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor0 F" @! W n# I7 K+ @
1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager4 ]1 }, M. K3 k- K% p
1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?8 i6 y o. O {* t* u8 M k
1089259 SCM IMPORTS Cannot import block into ASA design' v, f5 W \2 @7 I5 I+ [) u
1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form
; k6 u2 M1 \; `: n+ L% ^- e6 r1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project3 l. l( ?! t! _
1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory
- z& v4 I$ J$ P! a( W5 A( C1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor. ?6 \) R( W9 E1 _ s
1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165
2 C0 v6 I: k( S# S1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.$ \( c& K1 p& f% H8 n j
1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-220 g( K6 @& ?) Z: Z9 V! y
1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.9 L E6 x+ |. `7 f: ?8 i
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
! n/ }0 s) x/ h! I( |1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled6 @" {. Q2 j% N+ W6 F
1091359 CAPTURE GENERAL Toolbar Customization missing description' L2 a" d# p$ M2 c$ u$ W
1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
' s' i3 D8 M0 [) O* s6 K) y" l$ J1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time
Z0 S% _3 A( l K1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5
! h4 O- K% b9 e8 i1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design6 t/ A$ v6 Q9 w* ^% {$ }" d z
1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled$ y) g/ M* {8 ^/ E0 ^. h
1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters
6 W& T3 k/ A* v; a: ~, `1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error0 {: ]/ E+ V6 W8 V3 L
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder
4 u3 p" b, z' o8 m7 v3 d [3 W1093327 CONCEPT_HDL OTHER Getting error SPCODD � 369 Unable to load physical part in variant editor
: y) h' f5 S. C* @; u( ?1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
8 A' ~. u! a4 u& b4 x1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time
+ j" i$ o6 x$ `# L4 Q/ @ o1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save." @$ F, _& w# L
1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?+ a% N) c5 w t' l# B8 {6 [
1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic4 W2 E8 |! l0 D3 E9 @! r
1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.58 J W1 E+ W! d+ v
1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet( S( J7 x* M8 F8 T
1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die
( P* k3 W' m: U" R1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block
8 s% }0 O6 K# e y" v: L5 Z1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3
* U. k( o F- R4 M/ R6 o: W1095861 F2B BOM Using Upper-case Input produces incorrect BOM results: }, J* V# @; i; r& Z" {1 x
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import1 k0 O9 Q9 r/ s0 f |) g
1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
. v9 u( j3 S9 [1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias6 ?- ]* ]/ M& P* ]
1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate) w' V2 i1 W9 D, D" q) G) S
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
/ b5 s; h8 J8 p I1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL l* p/ `/ n) s: Z- `( E! y8 }+ F
1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.
- v2 n& V+ Q8 N7 c$ t1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side5 w' ~7 U* t" a7 ^
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command7 Z" g( Y& R# L: s
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
% Q$ {8 J" F; v8 ?1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives
# Q" v F, }0 g1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork
: U% h A$ ~4 M& M: _# U$ A5 N1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts
6 V* `0 {9 T1 i5 k, h4 @: H1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy
! H! M4 `: F9 Q' B5 i4 @1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.
7 Y2 z1 J" t' Y1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties. L" l6 t, Y" x' S' s
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.67 s# q2 v H4 q4 |+ X# N
1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad
1 v3 _- a! [) O4 e2 D9 V" w0 `: I1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P38 z |9 x& v9 [* y
1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad
6 d& g0 w6 X7 Z/ y( q1103703 F2B DESIGNSYNC Toolcrash with Design Differences
: k7 L8 E% c. k" f1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view
9 M t" F+ O, O6 y* h6 \1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6" N, j) w4 B, }- d- ]6 O, X
1104121 PSPICE AA_OPT 縋arameter Selection� window not showing all the components : on WinXP( {1 Y% h3 b: ~/ b' ^: A, Y+ V
1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly m1 A) P# _0 }* v0 W, }# ?2 o7 l
1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM
1 C4 J8 }3 `+ G1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.- K: R- A/ O/ d1 d
1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.) } J* R" W' H2 Q
1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form
2 R/ s/ ]- `# O7 `1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part; c+ V0 j0 |- L2 r2 y
1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked
/ t. R4 P/ l" ~1 a( _1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
- f* V* [ z* g5 }1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.66 V) k. e. k* g' N6 t! b, o8 I
1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only
! @- K; o! r# w4 l: \/ b4 \' S. z1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid$ K* V$ F+ q R5 b5 N8 c2 E& \
1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support. m. Z$ h$ d5 d; q
1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param/ n8 l: ~, n5 p7 U
1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish
2 c# e5 i0 `# O8 J1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).
9 c& P, B2 ^! m% u8 s( X1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke8 _- K, f+ v6 L! H2 g
1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.
4 b$ v. s/ f6 I' s# O( I3 H: t. Y1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode& Y. w) D1 K: c
1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs
& ^/ w' S. O' Q3 K& M1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6
3 _7 ]3 R& q, ]6 h/ J a% ~( ~1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.5 J8 \) S1 ^+ Y/ q8 C
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON2 a/ C, x- Z+ ?7 w* G' m
1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6" b' z1 a3 Y; s( C- J6 i, I; o
1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset0 n T3 n/ ~- p& j, @) U& W8 `* [
1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters
* t* M; p6 K B3 Z5 o+ ?6 a1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend R. e9 z# a/ O8 c, O
1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP
G( ^6 r5 R% {3 U5 @6 e0 U4 J5 ^1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint
1 x, A4 g; R* S% z1112774 GRE CORE Allegro GRE not able to commit plan after topological plan5 x6 U- q! T: @& I; T
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.
9 Y9 T7 F, Q2 T. G* P1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file9 k$ \2 D8 W: ?8 d/ C; y
1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6) j: y! a: G/ j; z, w1 t
3 p8 ]' P# _- ~ r# P3 Q& |DATE: 03-7-2013 HOTFIX VERSION: 0057 d; J3 P' x. K9 J, v
===================================================================================================================================
, G$ p- i% G: h, ^! E+ D0 UCCRID PRODUCT PRODUCTLEVEL2 TITLE
* i# x/ T6 c. @ }" y=================================================================================================================================== e" t* J5 F' V2 n' q& t3 l
1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 1102
) v4 @+ X7 E* b) g1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed
8 H/ U/ F, H% n$ H( b1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently& t+ s2 [8 r3 O- I
1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind
3 r; S! O1 G7 h3 X* p% L+ D1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view
- u7 |7 O2 X/ H I: }1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed
$ ^, q2 _" {) s: f5 U- {1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM
% X$ @2 d' o6 k. ~: H1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.6. |- D( G1 e+ E% V1 T
1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement.
, w. p* K, u+ w9 h1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design
$ R, `+ m( l. y% R( [5 m! @1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in OrCAD PCB Editor Professional$ P" K: P& s q9 }& `1 Q. P
. _; }- @+ k9 l
DATE: 02-22-2013 HOTFIX VERSION: 0044 y: S% V8 [7 f6 D
===================================================================================================================================) V, ~ |; V5 D9 [) _ s3 X! l% o9 n
CCRID PRODUCT PRODUCTLEVEL2 TITLE! |; o' V, Q: ^+ @' p+ D# @& K3 O
===================================================================================================================================
. O: h) u- M, B: }1081026 ALLEGRO_EDITOR GRAPHICS 3D Viewer do not show the height for the embedded component correctly
8 U6 A, F4 B$ v+ J+ H1095225 ALLEGRO_EDITOR EDIT_ETCH The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing. `/ v! I* ]9 R/ I. d; Y/ E
1096356 ALLEGRO_EDITOR DATABASE Cannot Analyze a Matched Group in CM+ k/ Q; }$ f$ J, q# i9 I
1097481 ALLEGRO_EDITOR INTERACTIV Allow replace padstack command in design partition+ u. z7 A6 A/ Q3 R! I. A" n; A3 L2 v) n$ i
1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend* f# \ j: ]) z1 h- f$ H
1099958 ALLEGRO_EDITOR PAD_EDITOR Library Drill Report producing an empty report
9 ?7 ~, k- O$ w$ X1100401 ALLEGRO_EDITOR OTHER Invalid switch message for "m" for a2dxf command
) n1 d2 M2 z' g6 _& c/ m& ^. h1101026 ALLEGRO_EDITOR OTHER utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit.
5 M! N9 U" K- k8 D; i0 N1101064 SIP_LAYOUT SHAPE 'Shape force update creates a rat
) X1 h( I3 @% X1102798 SIP_LAYOUT OTHER Stream out puts offset pad in wrong position if pad is mirrored but not rotated.% H6 t, i: |5 Z5 {* ?/ H
" O' J% m9 t) j8 P8 ^DATE: 02-8-2013 HOTFIX VERSION: 003. t$ {/ O" Y& y( @4 r
===================================================================================================================================
/ f s& ~. ]0 o5 uCCRID PRODUCT PRODUCTLEVEL2 TITLE3 s1 ~$ w! U) W4 O- J5 c% p( R4 ?& x
===================================================================================================================================1 J% i! l7 b. _$ h% a* u9 H2 b' P
1077728 APD EXTRACT Extracta.exe generate the incorrect result
3 ~7 ~, g* K& T5 Y5 ^! ?6 j% D1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF' Q% K/ Y; E: w& ^# E
1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer) u$ f% J) L5 W3 a8 E
1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.& L: W& Q K8 R
1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on0 Z, m" N7 W- F, E$ c6 ]
1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent* _) J! n0 J6 n! g) Y* v% F
1094788 SIP_LAYOUT WIREBOND Wirebond edit move command: `' c5 H$ w/ e# U
1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor
) z" K' Z h2 r1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn縯 show up after 縎uppress unconnected pads� option.
6 D1 E" u2 O. W6 T1 K1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff
3 \* p+ \/ ~% D. q1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible! Y& W" `! k, `/ S- u
1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35
% ~" \! n/ B9 Q* v1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.
6 Q5 B! X1 k! k+ z5 L* J j; q1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.. _+ {7 M; _8 s) R
1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.: l# `' H) u z" a6 |
0 a- i8 n; [+ N c3 V. f( sDATE: 1-25-2013 HOTFIX VERSION: 002
1 E: c6 d: f# e===================================================================================================================================
2 }, O+ {: g6 x: M o, I0 ZCCRID PRODUCT PRODUCTLEVEL2 TITLE* C2 ]5 ^# h0 T: W7 p2 P
===================================================================================================================================
* k) I8 P: G: o7 o! \2 x491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute
5 G$ e9 W! C2 Q% k" T a9 b: E+ O863928 ALLEGRO_EDITOR INTERACTIV Segment over void higlights false "nets with arc"
5 R! J4 D2 y/ @- J1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes9 h: m4 X9 X. i/ W
1074820 ALLEGRO_EDITOR GRAPHICS losing infinite cursor tracking after selecting the add text command with opengl enable
5 W# L4 U; x1 }- Z7 g1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33
) }- L0 T+ o, x1076986 APD WIREBOND Wirebond Adjust Min DRC does not maintain the finger position in the same sequence% n( S$ x2 F+ F* r# Y8 z: b1 S
1078031 SIG_INTEGRITY REPORTS Requesting improvement to progress indicator for report generator
$ E5 x: W% q" O2 g N0 ?1080213 SIP_LAYOUT WIREBOND Wrong behavior of Redistribute Fingers Command
2 I1 v6 v# r6 k5 ^: w% ]1080667 ALLEGRO_EDITOR GRAPHICS Allegro lines with fonts not displayed correctly in 16.6( Q2 d3 O; w/ d4 G4 {
1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note.
. [! ?" R- R* Q9 N1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete." H* |4 l1 J% v: r, c
1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL.
9 u" b6 O, G. U- Q5 j) A2 |; ~! _1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0
# D# e# i3 X% Q, e$ J2 @1082595 ALLEGRO_EDITOR COLOR Infinite cursor remains white even we change background to white. k( k+ A: J# K# T- w
1082704 ALLEGRO_EDITOR GRAPHICS infinite cursor disappears when using Display>Measure
4 M, i0 g; c5 X' C# E: B1082715 SIG_EXPLORER INTERACTIV Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer
2 q4 g& M) r1 X$ b! M Q9 S1082774 ALLEGRO_EDITOR TECHFILE Import techfile command terminates abnormally when importing a generic techfile.- N( w" ^% _+ }2 q) k6 [
1082820 CONSTRAINT_MGR UI_FORMS The configure generic cross-section pull downs do not work.
+ w' X0 v, Z; Q* a1083133 SIP_LAYOUT INTERACTIVE SiP will crash when using the beta Pad Rename command to change a BGA pads name.
$ S( |# O+ {- l9 A1083158 ALLEGRO_EDITOR GRAPHICS The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.6- U* R6 ^4 Y' g7 _ d. P
1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout
, E: \" [3 o$ F6 \9 m& z1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file
# b, w4 v1 c1 i% \1 `1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing.; H" g' {1 T: b' N0 c0 `; o. M# r
1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.' R6 b [+ A: T
1084166 SIP_LAYOUT DIE_ABSTRACT_IF Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties
0 c% H! I( x3 S9 O1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error
5 I; L6 ?, D* S1 X0 r1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric
( U# L1 J% P# e* v% Q1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol.. b4 j/ o# j. R* h6 ^! D
1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue% b6 q' e; f9 ~- G# [
1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command
" e/ i# G) Y/ z1085139 ALLEGRO_EDITOR GRAPHICS Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled
' Y$ j7 \4 ]; P6 w; p1085187 SIP_LAYOUT INTERFACE_PLANNE netrev with overwrite constraints fatal error
" `; w5 j* p" F* |' u1086402 ALLEGRO_EDITOR GRAPHICS Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled.0 l! {- o# [3 l7 M) X' J6 E( Y
1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function
% @( D2 h: n# C3 f% [( {7 o1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command.
5 [9 `# }9 E4 ]1 l6 b- P( s0 s1088412 SCM CONCEPT_IMPORT why reimport block adds _1 to the netnames?+ x, [ C o) U) A7 O2 h+ U9 m
1088958 CONSTRAINT_MGR INTERACTIV annot create Differential Pairs out of nets that belongs to a Net Group F. j( B$ y, v0 R( h
1089336 ALLEGRO_EDITOR GRAPHICS infinite cursor and pcb_cursor_angle+ x2 @/ z4 I& n2 w3 g: K
1090689 ADW LRM LRM: Unable to select any Row regardless of Status
9 o! O) H* m. _% d- F2 a2 \+ J4 O1090955 ALLEGRO_EDITOR OTHER Cancel command crashes PCB Editor when add rectangle* a6 @3 c8 V- d6 E
1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas.- A7 N- {% H0 L l' W
1091218 ADW LRM LRM is not worked for the block design of included project
( ^2 M$ G! t+ W1 E1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads" U! k! P8 @* S$ k9 Z
1091706 ALLEGRO_EDITOR EDIT_ETCH Allegro crash while routing after setting variable acon_no_impedance_width
( h& O/ C, g5 ^. H0 L1092916 CAPTURE OTHER Capture crash
4 t2 g" ]$ v( H G3 [1093573 ALLEGRO_EDITOR DATABASE team design opening workflow manager crashes allegro. possibly corrupt database
; t, C! B0 w2 t- J& h% n4 L! B# {$ w4 H" v6 k7 V/ x
DATE: 12-18-2012 HOTFIX VERSION: 001. v' V( _5 m1 J9 ^& ^7 P
===================================================================================================================================
6 f9 X" |) j5 a. u. cCCRID PRODUCT PRODUCTLEVEL2 TITLE8 s" }$ o* R5 o' K# H6 u
===================================================================================================================================5 x: ~7 n' S. ~& `2 L9 c, X; O' B
501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap" S" S- P0 l4 f) x& y* E8 I1 G* W
745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched2 d7 b6 O v: }, n" |# x, V
825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted
, ]/ `, L( \) _. m- L6 R' [871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash5 P7 W4 ?/ _* v) G9 z$ m- J
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
) K. y* u% D9 c H9 ]# |898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore
( h+ n/ |- U! g! A8 \923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties! A2 P, ^2 Z7 Y: k$ O1 H& b
938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic* [& [+ E ]; k# S9 E& }
947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.& Y8 K1 c3 ~9 e. R
968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing$ K+ f# l% Q! W( n* Z
976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
3 @# U% i" s- J! J L% D981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected. B9 d' G4 e/ y2 D X5 ~8 U2 D" d
982273 SCM OTHER Package radio button is grayed out
$ L2 {/ q* d) T) M, ~$ b988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command
) X( C( Y, S0 x) D& I k* p, K989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode
4 R9 }3 Y) n+ f0 t993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).) G" \( }+ a! q8 G
996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections! X: \: c, s6 H* J
997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
a1 Z; W6 B: f+ g3 z3 O1 Z4 e1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model+ I1 A$ H% r- E% e) k2 u
1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs6 |( X$ B% M) H. p! M) |1 }) s
1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg
! w5 t: }" u& n8 `, H+ w! ^7 u; l1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
9 X' ~7 K" v- @7 T/ m5 s. q1016859 SCM REPORTS dsreportgen exits with %errorlevel%. g0 f, J% W, o' c3 H+ B7 w% _
1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin
+ B) ^! ~% a3 F1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs
3 ^/ ^% x X$ H# ]% Y1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts2 z1 }) x/ B3 ]) R9 ^
1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
; Y1 ]0 w( A5 N* S6 g1 W0 K9 J1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.
# B0 d2 j* K) `/ X1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button( E2 N; S( c3 A1 G; ?! L
1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out
2 k8 l, u9 u% P: \1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist
4 f1 X- @7 n: a" q/ y2 M' @1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed
4 l, k; G1 q' H9 [1035624 CONCEPT_HDL CORE Options pre-selected when launching base product
$ Z M! v8 Z8 j) ?9 E+ N1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly
, c0 H: ?, }' T" e4 [1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.
4 P* z5 S! B4 }; l( O, m* k1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
6 L6 w3 d3 T! C3 q# q4 I1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol- X5 F- U* ~8 P- ]
1038285 SCM UI Restore the option to launch DE-HDL after schgen.
6 E% L1 \6 p& W1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."; b) u% w6 ]( P
1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro
( Q- G( x* Q% s) ?- O# v1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected
0 Z! F- s. l7 T% s# t1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing6 g" `# J+ w* @$ t$ z; q
1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found.
+ F! q, ?. A% v5 M# a1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.
/ E) @- N ?+ p5 e! n4 ~1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu
9 E1 C8 ^+ n5 B$ [1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.
3 s4 N" F% B D8 m, z1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow+ o6 }8 h# Z( c% H- X+ f
1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory
* F2 m ~* s4 N; p( G. P y1043903 GRE GLOBAL This design crashes during planning phases in GRE.
, I; T- L7 ?+ [. a" Y! A) f1044029 PSPICE ENCRYPTION Encrypted lib not working for attached1 [# K3 }4 ~! z* o d! Z/ d
1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory$ X' ~: R% G6 c* Y1 c* P9 g
1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.1 h [, w0 d8 G
1044577 GRE CORE Plan > Topological either crashes or hangs GRE
. o9 L1 W9 z0 a4 o/ N6 S" H1044687 TDA CORE tda does not get launched if java is not installed f" }8 e1 [1 D' p/ {. E( m
1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die
6 ]# N% ?2 q; M7 J$ o' x3 Z1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form./ N7 H- I" F6 i
1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?
2 @: a& W& g' q* X. D4 l# r# m1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.
: T! O2 e+ T' c' R7 t+ S0 Z3 ?3 y1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.4 T9 Z% ^1 G/ V m9 [/ ]. c5 k
1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow
9 K+ M5 Y, N! Y1 L1 }3 r+ X% u1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.* S0 C6 e% T3 i) p" o
1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill
9 \- L: V3 t; h! i8 ~ Q3 Y1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.' a8 `3 e' M& F! ` @& e" j$ X+ L: X
1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.54 q! A1 u$ P, I( I, E
1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5
. y. |" }% \- f1 H1 A2 z% p1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value3 M" u3 r0 j8 a6 G: C) @, X0 l
1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version3 {) p9 y, `4 N' I
1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn縯.! M9 h& J5 b( b5 A3 |' W
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.3 j3 H) L% a u' E$ v
1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.
" }- q, T! e8 [2 i1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes
: h% {. E/ q- w: N1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.3 O" {6 X$ V" w8 T5 B0 ^' s+ O, ]
1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3' k* d/ T- l" |- m1 a
1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file
$ |& D9 x; T6 Z+ x1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors
3 i1 [5 K; S8 J5 k# B) J$ k" y1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.
( } E, ?$ n- h: o* C3 D/ [1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.- h5 L+ J' k; v7 h: @8 V* X* u
1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design
$ ^ I8 d3 Y+ K) F8 O+ C1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs7 w/ J( [3 h7 [' q ]
1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label5 y/ e: w% e3 U) t2 V: z- g
1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.
7 [' V' C+ C# M1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy, w/ k, [8 n( _, `4 b
1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down( l* G0 u2 g& ~; v
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection/ z( X7 X9 `. [6 j7 A
1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.
f5 T3 d6 b* X: F8 @8 E' X" U1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views8 O. D* { l, y3 k6 }) W
1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline* O3 ~# l6 z/ L; l, ^
1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.5 j6 M3 i5 M/ r( F; _0 z2 o
1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created.
' t8 o/ l1 K% N; D8 t4 [1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move
?' ]' o: ]+ `# W3 @% T1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value. S( Z5 D4 r1 {: [* L3 P4 x
1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer% |! h) a" X, X, [8 E
1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report( y% Q5 l& ^5 u% P4 t! w
1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.
3 K" X1 `1 S) h# @( ]" B1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete
0 N: l k4 t$ l9 q/ Z1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
, r" C/ F1 k5 j1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets; M2 D; g- M4 @4 S! Y% `
1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?
, c7 K, q' b5 K) J- G; P1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.' M8 o; w* ]6 G1 u& a) ^5 g) ~
1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished.
5 f$ D4 d6 @0 Q1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 003 q6 X3 S/ Q% q$ ], `" A
1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
" h+ x$ E+ J& U* i; m8 n1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed.
0 q1 v8 L, K+ Q6 a1063284 PCB_LIBRARIAN OTHER PDV Save As is broken
* O/ }& h- [% A1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs J0 u, `+ k# p$ y( S
1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.
3 x* T9 U* x: c* H* r7 u1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.
6 l+ f) y! i3 @ D: k1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design1 M/ h0 u: v, U5 h! M
1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV
# _# l$ a/ `- d1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green.: N% J" l u& J" f0 S8 W
1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X
! G) t/ s) L0 `: {1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application% m6 [4 G) g* r6 x
1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report
5 T/ c9 G7 j7 @5 F7 m3 \0 f5 i1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
; d4 e8 h8 E; \5 [- U1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic2 L% m" b1 `. h! V
1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.+ N- S a$ u5 J3 H, ~; Z
1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file
3 k+ a+ U( l% K5 f1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command
6 i0 g, l4 l5 \: b; B- O& M& O% y, E1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended# V: t. R6 `+ h2 a4 S9 ^. }' `
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067
- S c. s* ]: m J) l2 M1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design8 a: R/ \% K3 F
1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify
: j. i0 ~' T+ S1 G# F6 P9 \: o+ @$ I2 X1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids$ F( }" G" ]4 q5 t
1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes
) C+ v& d6 J, v' C" i0 l+ J1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow
8 o( o# O6 G; y& c1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal, m" b. d4 @) w w4 }" N/ N( \
1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.: M( z" ?0 p- i, Z( y C3 d9 o
1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6
- l. i$ M. ?' Q' d7 Y' x1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.58 r9 y* d/ k# p/ q" p0 W* U' i6 W. e! V
1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode.
3 W! n. K) E+ x) B9 ^0 V0 \% Z# V1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
0 ~' ]* u0 H0 \% J1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor
& w" h( U9 x, L' X. M3 l1073464 SCM SCHGEN Schgen never completes.; O" f6 n% e7 x
1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory4 u! v! h( ?3 N. O+ p
1073745 CONCEPT_HDL CORE Import design fails
8 V6 g* [$ {! c% v! l1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'
, } g9 a$ V1 k+ V2 D8 C1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE
9 @; D; w2 i2 s! l" ~. W3 U4 G1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist
1 U3 {* b4 R: p- A: Q1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter# ~( S6 z0 z! z" T
1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal: v& z' _& t4 j) N: W t
1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.& [) P; e' d, d! \
1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI
% K7 ~. v* J% p5 U% z# e1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block# i% }9 k$ g0 F; Q9 e5 g
1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer( r4 e1 ` h6 V8 r
1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces; q! ^* J* Z; J& ^5 ~
1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2
% |2 v+ @5 p4 R' e1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix; @; K M( V" B2 h0 X4 g+ [
1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes6 J7 Z& z6 P8 V
1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top5 M1 x8 k" [& H4 Y" D0 W4 G
1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas.6 m5 {' r' [- d* A4 k4 {7 x
1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value
9 Y0 ]" S% p( T, m" E- s1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.6
" T$ y, y& z( O3 G+ `* d1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey8 V- G p5 B2 t7 A# E" S
1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database% T: f l+ H7 p" K
1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset
; j4 k7 r. s- q# p( b1077169 APD SHAPE Shape > Check is producing bogus results.
0 \4 N u3 f1 k; `- B2 A1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board.' C8 P/ y: R% ]: n* L+ p0 Z! Q" v
1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim
- R2 e3 V2 r) ?' F4 j1078380 SCM OTHER Custom template works in Windows but not Linux
7 X( J6 [6 }) J7 V& Z8 U w1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.1 B! x9 F% T: @' k. M/ \' D
1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide
: `) L/ g0 y) E9 @( q1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
8 ~ T3 t$ [& {7 }/ H! u1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"
* ]8 r0 r4 P& D9 C7 ^" v1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text
$ D" ?3 L6 B8 E- X0 {1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control4 h3 _' V. r' ~
1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical.: H/ N" K# r6 @8 i7 ~8 |9 b
1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.$ Q2 t/ R7 X. m* Z8 k. @' J- z: } u
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发表于 2014-7-31 09:06
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