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3 h ?! z3 T/ ?1 {# @/ ]更新说明：) }3 B6 T5 e, I$ v
DATE: 07-25-2014 HOTFIX VERSION: 032' W3 h' }: g+ C9 x
===================================================================================================================================; _4 l( L" { h: @
CCRID PRODUCT PRODUCTLEVEL2 TITLE# r2 E+ H& r; [9 u: U7 _
===================================================================================================================================" j1 B; ~* U6 t6 a
381127 SPECCTRA CROSSTALK Specctra xtalk reports aren't correct. a/ [4 W) @# t
616770 allegro_EDITOR COLOR Remove the APPLY button in the Color Dialog window.
( m- l; Y$ U Y# b4 F( \* H982944 ALLEGRO_EDITOR COLOR seperate the Etch to the Shape and the the Cline in the visibility window
- n! t! P, b$ ~982995 ALLEGRO_EDITOR INTERACTIV Shown infomation for the selected physical symbols5 B8 t8 {4 K" c" ]1 m* t
1024832 Pspice PROBE Shows wrong data & header when exporting trace to .txt. B: T M3 Y+ @: b
1063258 PSPICE AA_OPT curve fit fails with error same data works in 16.5 Simulation error: out of range of data" j4 m4 n9 Y3 _; ?; U9 {! M& ]1 g
1112360 PSPICE AA_OPT Advacne analysis gives runtime error while using Optimizer in attached design
/ A0 R5 L! Z! C8 g- d: U+ u1154323 PCB_LIBRARIAN VERIFICATION Con2con is choosing incorrect Primitive from Chips file and failing FTB Checks) v& d( e: r& A( H! a C
1184690 concept_HDL CORE Weird behavior of genview for split hierarchical blocks/ u9 ^8 F5 ?0 P/ j/ e+ Y" F
1212577 PSPICE MODELEDITOR IBIS translation fails without any information in log file
1 `- `; p% ~; L7 U2 e8 k8 k& P( c1213204 ALLEGRO_EDITOR PLACEMENT Place Manually with existing fixed net behaving incorrectly8 ^9 m& U* k/ O0 S
1213837 ALLEGRO_EDITOR INTERACTIV When copying a stacked via the temp highlight does not display on the last layer of the stack.5 N& n+ v. Z: r& B% b7 d n" f+ H
1216519 SPECCTRA ROUTE Autorouter will not add BB via between uvia within the BGA area% \/ U* z0 J' r
1220655 PSPICE DEHDL_NETLISTER Support for automatic addition for Power source and Ground Node for Globals in DEHDL PSpice netlisting( N+ e9 L3 y+ T+ G
1223018 CAPTURE OTHER Diff pair Auto Setup not working for the buses.
" `0 j+ l5 X5 X: y8 p0 Q5 t1225689 PSPICE AA_SMOKE Smoke analysis crashes with attached testcase& g6 z8 O7 S: k6 `) M
1232124 CONCEPT_HDL COMP_BROWSER unable to generate ppt_options.dat file in first go
6 A% t( D5 X* u8 v: F) Q; p1235059 PCB_LIBRARIAN IMPORT_CSV pin_delays not being imported into PDV# `, D: F2 H6 o" W5 R& s8 ?$ G) q
1238815 CAPTURE OTHER Capture doesn?t retain more than 191 library in add part/capture.ini under part selector configured libraries
0 Q. {0 x9 p- U/ k1239241 ALLEGRO_EDITOR INTERACTIV Via replacement doesn't replace with correct via but right padstack name.
N \" M/ S7 W5 H' S( D1240201 ALLEGRO_EDITOR EDIT_ETCH RPD DRC unresolved evenif HUD turns Green
) F$ V1 E# f5 R2 _: m. P9 c8 Y1240314 PSPICE SIMULATOR Getting internal error,oveRFlow for the second run) _! _5 W# l4 d0 \( C! q5 w" E
1242805 ALLEGRO_EDITOR DRC_CONSTR no_drc_progress_meter variable hangs allegro after running update drc. K5 u- m; @0 m7 A, U/ Q0 n
1243267 ADW TDA URL to TDO-SharePoint should be defined in CPM File
0 Y) z0 K9 \) F9 o# m! ? K1244857 ADW TDA Policy File Variables not working correctly in policy file
* a" Z& B' g2 V* q" \1 e" Y- l; I1245779 CONCEPT_HDL CONSTRAINT_MGR Obsolete objects in DEHDL CM" s6 d% h/ ~8 Q% O) I, Y' G5 {
1246811 CIS EXPLORER Option to keep the part type tree in CIS explorer expanded on every invoke
* g8 i4 O( W& b1 {. Y% z( |& |1246964 PSPICE PROBE Simulation Crashes in 16.6 but running successfully in 16.5
( c7 q2 c" l+ x3 x7 d+ b7 d6 W( k' o1248782 CONCEPT_HDL CORE Display winning physical bus names (occurrence mode) in the the lower block of an Hierarchical design$ @8 O: F1 \) D; `" u, v0 q
1249238 CONCEPT_HDL CORE Uprev from 16.3 splatters text around sch page* i0 e( ?$ z% G; a3 {
1249692 ALLEGRO_EDITOR GRAPHICS 3D Viewer is wrong when resizing its window.
% Q$ w5 z3 g. i0 \1249850 ALLEGRO_EDITOR SHAPE With shape_rki_autoclip Route Keepin to Shape DRC is created
: Y3 {1 E5 R1 Q1250683 ALLEGRO_EDITOR INTERACTIV devpath corrupts if edited from user preferences.
, p( d7 L; I- w& a. h8 A. G$ J0 r, f1252059 ALLEGRO_EDITOR INTERACTIV Preference Editor is unable to delete a previous path entry for library paths) w$ T& O% P; q! m: x9 p2 T
1253563 SIP_LAYOUT DEGASSING Not getting degassing voids when close to shape in center of design# ~" w- J5 ]( X( a: p6 a; d
1254319 ALLEGRO_EDITOR GRAPHICS ENH: Functionality to change the 3D Model color for more realistic view
$ { N: x+ |. L# F: b1 `9 p1254562 ALLEGRO_EDITOR DATABASE Unable to delete a subclass that exist only on classes Package Keepout, Package Keepin and Route Keepin.
3 S6 f0 Y* H5 [# J' m7 s9 a# s6 K1255169 CONCEPT_HDL OTHER ADW (BPc) Packager should report the specific corrupt directive in the .cpm file4 x2 ?8 t4 d8 [5 r4 |$ K
1255573 ALLEGRO_EDITOR DRC_CONSTR Need soldermask DRC checks when same net via and smd pad overlaps
1 v! m8 b4 _; a1257950 CONSTRAINT_MGR SCHEM_FTB Changing xnet name on Allegro CM.
- d. c A! b1 l" ?- K8 H1258165 F2B DESIGNVARI changing visibility of Probe_number in variant schematic changes it to $Porbe_number3 g" A! q! B: y7 g# t+ r' e
1258274 PCB_LIBRARIAN VERIFICATION con2con crash with no notification or error message( H; x! T5 l- G
1258860 CAPTURE PROJECT_MANAGER Bug: Text Editor (File> New> VHDL File) filters characters from Text+ j" e. Y6 U: N1 X7 J
1258872 CONCEPT_HDL CORE Objects are copied (instead of moved) when moved from sheet to sheet) C6 V1 ]9 E% R& m5 f3 m- ~
1259284 CONCEPT_HDL PDF HDL_POWER ( global) net does not get transferred to the published pdf
: B" E6 Y5 n n: Z ^+ ?+ y1259375 CONCEPT_HDL CORE Help link to cdnUsers.org needs to be changed
' r0 j7 J0 F/ d" G7 `0 U1259860 ALLEGRO_EDITOR INTERACTIV Edit > Mirror does not display asymmetrical pad correctly when the footprint is attached to cursor./ r1 p4 n. a2 r7 c& B: B
1260002 ALLEGRO_EDITOR INTERACTIV Alt sym hard is not obeyed when using Edit > Move > Mirror0 d/ b2 B1 {9 J& M* u
1260006 ALLEGRO_EDITOR PLACEMENT funckey r iange 90 rotation issue
) R! d5 Q D1 J1260667 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes when running AICC command on few Diff Pair traces.
; B0 K. b; N6 r( ]9 `; F1260763 CONCEPT_HDL CORE Export Physical fails with $TEMP entry in Setup-Tools
" ?* f+ U2 y K$ K2 c7 ?1260847 SIP_LAYOUT SYMB_EDIT_APPMOD Border texts seen as triangles.
2 W- }, C0 ^4 E1260948 ALLEGRO_EDITOR SHAPE Dynamic ground shape is shorting to via of a different net at layer 4 & 5 in this design; ~/ T3 H* Y1 O) V' d, R
1262011 ALLEGRO_EDITOR PLACEMENT Key Properties on Component Instance/ Definition on available to use with Quickplace by Property
+ A/ [& t& ?/ k4 m) z y8 @1 [1262322 ALLEGRO_EDITOR PADS_IN Pads_in can not translate route keepout which specified for the all layers.
{/ {6 z/ m8 @( g2 [1262626 CONCEPT_HDL CORE PROBE NUMBER attributes lost from the nets after upreving the design
' i& J7 e$ L6 o r9 d1263592 PCB_LIBRARIAN VERIFICATION Unable to check in Schematic Model due to pc.db file1 c! B9 Z, k5 P& I% ^ a2 s
1263685 ALLEGRO_EDITOR INTERACTIV Editing Photo Width value from non zero to zero allegro gives warning- Value must be greater or greater to zero, j/ L; ?' }: u- Q! y, B" F/ J
1263704 ALLEGRO_EDITOR EDIT_ETCH Bug - AiTR wrongly deletes blind vias and do reroutes.
4 C" v, f3 u8 i* r& l$ c2 Z! y. B1265120 ALLEGRO_EDITOR SHAPE Require voids in dynamic shapes to use pad value
, I% v# R- I* u1265275 ALLEGRO_EDITOR DRC_TIMING_CHK When XNETS are dissolved by removing the Models all Physical and Spacing NetClass associations are lost" ^7 S6 y. ` ]. g* Y; g
1265633 PSPICE SIMULATOR Bias point result is different in consecutive simulation run of the attached project
7 E8 B6 n; A( q( K4 @1266349 ALLEGRO_EDITOR PLACEMENT Rotating symbol while placement show wrong angle of rotation than the placed angle when Angle is set in Design Parameter
8 Q# S) U; _: u+ ]1267541 PSPICE PROBE pspice.exe does not exit when run from command line
3 l6 G0 c j0 \* }1267707 ALLEGRO_EDITOR PLACEMENT Mirror Command - preselect/postselect bug with general edit mode5 b5 j$ @0 r$ ?/ R, h+ o
1268299 PSPICE STABILITY Pspice crash on attached design
4 ?' L5 v+ x2 G* R4 v1270879 ALLEGRO_EDITOR COLOR Color view save creates .color file using older extension* P8 T) h( y) H1 a
1271295 SIP_LAYOUT DIE_STACK_EDITOR Die stack editor support needed for large variant combination designs.2 L' I. y5 n: I* x+ J1 p. _2 p9 \
1271385 CONCEPT_HDL CORE Locked property can still be added
5 \5 T p0 R3 _0 x7 Y1271853 APD OTHER When using the beta "shape to cline" command, add improved messages and partial completion of individual segs in error.# _: R! i' g% Z; c0 w* K# l
1272197 CONCEPT_HDL CORE concepthdl_menu.txt contains invalid Variants menu
) ^+ g( f8 x J4 o; s& C7 d1272318 CAPTURE GEN_BOM BOM_IGNORE not working for Capture BOM on hierarchical designs." n* c& r& q6 Y/ ? T
1272743 ALLEGRO_EDITOR PADS_IN PADS Library Translator does not open the Options dialog window.
( K3 S J: q6 T1273517 F2B PACKAGERXL Netrev error - ERROR(40) Object not found in database
* N* F" L- M$ H& X; b1274000 ALLEGRO_EDITOR DATABASE PCB layer can't be removed. n4 d2 L9 W0 ?
1274530 ALLEGRO_EDITOR INTERACTIV Add Circle radius value changes next time using this command
- X: L" k* N, O6 k1274697 PSPICE AA_MC pspiceaa crashes when running Advanced analysis monte carlo for the attached design
$ T: p n1 c) @* q+ {1275154 CONCEPT_HDL CORE Hierarchical Blocks lose ref designators when moved to another page
0 l8 M, j/ F2 K* d1275724 GRE CORE AiDT delete another clines
+ G; r+ m. f' W1275831 ALLEGRO_EDITOR DRC_CONSTR Waived DRCs return when using multi-thread DRC check
$ Z3 T# ` M, Q3 T) w1275834 CONCEPT_HDL CORE ERROR (SPCOCD-569) on global bus
- ]1 f* d" u+ } {" V @) d$ k1276334 ALLEGRO_EDITOR PADS_IN PADS Library Import problem with outlines$ y* ?3 ?! S" }+ O
1277062 ALLEGRO_EDITOR PLACEMENT Swapping parts from top to bottom Orientation changes
: L5 N7 V/ A( n. B7 t1 W0 Z1278746 ALLEGRO_EDITOR DRC_CONSTR Package to package DRC allows place_bound_top in 0 spacing has drc in 16.6 version.
& |. u! i, R6 o2 {3 E2 |1278804 CONCEPT_HDL COPY_PROJECT Copy project crashes
8 t3 N9 i9 J/ P* ^, _0 o1279362 ALLEGRO_EDITOR INTERACTIV User skill file makes Allegro Icons gone away
3 k0 i/ \; W) T& c1279619 ALLEGRO_EDITOR DRC_CONSTR Netgroup in a Netclass doesn't inherit Spacing Cset
; K: A' G* d$ c( G/ w' S2 I; Q1279815 CONCEPT_HDL CORE Text > Change and RMB Editor does not allow multiple text edits
u" [& j$ e; L* V) ]9 u3 y1279876 ALLEGRO_EDITOR DATABASE Using the Curved option in Fillets results in a pad to shape DRC) n; J: P9 `* m* l; T7 j
1280435 F2B BOM BOMHDL with variant repeats the PART_NUMBER value
. V$ z0 q. C8 _) }1281669 CONCEPT_HDL COMP_BROWSER Match Any radio button in Component Browser didn't work.
' [2 ~ P! N$ s7 {3 J% Q+ C8 D7 |1282001 ALLEGRO_EDITOR DRC_CONSTR Updating the DRCs on this design cause the DRC count to change on every update& r& o" g3 E; M
1282480 SIP_LAYOUT WIREBOND Info on the Wire Count property needs to be updated indicating that it is a User Defined Property
+ p- E9 m8 q( G" E" a" p7 l1283952 ALLEGRO_EDITOR PLOTTING Published pdf does not show dotted or phantom lines- l& V" P: |/ M5 w8 c
1283957 ALLEGRO_EDITOR INTERACTIV Replace padstack in "Single Via Replace Mode" is changing netname of the vias with the latest hotfix of Allegro 16.6- I2 i' D$ L1 S ~6 R& O' l
1285588 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase control has wrong analysis result when add rectangle test bead in Clines.( _7 p1 w. ]2 l# l9 h8 E% }
1286743 ALLEGRO_EDITOR SHAPE Getting copper islands in the design after running the Delete Plating Bar command) d3 Y2 |8 y' D8 V2 Z5 ~
1287215 ALLEGRO_VIEWER OTHER Allegro viewer plus does not support constraint regions2 _7 }& ~& m4 H1 c: g6 S) z
1288808 APD LOGIC Derive Assignment stalls out or won?t finish and appears to run out of database room.
; r2 l& m1 D5 T# q1289251 ALLEGRO_EDITOR SCHEM_FTB Pin escapes (clines and vias) not inheriting new net name from a pin with a new net name.
- K% U* I. S7 m3 O7 a1 A" h1289293 F2B DESIGNVARI Warning 04: Cannot merge the variant properties on variant instance C119 component with same canonical path not present. `6 U5 Z& I, f) f* p
1289809 SCM VERILOG_IMPORT User not able to import a verilog netlist into SCM
g X! ~' y4 l( w6 A. ~2 d. f1290696 CONCEPT_HDL CORE Copying a net name repeatedly causes it to go off grid
+ Y. l7 E& R' {1291162 CONCEPT_HDL CREFER crefer crashes when selecting generate cross refernece for all nets selected
. \' {6 c6 q4 \ g5 A n1291285 SIP_LAYOUT IMPORT_DATA Replacing a Die with the Die Text in Wizard causes some Clines to Shift, creating new DRCs.
1 q6 M. p: J4 c. [1291658 ALLEGRO_EDITOR INTERACTIV Cannot add Frectangle to Group
3 y/ P$ F) Q0 z N/ K, }% W1292180 ALLEGRO_EDITOR SKILL Allegro Crash while performing query contents of "Maximum_Cavity_Size" with the skill command 'axlDBGetPropDictEntry'' U- a* d5 x+ t( Y# T
1292210 CONCEPT_HDL CORE DEHDL crash if design was opened with -nonetlistuprev option.6 Q" O( P5 b+ i r3 w
1292278 SIP_LAYOUT WIREBOND When creating Wirebonds by Importing a Wirebond File, (wbt) the wirebonds are not on the correct Die layer: t, H! E- H! G! a
1292282 SIP_LAYOUT INTERACTIVE Getting Multiple GUIs when the Wirebond Import is open and we select outside the command GUI.& p/ r; x1 V* K% j0 q7 P
1293381 SIP_LAYOUT IMPORT_DATA Import SPD2 error0 t8 }9 T9 H9 _$ R: ^# h" O- D" L
1293889 CONCEPT_HDL PAGE_MGMT page name regression result deleted by netassembler
/ E H! M3 S+ L* f# x5 C! T7 ]1294124 ALLEGRO_EDITOR INTERACTIV Samsung Mobile division wants to disappear the grids in the display window when zoom-out function executes in the allegr
4 b5 K! H+ S4 k9 E' K1294749 ALLEGRO_EDITOR ARTWORK Null pad is flagged as an error that break Thales automatic tape out
, X; R2 \* U; d7 u1294777 ALLEGRO_EDITOR SYMBOL Mechanical symbols missed on STEP result
5 [8 z1 O! h! k4 d' x: T) o- c
: M v2 u: x6 n% u% @DATE: 06-20-2014 HOTFIX VERSION: 031
0 O3 M; m: i4 u; l8 l===================================================================================================================================: ], x$ w: c4 q, y
CCRID PRODUCT PRODUCTLEVEL2 TITLE6 ^9 R# Q3 {& v# B
===================================================================================================================================- X2 e& e3 E2 I; S5 g1 H, e
726553 FSP CAPTURE_SCHEMATI Method to select bus bit?s order while generating Capture design from FSP.
# `- x. O8 V) w) @& @0 P% [1257631 FSP DE-HDL_SCHEMATIC Schematic Generation selects incorrect symbol version8 F$ h0 e. V' B, l' f" I
1273456 ALLEGRO_EDITOR PLACEMENT Place module instance causes Allegro to crash# ~& M0 t+ m# ]/ b! t9 O
1277099 ALLEGRO_EDITOR INTERACTIV Clines and pins are disconnected even though they are at the same x, y coordinate.' i/ }/ S; ~% M
1280913 ALLEGRO_EDITOR EDIT_ETCH Add Connect should be able to be made by go straight even though the cursor is not exist on straight line( @7 v3 ?. ^0 I1 a) P
1282491 ADW PURGE ADW PURGE is removing Page Name data in DEHDL7 {8 }0 V( H! N z/ f9 p
1283045 ALLEGRO_EDITOR DATABASE Ecset not getting downreved.4 n0 K# S* Y$ x. k
1283138 SIP_LAYOUT IC_IO_EDITING symed app mode chooses wrong text block sizes for I/O driver inst names7 i6 }+ u& m+ j
1283227 PDN_ANALYSIS PCB_STATICIRDROP Enhancement request to add 32 bit files for IRdrop+ _; j2 i0 L5 h* U" W
1284656 CONCEPT_HDL CREFER Crefer fails on large design
5 e0 y8 n# Y$ w% w8 Q+ r4 U2 M* F9 d1285814 CONCEPT_HDL CORE DEHDL crash on opening the Design( U6 f5 L F: y, C5 R
1285967 ALLEGRO_EDITOR EDIT_ETCH Slide via in circle pad
% X3 }2 k2 k7 m5 l2 U" k: V- m, T; v M. J2 N7 M, J% x) z
DATE: 06-12-2014 HOTFIX VERSION: 030' ^, K7 h( l8 N" q
===================================================================================================================================' U( y9 _( e5 Q, J& ?# g/ y
CCRID PRODUCT PRODUCTLEVEL2 TITLE
0 _6 K2 x+ i7 V; w===================================================================================================================================! R5 e' Q/ W( @0 ]) d9 B* E* b
982961 ALLEGRO_EDITOR PLACEMENT Show the Rats when one selects physical symbols to place them
4 S4 m' N/ j! L6 s" y* n1138680 FSP POWER_MAPPING Ability to assign decoupling capacitors in spreadsheet like application
7 o. M) h2 L4 `) V2 T1243410 SIG_EXPLORER EXTRACTTOP Circuit topology extract failed in case of CLASS, H7 n* I) Y. u2 I/ Q9 E9 d& Q
1262977 ALLEGRO_EDITOR TECHFILE When importing a certain tech file into an empty .brd Allegro crashes. ]- n8 {. B+ k, C
1267558 ALLEGRO_EDITOR INTERFACES Arc part of symbol pin missing in 3D view of step model6 f \2 ?' e; G3 x
1268252 ALLEGRO_EDITOR GRAPHICS step place bound issue(3D View)
# {4 V7 ]7 T8 L' ~' [; y: h3 }( @1270450 ALLEGRO_EDITOR INTERACTIV footprint add line on line crash4 p( B# t* @" {. x) m" N
1270962 CONCEPT_HDL PDF PDF Publisher command line does not print pdf file if double back slash is present
2 c3 A3 k% D% G3 q5 O9 A$ p1270964 ALLEGRO_EDITOR mentor Mentor translation crashes with no errors in log file
. }$ B/ ]8 W, T1 ?( ]* z, h( Q1270999 MODEL_INTEGRIT TRANSLATION ibis2signoise Issue9 t9 ~8 V& ?( ], L6 Y. P. s" h
1271543 ALLEGRO_EDITOR PAD_EDITOR Library import reporting missing padstacks
. N b U# y: Z& d0 d1 }1272099 ALLEGRO_EDITOR GRAPHICS Plotting does not fill shapes
3 m. c* m0 w5 Y1272406 ALLEGRO_EDITOR DRC_TIMING_CHK SKILL command 'axlDBTextBlockFindName' returns 1 when nil is expected5 k6 n! F! D( Z2 m2 C$ _
1272748 ALLEGRO_EDITOR GRAPHICS 3D viewer crashes on this specific testcase% p+ z, k; v" K
1272793 ALLEGRO_EDITOR GRAPHICS 3D view doesnot displays hole with offset correctly
6 ~0 T* V) i3 _1 Z8 j" M1272863 ALLEGRO_EDITOR INTERFACES Ability to find the origin of STEP File in order to place it exactly where it needs to be on footprint during mapping.
2 ^" {7 l# x3 ?7 P- J& u1273264 ADW COMPONENT_BROWSE hyperlinks not recognized in the component browser4 s* `& w6 D7 B1 y: I: j! W
1273304 CONCEPT_HDL PDF Publish PDF from commandline does not work if there are spaces in the Path2 K. _ ?( `! [7 p1 L
1274661 CONCEPT_HDL CORE I can't copy a property from one component to another# w( n( q6 [" j. j$ b4 h7 ~
1275237 ALLEGRO_EDITOR DATABASE Allegro Crash on running DBDOCTOR for a board5 [( h. I7 X" G+ w
1275345 CONCEPT_HDL CREFER The Xref information page number values are incorrect' J _8 a/ `+ B+ E+ ^) }) ]# [
1275748 APD IMPORT_DATA WireBond starts away from the Die Pin after importing Die using Die Text In Wizard
7 @* K9 h) R+ c5 j B$ R- R1276270 CONCEPT_HDL CORE DEHDL crash by Zoom In > Ctrl+A > Move4 o$ ~" n9 Z9 ?$ H, Z
1277735 SIP_LAYOUT IMPORT_DATA sip layout spd2 translator issues with offset die and mirroring( f! |8 f9 @2 t" v2 { B
1279258 CONSTRAINT_MGR OTHER Import logic stops with error/ d- X" E B( Q5 u! z4 G
1279694 ALLEGRO_EDITOR SKILL axlCNSSpacingMin('via nil) crashes Allegro PCB Editor0 w% A+ e$ Y! i5 X2 j4 _
/ Z/ w" f3 j' B& q5 PDATE: 05-23-2014 HOTFIX VERSION: 029( i; y) s5 A$ k6 l9 X
===================================================================================================================================
) G; ?3 w4 N K$ f; ]! [+ h3 [CCRID PRODUCT PRODUCTLEVEL2 TITLE
3 f: M4 _ s$ R' n) G===================================================================================================================================( T) Q2 |5 ]& }' A$ |% |6 Q5 H
1209461 FSP DE-HDL_SCHEMATIC Hierarchical Block Size not automatically adjusting to text needs; j7 n2 r: m7 H
1217832 SIG_EXPLORER SIMULATION S-param generated by SigXP doesn't match with HSPICE/ADS.
6 l. R) C% ]1 ^3 m7 b. T1263575 CONCEPT_HDL CORE Copy-Pate makes Components Off-Grid$ U& ?# H9 ?) a
1267602 SPIF OTHER Route Automatic hangs
( N0 Z; q! ?* _0 @( Y: B6 Z1268022 FSP PROCESS FSP is not respecting the use banks for attached design.0 y9 f" _- l9 Q& ^$ ?
1268587 ALLEGRO_EDITOR INTERFACES Enh. Preserve relation between hole and padstack in IPC-2581
" {& D' J3 R0 Q9 I1268918 SIP_LAYOUT DIE_ABSTRACT_IF SiP - DIE export from co-design object to XDA results in missing data6 v3 M9 N) p4 ~
1269232 CONCEPT_HDL INFRA While pspice uprev the design crashes" N. b' `3 H5 r; l9 j
1269825 SIG_INTEGRITY SIGNOISE PCB SI hangs when running crosstalk simulations
% J) ?/ Z8 @; C1 t; V7 O1270963 ALLEGRO_EDITOR GRAPHICS Add Circle lint font hidden/Phantom has resolution problem7 n0 f6 R8 V# O2 I m
1270990 ALLEGRO_EDITOR GRAPHICS Allegro response is slow when added circle
) G7 G4 U/ x7 x1 A/ {1271655 ALLEGRO_EDITOR MANUFACT Dimension option causes a generic crash, reproducible in any design
. c, j( N- n" h9 f. }1272495 ALLEGRO_EDITOR MANUFACT Filtered Part numbers in IPC-2581 still pass actual part number for references onutide of BOMItem+ s; L$ g6 \: W- A
1272839 ALLEGRO_EDITOR MANUFACT Kindly explain the drill legend behavior when padstack rotation is 45 degrees and mirrored ?
/ k, q! F3 z7 [4 |4 X1274518 ALLEGRO_EDITOR ARTWORK Artwork does not create void correctly.
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DATE: 05-10-2014 HOTFIX VERSION: 028) I5 V: e/ X$ Y1 r& p
===================================================================================================================================
7 s- v- \% k# ]5 K0 @1 N0 iCCRID PRODUCT PRODUCTLEVEL2 TITLE. S \' L5 i, g4 \/ J
===================================================================================================================================/ X; P9 t: m5 g( m2 Q6 Z
1199256 ALLEGRO_EDITOR INTERACTIV DFA bubble does not appear when moving a symbol to within another symbols dfa bounds on specific symbols
+ l$ q' A Q* S8 `1220196 ALLEGRO_EDITOR OTHER create xsection chart results in ERROR(SPMHA1-73): Text line is outside of the extents.
8 P7 |1 r. G/ M" Q. }' X1259520 ALLEGRO_EDITOR EDIT_ETCH Allegro will crash when adding connections to a differential pair.
' u( I, |) b3 S- G( N' \2 m1260446 ALLEGRO_EDITOR VALOR Creating odb output the xhatch shapes where arcs are will become inverted. Difference in the geoms.out extraction?6 S/ H* [: {0 k7 Q) M
1261313 ALLEGRO_EDITOR INTERFACES Step mapping does not show all Available Packages. f+ T5 ^ A- d+ P
1261356 CONCEPT_HDL CREFER crefer is crashing with generate for all nets option) k$ F( y! @, A S- l8 a
1261514 ALLEGRO_EDITOR ARTWORK Exporting raster artwork with overlaping voids fails.
- L! I% v* ^2 k1261735 ALLEGRO_EDITOR ARTWORK Presence of Smaller shapes inside bigger shapes is crashing artwork generation.
' _8 e# C# G7 Z( W$ K8 k1262019 ALLEGRO_EDITOR INTERFACES Artwork control form hangs if we close PDF publisher gui
) g, ]" l2 A- o/ t4 e- [1262246 CONSTRAINT_MGR ANALYSIS Constraint manager shows ALL PASS when Adding members to a NetClass and adding parallelism rule1 T" b) B9 f4 B) L. P' S' ^) ? X+ [5 o
1262560 APD WIREBOND bondwire can't connect to GND ring directly
, M6 D1 K* }1 v5 r; d3 ?& B# @. U1263275 CONSTRAINT_MGR OTHER Import of constraint file hangs in this design
8 a( _1 P0 r; R6 D) u0 M" C1263358 SIP_LAYOUT OTHER SiP Layout - Void adjacent Layer enhancement to merge voiding for PADS without changing shape params
/ J6 Z1 g: v% R8 R: r' ?1264109 ADW LRM LRM error - WARNING(SPDWREV-7): Unable to read the design
# @$ O, d( b( Y, @4 \, \7 C1265580 APD MANUFACTURING Icp_soldermask_allow_pins cannot create correct solder mask when the pin rotate.
* q( w6 I5 K) h0 l: k% y1266391 APD LOGIC SPB16.6 Derive assignment : want to select 1 DRC marker only.
2 r% D0 v' I7 j0 }# m/ E6 D1266687 ALLEGRO_EDITOR SKILL The SKILL p* J( q% K1 b& A1 J; T. U; d; [
1267267 SIP_LAYOUT WIZARDS Attempting to create a die using the die text in wizard but the tool is not creating the correct die outline! {* G6 @8 J( N+ k; m" g; [) u3 n7 d
1267308 SIP_LAYOUT OTHER When updating a BGA with the Symbol Spreadsheet tool it will start, update a few pins then stop.
8 ~) d% w3 I: Z1267639 ALLEGRO_EDITOR PARTITION Allegro crashes when partition is created and opened from a location that contains "!" in its path.* ~* [" C% V+ Q+ H0 Y# k
1267704 SIP_LAYOUT STREAM_IF Cannot import stream file, the tool starts scanning the file and never stops.
0 A" v. q% o G- A1267907 CONCEPT_HDL CORE Ctrl+RMB Context Menu Option doesn't work.
) i- b8 Q0 q; d6 N5 ^/ h$ n
/ \8 @: x) g0 C& i$ bDATE: 04-25-2014 HOTFIX VERSION: 027
. T7 y7 E+ h5 P X; u9 K# a6 o4 a4 d===================================================================================================================================8 A6 J6 b7 w9 f
CCRID PRODUCT PRODUCTLEVEL2 TITLE: W# X8 }9 I! W/ t8 r
===================================================================================================================================1 D Y' T; R# h. J
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM0 n9 \2 P% N- Y; V- t( v, e
481674 ALLEGRO_EDITOR PADS_IN No board file saved from PADS_in- O9 {# x; }1 }7 N5 v+ A1 f
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
6 g7 O' G( Q: T3 ~( O$ A3 q1012783 FSP OTHER Need Undo Command in FSP
$ R! D0 d% h( J6 }: |1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.
& x7 ^ j; F: e9 s- F: q" c1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
8 j- q" G% W9 \( O6 Z3 f/ K1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.! Q) L4 Y+ ~- v3 V M
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups+ I3 X' X' d+ P" w$ B
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash- {0 ?5 f& }5 L3 ]
1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
* f( w. k( N K/ Y1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
( S% `6 o0 i9 J1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present; P. Y/ Y8 e6 |0 i. ?
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list. _! W) D4 q- E% @( j; ]0 G
1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings2 I# w$ B( ?" l: G
1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.; E1 Y; y/ _5 `/ W: B
1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
7 m" E- c* e& w0 i8 S8 b1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
$ _! H$ d$ U* N1 f. U% r2 `) l5 Z1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
: x; @! H. i$ R4 A: r' s& b1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime2 \' U/ t. O# R
1208478 PSPICE PROBE Attached project gives overflow error with marching ON.
; O2 o5 U o8 u8 Y/ y' N1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol# [( h' d, F. g* i' I. ~. q( ]
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
) I4 ?% n" L! e: I1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
- E2 _2 p' i/ z l3 F S3 V2 b1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers3 f- x5 b( y2 Q4 a
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?
% N2 t( K. c% A2 e: Y1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.
" R( g. z+ E; Q$ T' V$ b# o1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values
! a- {. }6 i1 w9 M% n+ B P, f8 f' F1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging
: V4 W" ~. T: P' ~1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
3 h" }0 d1 [0 Z7 l; D- i7 O1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added0 T8 y+ I9 n' t$ K+ s: d% G
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
0 E1 @0 F4 O8 m# P5 p1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes4 |2 J- |. k. ]5 |0 k4 S: z
1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux) c' ^! I# V& g* |. [4 q+ B0 G' G
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
6 K+ X* V: r) g) v1221182 ADW TDA Team Design with SAMBA
' A, t* u; z% f- [) E4 o9 Q1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
. V; Q4 m/ o9 U/ c0 U7 S) m1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
a8 |7 c+ _4 _: `) o1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol? Z5 y- q) C4 B0 c Q
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts8 r2 ^* H# U4 a+ ], l5 g
1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms! p6 D- l* s5 I/ D6 U* \
1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.) ^6 X3 ?% M9 c; o% x$ f1 ^
1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor& ]0 A0 \' U: u0 z8 V4 \- j. n2 Y" Z
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.9 n9 `; D) }( T3 ~1 o
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
% C" `4 x+ C% q* J1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin E9 R- S% `" e
1225494 CAPTURE DRC Different DRC results for Entire design and selection" Z/ c4 q, [' `5 u# L
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property
. K9 \1 ]: D$ M r5 W1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
+ Z$ ^0 z- m! ^! v$ ^+ n# ?1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet; s! D2 I5 {0 c* s. I4 Y
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts� function is inconvenient for Global Signal, ^/ ^$ {# d& w* n5 c! P
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
1 r3 c+ k& h1 z u1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors3 U& h# q( g6 Z8 k% T' v j# J5 O' z
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
# a3 M1 C) n% F: u4 I1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration* ^, V9 P/ }& o2 J+ M! ?5 c
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part O3 f( p- Q" p" |
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case4 g' D/ j2 P4 c# h
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins
+ G) z% _% Z; b1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection4 L/ U4 r$ E) K; {
1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time." E: [7 h1 H1 z% [2 q, m5 ^3 d; ~
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
. J) d' ~- ^* t% m2 W& N2 u* T1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
4 @' D) V: K' }/ j5 U& O0 [# s1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM U; H( t: l8 l: O
1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
4 P( V) [) r- q7 [( I1230432 CONCEPT_HDL CORE No Description information in BOM- D- B+ c4 b, H C) H: x3 O
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes+ x& j6 y' t7 v) s7 b; Y
1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files
4 k8 r6 ]3 i2 P+ e: ^% r# u8 ?1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
7 D2 h! p: O% b. m3 ^ F3 b7 L" C1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets
+ T5 M- b! j( R& s4 \$ f1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
, A1 G) h( }; ]+ ~1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode
( I8 `3 l/ {" ^1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical% e# ^. A0 C" s) c' a, y; j$ j
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode
2 _7 U: @: Y- {' J1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files
1 i2 R2 d9 Q" u2 Y7 m1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy
- V$ G! O$ Z h) b5 h$ `1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
6 a. Y4 J, x5 V6 _& S! y1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect
. i( H' u; m( G- c% s) p1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
& ^" p( C' O& a$ `" \" \1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
8 D; X9 K" \5 o# @$ G" H1236161 CONCEPT_HDL CORE Import Design shows the current project pages
, j! `/ a6 e0 c4 j( L- ^6 C% _4 y; _1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.
8 f" z$ ?% J( r9 @5 D- h1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion9 Z" C! r t7 w2 T6 Z2 C
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file8 G% r3 r/ q. p( b- K
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape6 P3 S2 f) K- [% r! H5 P
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming1 v0 e8 M8 P Y) N1 ^
1236781 F2B PACKAGERXL Export Physical produces empty files! S$ Q4 k" \* E6 B& R" Y
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
& `3 g- P/ N4 \( r1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib� command6 F# x4 B8 p7 i
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
3 b: f& c, q+ h1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
# d7 W% O" D7 X0 i& H- c/ D1238852 CAPTURE GENERAL signal list not updated for buses* G: P1 a# b/ ~
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes; X8 F0 G) S+ p
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
# ?# j9 }! e/ k9 C3 c' G1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE
- l: B0 m: c4 N) Z: Z% @; T1239763 PSPICE PROBE Cannot modify text label if right y axis is active v4 m7 B! q3 t) O1 E, f
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images
9 y. u, Y7 ^ W( L' G1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
( a8 P) d. v8 }# e1 w5 o1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing1 u9 P K1 _- `8 D( E- s
1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file0 N+ g" B' x; Q% O0 P: Z: u
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable
5 S5 E) k8 ^- K- b" U4 S0 I% V) A+ L1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy2 E. ~; ~: [ Q4 U
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms+ Q, S' a- x+ O. R) K5 r
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working
9 g" A: B. ~( @: F& N G! Y; x1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.2 @/ N! q( d6 h$ X
1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard" b! d' V: n+ _% N2 L& R
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning! M% c, Q5 P- f
1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side5 n' e" n2 P& Q
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer( Y. a5 N1 Z$ Y! K, w$ g
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results7 E- i$ q, I4 s; O1 @
1243609 CONCEPT_HDL CORE autoprop for occurrence properties3 D: b+ g1 e. B3 G+ C9 n
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
& j5 _0 ]9 T0 ]8 `; y) N( C1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
% M$ E# [# v1 G. q8 T# C1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
- O! U3 K3 G7 m1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
3 Y2 x% s1 `2 ]& M. T7 P1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
1 B/ {6 I: L# C* v* X# r/ A1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design/ G1 R% A( X& |% W# n# @
1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?" i9 \8 w" G1 \9 s) g
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
+ t6 F1 V) b# S3 d7 I$ a) @! X; t1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters$ d+ c6 D6 y! Q% ?1 h b' h1 d
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
; c' Y) I' j1 y5 E1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
# ~1 ?" C% E x! T1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL( @) Y! K9 }- Y8 z3 y
1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained
/ C' R' A1 s+ B) J" R1247462 CONCEPT_HDL CORE Text issue while moving with bounding box
; }+ N& ?% W" ~1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered
r, W1 a# s- h+ h+ V, O1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
2 u! g7 ^& q' t$ ^. @: T' C5 V0 V1 G1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts
* q J' k+ l p, u3 W1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
4 i6 H" y3 Q' ^9 r- f, \1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
6 D$ L) B0 N* d# U# {, x1 }1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly
# k% \+ q' U: [1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.7 O* e2 \, f/ u4 S+ h
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies0 A' z2 k* p! X( @- ^) }: O! J; j y
1253424 SCM SCHGEN Export Schematics Crashes System Architect; m: ? s0 W3 I: a/ X7 F& h; r
1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled9 k8 |1 r0 b# W. O# ]% M7 q
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
% R( U$ k, k ~! n6 m) T1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router) h7 T0 Z( Z" V0 { z- ~) p
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error
. @. r- v T. }5 B: t1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
& M( a2 S0 D: d, a1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation
# f9 f+ ^' J$ W& Y* q1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects7 S( t: \6 r- i% j2 J0 v
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode1 F3 n7 t5 j/ L+ a9 ^$ ~
1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
0 v9 M7 ?! H9 v8 D7 y" p3 s Q* S1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE, e/ b$ `+ e: q: @$ R& _
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
, t4 H f5 L0 F. [$ D# ]2 o$ D2 j1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design! C9 J( v1 j4 o# H- g3 c
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library& y. `- h& ~' l% H/ c+ ~1 J
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
; X. [+ N' A" ]8 r- q1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash+ k. F6 c* o# L
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
( z0 I2 O0 Z% R- Z H+ x1258029 APD WIREBOND The bondwire lost after import the wire information b! o% H2 g) c- L7 q& ~
1258979 APD NC NC Drill: There is difference of number of drills.
) ^3 P8 V5 L; D6 P- ~+ t1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement/ ]9 |) Z0 h- W d5 h: p, E5 V0 Y
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.9 n4 J9 J; w& `5 M4 ^
1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"
, @9 r' [3 I5 l8 U* h1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines: h: ~: }4 L. p3 h5 U B
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void+ b; J6 S) F S8 T5 e- O( @- X
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss |. \# i$ s1 t
) M1 M+ O+ O" [! W/ i: c1 n- u. \ S7 wDATE: 03-28-2014 HOTFIX VERSION: 026
+ E( j" \& Y9 c2 }' z- x5 [===================================================================================================================================
2 A3 a: u$ c) [' y9 R3 L9 Y+ o' TCCRID PRODUCT PRODUCTLEVEL2 TITLE- Q* p5 k! g5 l1 A& }
===================================================================================================================================
" J2 G! f& J( M& n, f+ Z1190942 CONCEPT_HDL CORE Cannot copy locked .xcon files) S3 D# X: _# E0 q5 `& T! Y
1226085 F2B PACKAGERXL Winning net NC shorted with loosing net due to PACK_SHORT. z7 ^3 _4 K$ r0 v6 i9 L; v/ p) C
1244894 SCM SYSTEM_OBJECT Get packaging error when adding a pullup/pulldown resistor' w& F: `) ~0 Y1 D# k
1247432 CONSTRAINT_MGR OTHER PCB Editor crash$ J1 r+ a1 g' z: }9 M; S
1248560 F2B DESIGNVARI Variant Editor > Help about for S024 says unreleased ?
$ G+ U: v7 P2 J# G" W& o0 {1248712 SIP_LAYOUT WIREBOND Changing the charecteristics of a Bond Finger causes it to shift position6 d( B$ P F) b5 G" U6 x" n2 {
1248839 ALLEGRO_EDITOR OTHER 16.6 S023/024 crashes on Logic Change Parts command.$ f. g$ T: \7 M# w6 p* a! T- \) k1 u
1249000 SIP_LAYOUT DIE_EDITOR unexpected shift of instances/pins by co-design die editor
0 w1 j8 B* u: I; B2 W, q1249186 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 ignores property UNUSED_PADS_IGNORE
0 Y# Y- k! E* S; Q8 j$ _1249272 SIP_LAYOUT IMPORT_DATA film resistor pins/pads are created on the wrong layer. Always synthesized on top cond layer regardless of config file0 i, I" a1 n* ^2 t" J
1249792 ALLEGRO_EDITOR INTERACTIV Cannot place rectangular shape as per included width and height.: O! e) D; F P- q4 \6 r2 T$ X
1249801 ALLEGRO_EDITOR INTERFACES Bug - Arcs in IPC2581 export are corrupted
) f* N+ H1 O9 k" K5 ]# @4 ~! R1251006 ALLEGRO_EDITOR INTERFACES IDX does not recognize PKG_PIN_ONE property- e3 S3 S2 w: v' B
1252142 ALLEGRO_EDITOR INTERFACES Remove inappropriate Conductivity specs from the dielectric layers from the IPC-2581 output
+ [( S1 U+ V% F( G3 C% V( w1253047 ALLEGRO_EDITOR SCRIPTS Bug: SAV file when creating symbol
5 [; l; D- h1 J+ B1 v* H: U5 k* g, @% @* B
DATE: 03-13-2014 HOTFIX VERSION: 025+ ?$ u7 C# U) i, {% Y
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CCRID PRODUCT PRODUCTLEVEL2 TITLE9 n1 q& a& _9 O/ n" v$ M1 G) A
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, Y4 W B d5 M5 E& r) u6 i1194646 CONCEPT_HDL GLOBALCHANGE Global Update > Global Component Change does not work' K/ ?* H6 a6 P' J. c2 N! L
1227843 SIG_EXPLORER EXTRACTTOP Cannot extract the topology correctly.& i8 g7 Q& i8 c' d3 H
1231510 ALLEGRO_EDITOR INTERFACES IDX exchanges with CREO 5.0 issues6 T1 p1 O) a& C' h8 M
1233030 SIG_INTEGRITY GEOMETRY_EXTRACT Net Parasitic of ground Connection3 O/ n, ?5 w8 o! m. T9 X
1236961 SIP_LAYOUT OTHER Moving component using Place Manual -H causes mirror_geometry.2 S9 ?, ?7 ?3 @) N9 A
1241456 ALLEGRO_EDITOR EDIT_ETCH When creating Die pins or changing their attributes an oval is placed on the pin: |( m9 ]: G8 n
1242461 SIP_LAYOUT OTHER SiP Layout - DIE is being mirrored when placing
- D. `& X* k1 y1 b" L1242682 CONCEPT_HDL PDF PDF Pubisher crash DEHDL on design7 c7 F Y3 j5 Z# Z- |1 n Z
1242685 SIG_INTEGRITY SIGNOISE Incorrect net name was displayed/output if the net include consecutive underscore. \% o5 O$ ]) I; `& w. ^
1243357 ALLEGRO_EDITOR INTERFACES Ability to add any new name, S5 c3 D( K9 V1 j4 |" Z$ ^
1243758 ADW COMPONENT_BROWSE I don't see an option to switch between database and cache mode
. d4 W2 L& p! Q- s5 b3 b& C1244325 ALLEGRO_EDITOR INTERFACES Merge all the BOMItems with same part number into one single entry in IPC2581B.
) O, w" L1 r3 `# R1245363 CONCEPT_HDL CORE Design Entry HDL program crashes upon save9 E3 n1 V$ c% L, F. a5 ?1 J
1245790 ALLEGRO_EDITOR PADS_IN Bug: PADS Translation with 16.6s023 gives parse error
7 F+ u, @5 H, }' `' D. y1246343 ALLEGRO_EDITOR SKILL axlAirGap command is broken in s022
1 N9 k/ `, c& W% y1246419 CONSTRAINT_MGR OTHER Netrev fails with SPMHGE-268 on existing design
1 q. E# M# R* _# c: p$ J1246878 CONCEPT_HDL CORE Changing Symbol in Variant Editor makes schematic page crash
$ b) a/ F: f) H1246884 ALLEGRO_EDITOR GRAPHICS Infinite cursor disappears from the canvas after step package mapping GUI is closed.* m9 ^0 {! W4 X5 |6 y
1247016 ALLEGRO_EDITOR INTERFACES STEP Model of connector cannot be zoomed sufficiently after mapping it to symbol dra file./ v3 ?. ~* _7 o
1247107 ALLEGRO_EDITOR INTERFACES Incorrect Spelling in IPC-2581 EntryFillDesc field
: M7 a# ~2 F. w1 n' J% ^/ e* ?2 W1247177 SIP_LAYOUT WIREBOND Bondfingers not aligning to wire when tack point on the other wire end is moved from center
5 P! Y w+ a) X3 F% h1247400 ALLEGRO_EDITOR INTERFACES option to Export optimized PDF in color! R; y* Z. l6 \: A
2 @: r5 R& {8 _( e
DATE: 02-28-2014 HOTFIX VERSION: 024" i( {, u, I: z
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
6 A& b2 W+ D S===================================================================================================================================; S9 d2 t0 d7 D# }. E& u# S
1207753 CONCEPT_HDL OTHER The Variant Name with a dash is represented by #2d
9 r7 @% i0 l, E( x6 ?; U& r1234991 ADW TDA Team Design does not remove deleted page files from zip files5 A, z8 g( v# \6 f5 e
1235919 CONCEPT_HDL PDF DNI crosses are not printed on the correct components
: ^ d! t' p( A! A0 m1238007 ALLEGRO_EDITOR PARTITION Import partition removes properties from RKO that were on the exported partition. s. n# V+ {8 g- c* S3 d
1238140 CONCEPT_HDL CORE Design Entry HDL Crashing
/ ]" l7 A8 }" Z1 x1 Q+ o L$ Q- J' m1238195 ALLEGRO_EDITOR DATABASE Via's losing net idenity after being mofifed or replaced.
$ C4 C1 b- x3 x+ R! x1238478 ALLEGRO_EDITOR ARTWORK IPC-2581 negative artwork layers does not recognize shape bounding box value
9 O1 q; P6 E5 ^/ }$ N( E! g1238483 ALLEGRO_EDITOR ARTWORK IPC-2581 not drawing negative artwork correctly with traces in voids.
7 k7 x3 ]/ F. ]1 c" D9 d: Q. o z1239070 SIP_LAYOUT WIREBOND When importing wirebond data onto a Die rotated 90 degrees the WB data is placed in the wrong locations
1 }& i4 [; ]" i% P% A1239433 SIP_LAYOUT WIREBOND Need the Wirebonds to lock to the die aftter importing wirebond data
$ b, Q$ C& _4 u N0 x5 F1239952 ALLEGRO_EDITOR SYMBOL Allegro crashes with a component rotation of 45 or 135.2 k/ ^9 a' w, \. \3 h
1240205 SIP_LAYOUT DIE_EDITOR Crash occurs when trying to "oops" for a moved driver in co-design die editor in SiP/ e/ L& W% _) o$ [9 a
1240288 ALLEGRO_EDITOR INTERFACES Why are some of the mechanical holes not showing up in Step output of thi design, while others are ?! k# K* Z! ^* q( c+ g
1240305 ALLEGRO_EDITOR INTERFACES STEP Export gives some errors which are not documented
; r& }* J* X: s1240425 ALLEGRO_EDITOR DATABASE Export ODB is not working on 16.6 HF 22
, ]" b' Y1 [$ k- u1240879 ALLEGRO_EDITOR NC NC ROUTE file is not correct using hot fix 22 of v166
3 `" ~; {# J, E/ u" s1241904 ALLEGRO_EDITOR INTERFACES IDX baseline import displays false DRC with Package_height Offset until DRC update is run.) h" `- u; ?# ~3 c8 R) g
1242266 ALLEGRO_EDITOR INTERFACES IPC2581 crash on HF22 and HF23
/ K0 J0 |% l7 V% z& S1242433 ALLEGRO_EDITOR INTERFACES ipc-2581B incorrect LayerRef values in BOTTOM side RefDes elements' k* |& |$ N, n' Z( B5 K5 f% u
1242988 ALLEGRO_EDITOR SKILL Allegro crashes on skill command axlDesignFlip
. v" r, z- w( H$ Z9 X+ ^. H1243845 FSP FPGA_SUPPORT FSP design created in 16.6 s018 will not open in 16.6 s021
/ u) T4 M- L1 ~( g. ?. F/ a9 a6 R9 p) f- z& j- U5 i
DATE: 02-14-2014 HOTFIX VERSION: 023
/ y+ r1 r" U3 I7 U===================================================================================================================================
1 c6 c5 g0 m1 d; H0 F$ L! ACCRID PRODUCT PRODUCTLEVEL2 TITLE: ~" |* `9 L, b9 I( @) h
===================================================================================================================================: S: d& Q4 z) u9 a, Z- d
1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.% H, x- ~) d9 w& B3 O7 J
1202715 SPIF OTHER Objects loose module group attribute after Specctra8 N6 r6 H1 g$ ^, L% {
1203443 ADW LRM LRM takes a long time to launch for the first time5 z9 N3 |8 C$ H* V" O
1207204 CONCEPT_HDL CORE schematic tool crashed during save all8 ]: ]% t4 } r2 O! M7 H
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter$ d& y5 ~" [4 W$ q$ i: u( i2 Y6 U
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA1 o1 ?3 `+ N: u$ L
1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side% Y7 n& O: J% h0 y
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
: X* Y- V- ]0 M9 n8 b1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.
* H. t# B4 z9 c. j* ]* l: G, m# T3 a6 R1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
' r3 y% Q! l3 ^) p1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.* h5 N- E3 `5 w2 @% g
1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7! z3 _5 o" ^( Z: t' v( c6 Z
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's3 L; W6 @& F. k3 w
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.* q* Z7 ~; k2 ?0 k( I
1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes1 |0 m; f( U7 X {) y8 W( i& a
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form. K) W# y$ }" U. @4 j( q
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.1 m5 J' } O/ s9 D7 N4 i) H
1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
4 ?; x2 S3 ]; r6 f4 N) H" n! Y1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.: R# n1 L1 v/ H( K7 g! Y: X
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
7 ^) ^0 _3 {9 \1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol& U* N; N6 X* w: o- b* j
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
& ]- s: N" h! R* U) t- [( z2 B) ~" C1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File1 Q3 d' e& `5 z
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat0 q! V9 ^- M8 D0 Z# j
/ C+ D; E& E+ }; h; v: rDATE: 02-7-2014 HOTFIX VERSION: 0223 r F' W8 ^* j P0 H x; ?
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CCRID PRODUCT PRODUCTLEVEL2 TITLE" ~+ ^" H2 o) o7 {" i
===================================================================================================================================
3 K1 X; S' P `6 g0 ~192358 ALLEGRO_EDITOR PADS_IN Pad_in does not translate some copper shapes, W' s' h$ z' f" }: r8 B' p
222141 ALLEGRO_EDITOR PADS_IN PADS_IN: Extra shapes are created when importing PADS design' V% O. V2 ]7 i' B$ A' j4 J
274314 ALLEGRO_EDITOR PADS_IN PAD_in boundary defined for flooded area be translated DYN5 I! Z& I. Y) Z+ N# x' ^
413919 ALLEGRO_EDITOR PADS_IN pads_in cannot import width of refdes." l0 j! V4 m( E# _" p2 y- ?
609053 ALLEGRO_EDITOR PADS_IN "Mils to oversize" of "pads in" did not work correctly for MM data.8 ]! q+ H9 C) }7 q4 D
666214 CONCEPT_HDL OTHER Option to increase Line thickness in publishpdf utility
% z- f- r& X6 }4 T) b5 V4 W738482 ALLEGRO_EDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphics card
) Y2 B l+ f* z982950 CONCEPT_HDL OTHER change the mouse button for the stroke to have same function with in pcb editor, U) _: y Q' D) y' V
1020886 SIP_LAYOUT LEFDEF_IF a quicker way to promote die pins (by importing macro_pin list)# P4 ?0 P2 B6 E. ~6 q9 ?
1032678 CIS VIEW_DATABASE_PA View Database Part gives incorrect result in complex design with variants.8 a$ n' W, L9 s' b/ I
1033864 ALLEGRO_EDITOR PADS_IN pads_in doesnot translates teardrops present in design, Y: O) T' l( P* {* I: |9 c
1054862 CONCEPT_HDL OTHER Option to increase Line thickness in publishpdf utility
. u" I: ?2 P$ L+ a7 |1055252 FSP PROCESS Add a synthesis option to target a group to contiguous or consecutive banks
# f0 }- X1 j3 N- u q# O1100772 CONSTRAINT_MGR OTHER In Constraint Manager > DRC > Spacing the Show Element DRC totals are wrong.
5 g* Z w7 R- u) V7 y o, k1135020 CIS DESIGN_VARIANT Variant list is showing wrong results for hierarchical designs
& u* T: x* v3 b1138951 SIP_LAYOUT DIE_ABSTRACT_IF Fix die abstract r/w to properly support pinnumbers on ports* [ j# O! \8 l: J
1140042 CONSTRAINT_MGR OTHER Diff_Pair lengths and analysis are lost after closing and opening Constraint Manager.6 C/ O' H$ S: Q
1143662 ALLEGRO_EDITOR INTERACTIV Enhancement Request for RMB - Snap Pick to options increased to include Pin edge
, l* u: z7 ?' ~, `: a! P/ I1147961 PSPICE SIMULATOR Simulation produces no output data
; l. k9 q! x$ N/ a, o1150874 ALLEGRO_EDITOR PADS_IN Dimensions in PADS are not translated correctly during pads_in translation
! k! z6 X3 X6 v; w: u" m' l0 Y1154184 CONSTRAINT_MGR CONCEPT_HDL Difference in the way topology is extracted in 16.3 versus 16.6
2 a- s) M: d3 f- f" V8 X# h0 K1154770 CAPTURE PROPERTY_EDITOR Variant Name property doesn't show value in Variant View mode
( x& J) k* Q( l0 R1158350 CONCEPT_HDL CORE Need a warning Message while importing a 16.3 sub-design in a 16.6 Design: O% z9 u" f; V" J' L$ Z! I" @' j
1162347 ALLEGRO_EDITOR EDIT_ETCH Enh- Allow new option in Move command such that it allows stretching etch using only 45/90 degree segments directly5 ~( x! G6 p+ X$ m0 B" u' ] U) ?
1165553 ALLEGRO_EDITOR INTERACTIV Subclass list invoked from the status window does not represent correct colors.
, `, e# S- @3 b1168079 FSP MODEL_EDITOR Clicking OK or Save As in rules editor allows user to overwrite the master with no warning6 g7 M& s6 e5 A$ |/ ?
1172043 SCM OTHER : in pin name causes SCM to crash
3 M; \0 c. L C! Y8 m( _1172207 CAPTURE STABILITY Capture crash while adding new part from Spreadsheet
; r5 ^1 S5 G/ z, `( ]. p1172743 ADW TDA Allowed character set for the check-in comments is too limited# x6 E2 a0 ~4 {/ Y) v2 k8 s
1174099 SIP_LAYOUT WIREBOND Option to reconnect wire based on 縫in name� in the Wire Bond Replace
# }' q2 y, ^* @4 K3 a1177672 APD IMPORT_DATA Netlist-in wizard didn縯 provide detail information about what columns have been ignored by import process$ A5 q0 G P3 \
1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATION property can not be set to invisible, b* H, @& G+ W
1177820 CONSTRAINT_MGR INTERACTIV Done the Allegro command when attempting to launch CM
6 G& a" [* {3 |8 |( C) r! G1178586 ALLEGRO_EDITOR EDIT_SHAPE Number of digits displayed after the decimal point of Shape Creation function does not match the Accuracy of BRD- j- H8 {# o& x t& B7 w2 _
1179688 PSPICE STABILITY pspice crash for particular HOME variable vlaue6 ]: n) A& j- p/ H% i1 r8 k* g; C8 X5 j
1179827 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to Symbol export - enable field to add Keywords for data fields to excell cells7 T! @) A7 W7 w$ u# ]% }
1179879 SIP_LAYOUT STREAM_IF Data file corrupt when exporting Stream data from SiP database.
z$ M+ { U6 B$ x7 p: l4 S1180164 F2B BOM BOM csv data format converts to excel formats6 `; W8 x P i* \: x$ r( s K4 X
1180477 ALLEGRO_EDITOR INTERFACES IPC-356 output is listing a duplicate location in the comment section9 m2 x" D0 }3 v0 `/ s; L# q) w
1180932 SIP_LAYOUT OTHER SiP Layout - Symbol to Spreadsheet add option for writing to existing spreadsheet) R+ G) d3 L! J* D) C. _
1181377 ALLEGRO_EDITOR INTERACTIV Pick Releative does not work correctly with RMB-Move Vertex$ Y/ T8 c) B9 Z/ C- U# u' \
1181516 ALLEGRO_EDITOR DRC_CONSTR Getting a "Thru Pin to Route Keepout Spacing" when there should not be one.8 L: y9 a$ q% G1 J
1181739 GRE CORE Running Plan > Spatial crashes GRE7 p5 U7 O& _# Q/ r# J% Q
1181935 ALLEGRO_EDITOR DATABASE Enh. Property that allows internal C-C DRC errors
# M2 w- l' f3 x) X4 m0 @1182185 SIP_LAYOUT OTHER SiP Layout - Import symbol spreadsheet - suppress Family for the font in the XML spreadsheet7 @: {- n+ d$ T
1182566 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to symbol - Enhance ability of spreadsheet exchange to allow for a portion of a full pin map$ L: }- H/ I5 T9 p- Q
1182599 CONSTRAINT_MGR DATABASE CM Prop Delay Actuals do not update after Z Axis option is turned ON or OFF and Analyze is run.) p, g$ D) K4 V: ?8 Z- d. p: b3 d& J
1182892 CAPTURE SCHEMATIC_EDITOR Pspice marker rotation before placement+ v [8 \8 E% W$ x
1183682 ALLEGRO_EDITOR DRC_CONSTR Implement Nodrc_Sym_Pin_Soldermask & Nodrc_Sym_Pin_Pastemask to symbol level
8 O. @6 W5 V! E' b1185445 SIP_LAYOUT DIE_ABSTRACT_IF Die abstract export needs to be able to select xda file type when browsing
; Q; q. ?0 s2 ^- L5 H. ?* a4 ]1185932 ALLEGRO_EDITOR SHAPE Soldermask in solder mask void DRC, j; O# y# x# C( N0 F. b) p
1185946 CONCEPT_HDL CORE Ericsson perfomance testing report 5 sept 2013* m9 K5 A' v) j) V
1187213 FLOWS PROJMGR Unable to lock the directive: backannotate_forward
. s _8 u( m: d1 w$ \ Z2 I( f1187444 ALLEGRO_EDITOR DRC_CONSTR With this design Database check prompts error "SPMHGE-47: Error in call to batch DRC"
7 q# S! q# n" G, X1187597 ALLEGRO_EDITOR DRC_CONSTR No Package to Package Spacing DRC error, when symbol overlap sideways at 45 degree.1 Y! E% w$ j/ G( d- |- ?
1187723 FSP PROCESS Synthesis can fail depending on component placement: T# l6 l2 V$ p3 m/ M7 M( x# T. |
1188164 SIP_LAYOUT OTHER SiP Layout - Spreadsheet interfaces Import Export and Add Component - include Keyword for NET_GROUP& [5 g$ ~: {6 C
1188245 CONCEPT_HDL CORE INFO(SPCOCN-2055): You cannot run the CHANGE command in a read only schematic6 Q9 b, \* T; a3 A
1190927 CONCEPT_HDL CORE Check sheet does not report shorted signal/power nets if power symbol is connected to a pin9 E6 {/ I; Z6 j6 _" E, F+ @& `
1191497 ALLEGRO_EDITOR INTERACTIV ENH: Adding names to the text block parameters numbers- Y- s& q7 X% a2 K8 u6 q! g2 ~
1192005 SIP_LAYOUT IMPORT_DATA Import SPD2 is missing 1 smart metal shape from file' T. u# v1 _/ t" F' w! U
1192204 ALLEGRO_EDITOR EXTRACT Need ability to extract vias that are labeled as microvia
+ b5 F/ h; Y' g( v; r+ T2 C: u, Q1193063 ALLEGRO_EDITOR MANUFACT TestPrep log displays "Pin is not accessible from bottom". The component is through hole.
, d. O# R1 X7 |0 k1193418 ALLEGRO_EDITOR GRAPHICS 3D Viewer can`t export image in both SPB166S015 and SPB165S047
2 r; `0 C" ]* C1 j' p1194305 SIP_LAYOUT EXPORT_DATA export package overlay creates file with no package info; {# E; |4 ]) g( u6 S
1194418 APD IMPORT_DATA issue when do File->import->netlist-in wizard
# ~2 c6 Z' T/ B h& s1195279 F2B PACKAGERXL Ptf files are not being read when packaging with Cache8 j7 O1 W( H# e4 T! L
1195374 ALLEGRO_EDITOR INTERACTIV Modules are not showing up in Tools > Module reports, c& e6 ~0 ~" o! c V+ t
1196603 SIP_LAYOUT EXPORT_DATA Change form for "Write Package Overlay..." to better support longer lists of routing layers+ u$ q- V; t5 F' ]/ Q' C7 a
1197302 CONSTRAINT_MGR UI_FORMS Inconsistancy in selection of object for Spacing Constraint Worksheet9 a6 d7 Q: x# m) J$ Q' T2 B A* T
1197399 CAPTURE OTHER Draw toolbar disappears when using Print Preview
$ N' }% r% ]6 I6 Q5 s1197543 ADW TDA TDO does not correctly show deleted pages
' A8 ^4 E5 I) b& a5 Y, M1198033 CONCEPT_HDL CORE Signals do not get highlighted when Show Physical Net Name is option enabled
0 s7 g( [7 t% k: ?1198468 ALLEGRO_EDITOR GRAPHICS 3D_step model does not show the correct view in 3D_Viewer when symbols have multiple place_bounds.6 v* T7 O. k- e6 E, C: {' x1 k
1198617 CIS GEN_BOM Mech parts are showing with Part reference in CIS BOM y }( o9 h8 }
1199764 ALLEGRO_EDITOR SHAPE Allegro crashes when trying to delete small island on POWER layer.- S& g7 v ^6 T/ ^" Z: F2 ^7 Y# T/ \
1200232 ALLEGRO_EDITOR INTERACTIV Moving all items including board outline which is made of lines does not move the board outline in General Edit Mode.
3 v. W1 ?* m6 `4 q" Q# i6 f: {3 L4 l1200748 ALLEGRO_EDITOR INTERACTIV Additional pin edge vertex object to snap pick# h0 h f2 h1 e- _# M' v$ I
1201056 ALLEGRO_EDITOR DATABASE Unsupported functionality strip design creates a .SAV file' _: [. B8 [; ]8 s- @
1201638 CIS PART_MANAGER Part retains previous linking inside the subgroup
' j' W6 R0 h0 T2 C, ]3 y1201834 ALLEGRO_EDITOR PLOTTING Bug: Import Logo command changes resulting imported object
6 ?7 x+ f/ V; `/ X& K1202406 SIP_LAYOUT OTHER enable the dynamic display of component pin names for co-design dies in Sip Layout
* I. j% o' G+ j' H+ s$ u( t5 U1202431 CONCEPT_HDL PDF The publishpdf -variant option should have a "no graphics" option
4 t( h* C! M! j1202717 ALLEGRO_EDITOR DATABASE About Warning(SPMHA1-108):Illegal line segment ... end points.
9 s3 h. O% k. V: h2 Y0 \1203459 CONSTRAINT_MGR INTERACTIV Object Report has no mechanism to output information for a specific design.
8 `) a( H$ m. {2 ?# u/ n1204544 F2B DESIGNVARI Variant Editor does not warn on save if no write permissions are on the file$ x7 t. {9 @# _9 @
1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDL syntax
$ t# i. C: y2 Q' v2 |1205952 ALLEGRO_EDITOR GRAPHICS Step Model for Mechanical Part is visible in 3D viewer only when Etch Top Subclass is enabled2 p6 C' l! B: Q8 A" W
1206103 SIP_LAYOUT IC_IO_EDITING add port name property to pins, and add Skill access I/O driver cell data
* y2 _4 G1 G3 H$ p1 E1206546 CAPTURE ANNOTATE User assigned refdes are resetting when 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�) y- F p) l, @
1206561 ALLEGRO_EDITOR GRAPHICS Not all mechanical symbols made with Step files are displayed in the 3D View
; _3 p$ W4 o: B1207125 SIG_INTEGRITY ASSIGN_TOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus/ s4 h4 {6 n Z- p
1207386 CAPTURE GENERATE_PART Altera pin file not generating the part properly1 z( A+ D5 T" W
1207629 CAPTURE TCL_INTERFACE Bug: GetMACAddresses tcl command not working' o5 T& m2 _' i+ M& g) ~
1207994 CAPTURE TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pins with black color; l& f0 t! o! _6 ~2 g- B/ _
1208017 F2B DESIGNVARI sch name is not same when updating Schematic View while backannotating Variant, W5 Q+ r4 p2 E) g
1209363 ALLEGRO_EDITOR INTERFACES When placing pins using the polar command the tool returns 4500.00 for 45 degrees.
7 E1 [& r. |) s( [ k a% d5 C1209769 CONCEPT_HDL CORE Top DCF gate information missing' U$ h% m1 o% E, i; w4 \9 [0 R3 ?
1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box) M7 U2 V9 X8 G- X
1210442 CONCEPT_HDL INFRA Save design gives ERROR(SPCOCN-1995): Non synchronized constraint property found in schematic page
, l/ `) x0 l; k: h6 M# y6 N; `& A1210685 ASI_PI GUI User can't edit padstack in PowerDC-lite
# B/ ~& V! V7 {/ |# X1210744 SIG_INTEGRITY SIGWAVE SigWave: FFT Mode Display unit seems not to be correct
' N% ^$ x+ G+ C5 S# b1210829 CAPTURE NETLIST_VERILOG Shorted port is missing from verilog file
6 C- U: e, g7 {% p6 n+ `1210850 CONCEPT_HDL CORE DE-HDL backannotation crashing after instantiating specific cell from Ericsson BPc Library
6 y3 |5 ? B A [9 T) L1211620 ADW COMPONENT_BROWSE Component Browser Performance
' A4 y/ Z0 y* m2 B% P1212102 ALLEGRO_EDITOR INTERACTIV Shape edit boundary adds arc mirrored to the highlighted preview.! x( o) L7 U8 \- M( I3 u9 U
1213294 CONCEPT_HDL SECTION DE-HDL windows mode multiple section fails to section first contactor pin from column of individual pins
: A; G0 I6 P3 h$ K- P' f' u* o' D* I1213402 APD DATABASE The old "ix 0 0" fix is now causing the features to lose nets entirely.
; U f& G/ Y) c6 m+ }1213694 ALLEGRO_EDITOR PARTITION Via connected to Dummy Net pin in Partition gets connected to shape on the board after importing partition
% V" h" l! S8 B1214247 CONSTRAINT_MGR UI_FORMS Selecting the "All" folder in Spacing Constraints in CM does not automatically select the first column for editing
# `) {$ y& `2 R: j: [' P! W# @1214320 SIG_INTEGRITY SIGNOISE signoise command with -L and -k option, d( i3 E- b( Y4 a% X1 m
1214433 CONCEPT_HDL CORE Genview does not update sym_1 with ports added to the schematic7 ~% |( y) F% l
1214909 ALLEGRO_EDITOR NC NC Drill Legend show extra rows for drills' l3 \. c0 h/ [2 g
1214916 SIP_LAYOUT OTHER package design integrity check for via-pin alignment with fix enabled hangs
& }% q0 [% @" y# x) a1215954 SIG_INTEGRITY SIMULATION Cycle.msm does not exist error when simulating extracted net
$ y6 F s9 d* W" z' w1216328 CAPTURE STABILITY Capture crash
1 `# W) k1 l0 [/ U- @0 @0 D0 p1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.049. o1 H$ P- Y/ y1 |$ j4 n
1217450 F2B BOM ERROR 233: Output file path does not exist; v% V0 ]' m$ a
1217612 ALLEGRO_EDITOR INTERACTIV Replace padstack will not replace padstacks that have multiple alphabetic characters in the pin name - AB21-AB37 U, i6 {# s5 I+ ^
1217823 ALLEGRO_EDITOR INTERACTIV Compose shape fails with SPMHIS-473- r. ~; I; i0 B4 X+ u/ }
1217887 ALLEGRO_EDITOR INTERFACES An undo option to be made available in the STEP Package Mapping window
0 G) l% ^: S) C( b1 T k& V1218665 ALLEGRO_EDITOR INTERFACES In step viewer, the bottom side parts are placed above the pcb board surface- d# B" y* i9 O3 a
1219053 PSPICE PROBE PSpice crash with the attached Design
/ C* N5 k7 Z- I) U6 @3 g7 r& @1219067 ALLEGRO_EDITOR EDIT_ETCH dynamic fillets behavior is unstable
, k: M5 D' r4 ]6 U% I1219095 ALLEGRO_EDITOR MANUFACT Design Cross section chart is tapered for two layer board
/ {) p' Z5 X( k" r) l1219126 ALLEGRO_EDITOR SKILL Skill issue with axlRefreshSymbol()
( n" C; o3 Q8 B* i9 w, l" f; r1220701 ALLEGRO_EDITOR INTERACTIV View > Windows > Worldview (showhide view command) fails with command not found3 F' a% y' c8 w4 D
1221057 ALLEGRO_EDITOR REPORTS Units in Cross section report for spacing is not synced with the design( P+ b5 R, Y# x' [, A0 l6 S8 P e
1221139 ALLEGRO_EDITOR EDIT_ETCH Delay tune is not tuning differential pair
4 _8 }, d, ?3 Q. X1221157 SIP_LAYOUT IMPORT_DATA import spd2/na2 file is not importing data correctly into sip* y+ Y* R' t& T9 e% [% H
1221163 SIG_INTEGRITY GEOMETRY_EXTRACT Simulation aborts with severe convergence issue when coupled vias is enabled.( D! S5 w4 r. V: w$ X j
1221416 ALLEGRO_EDITOR DATABASE strip design for function type
& `- d0 g, T2 {% g, f% M# u$ `1221931 ALLEGRO_EDITOR DATABASE Fatal software error when embedding component5 Q* r" p8 U& N$ C9 W. D1 m4 N
1222105 CONCEPT_HDL CORE Moving Pins around the edge of a Block causes the text of the pin to change its text size.
' C% D; F8 `- M# f1222124 APD DATABASE Same Net DRC's exhibiting inconsistent behavior.- M# ]3 h* m, w/ c. ~, f, J
1222272 SIG_EXPLORER EXTRACTTOP Cannot extract net or open SigXplorer after selecting a netgroup$ A5 b- a; [: z. B+ w. f
1222329 ALLEGRO_EDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top
" K; u. E2 K" F4 W; x" U1223183 SIP_LAYOUT BGA_GENERATOR Getting an incorrect error message when using the BGA generator with a long BGA name." [% i! X9 a4 J% X8 E# k9 \; F; g
1223662 ALLEGRO_EDITOR REFRESH Allegro crashes when trying to refresh symbol4 x* _4 w3 u$ L) h
1223932 CONCEPT_HDL CORE DEHDL block desend does not find 1st page if its not page1& v1 o# l1 v X7 @6 x: z6 f
1223940 CONSTRAINT_MGR UI_FORMS Unable to change CLOCK name in Setup/Hold Worksheet under Timing in CM.
& ]" r& B# h1 k8 r% v: g4 t1224127 SIG_INTEGRITY IRDROP Is the old static IRDrop in 16.6 officially supported?
, i+ u! B" B* d. T1225492 PCB_LIBRARIAN CORE PDV expand vector pins resizes symbol outline to maximum height again7 d+ x& e3 A5 R+ B
1225546 CONSTRAINT_MGR ECS_APPLY nets where the referenced ECS maps correctly in constraints manager for front end but not in back end
& g, k# g& `( I3 u" M1226405 ALLEGRO_EDITOR INTERFACES File > Export > IDF ask for filter config file eventhough it is created in same session and stored in parent folder5 z2 |( A8 l+ R4 E2 }
1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDN Analysis with XL and GXL
2 X0 K4 y d: N* p. J1 k! N' H1228721 SIP_LAYOUT OTHER File Export Netlist Spreadsheet enhance sort to be a natural method per Jedec according to customer
1 q& k5 v& Z; P) t! M; e- X2 H% U$ [, p6 O9 t
DATE: 12-20-2013 HOTFIX VERSION: 021
7 G- M1 e, ] V9 W7 b===================================================================================================================================. Y! F- p: G" t5 d0 L" E; O& t" X
CCRID PRODUCT PRODUCTLEVEL2 TITLE( q+ @ E. P: s K1 _0 i
===================================================================================================================================- k( r8 u1 Y9 g: L* d2 d; V
1214932 ALLEGRO_EDITOR OTHER Allegro will crash when performing show dimension on linear dimensions.
3 J* D; n4 W* e: G/ q1215045 ALLEGRO_EDITOR SKILL Successive file open / ipc calls crashes Allegro 16.6( D1 @4 }2 _& r( p; ]: \* A
1215115 ALLEGRO_EDITOR NC drawing name doesn't display in the ncdrill.log file% j) X. G+ I3 _1 p: B( n. |0 E
1216028 SIP_LAYOUT PLACEMENT Design will not update embedded component symbols.
9 l% G# Y; F, g$ z4 q2 z1218451 ALLEGRO_EDITOR DRC_CONSTR Route Keepout to Pin DRC created even after adding Void in RKO shape
$ J' {' G) ]1 {- \$ a8 w1218636 ALLEGRO_EDITOR SCHEM_FTB netin process will rotate embedded symbols
' E0 @1 J% D9 t8 x s: e1218706 CONSTRAINT_MGR CONCEPT_HDL NCC associations get deleted from FE CM
: i- G0 `4 {4 D. x5 N; N& s) Q: A) T+ V9 _/ e
DATE: 12-4-2013 HOTFIX VERSION: 020
) m7 ` j0 l U5 A0 z$ n$ @: R, m" u===================================================================================================================================- Y0 Z" B1 Q8 @+ e# Z6 v/ t
CCRID PRODUCT PRODUCTLEVEL2 TITLE0 V5 O" l& l" C2 d
===================================================================================================================================
1 N0 I. {2 h6 n& o" z1 X( q: K; S1116426 F2B PACKAGERXL Packaging in 16.6 increased by 3 folds compared to 16.3; O$ s' A: R& ^) A3 m% x
1190095 CONCEPT_HDL CORE In Windows mode select the part and click on version placed selected version +1. u, k' p5 M( s" g
1199410 CONSTRAINT_MGR CONCEPT_HDL Constraint Differences Report window hangs in 16.6-s016
0 x7 p4 A' d% Y) u1199425 CONSTRAINT_MGR CONCEPT_HDL Import Physical fails (the cmfeeback.exe has stopped working) in 16.6-s016- [6 @/ [ L6 r( N8 T3 V: j D
1199700 PSPICE NETLISTER Netlist fails on addition of netgroup' p+ O7 Z. X5 n- d
1200936 CONCEPT_HDL PDF publishpdf fails if UNC paths are provided from the command line1 R; _( X$ V" X3 Q% X" u
1202391 CONSTRAINT_MGR OTHER Getting 'An Invalid argument was encountered' when generating Net Class-Class report in CM( v# \' o* A* ]" D
1202587 CONCEPT_HDL CREFER Crefer schematic reports cannot be deleted on Linux.- O6 }& v. C( @+ {/ \# b" }0 \
1203143 GRE CORE GRE crashes on running Plan > Spatial" ^* C" H9 B$ {9 p$ Z
1206019 ALLEGRO_EDITOR INTERACTIV Allegro needs to be restrated to read steppath with 16.6 S017. K9 y9 Y( e( W8 d; E% V# N
1207050 ALLEGRO_EDITOR INTERACTIV Refresh Padstack fails on Warning
' C; h. ~- x F( O3 i r1207178 CONCEPT_HDL CORE Aqua color on wire does not matches icon color' F5 _$ [: V( r# g2 H( b
1208152 F2B DESIGNASSC ERROR: Dictionary File: cmdict.l could not be found
; T, f$ }% z2 Q1 d& _1208276 APD STREAM_IF Stream in fails to import what Allegro exported% v* d) d, ^) n: e# Z" n% L# P
1208345 ALLEGRO_EDITOR SKILL Why axlChangeLayer not working for shapes on this attached skill file?
) }: [. {2 ]" v$ p5 u1208351 ALLEGRO_EDITOR SKILL axlFilmCreate do not define the IPC2581 domain correctly.
4 q7 B6 w- W8 u$ l2 L2 V5 C1208467 PCB_LIBRARIAN VERIFICATION con2con mangles cell data after checking cell having syntax errors on part_table
* x! }. q& t/ p9 t& x1208579 SIG_INTEGRITY GEOMETRY_EXTRACT Incorrect traces are extracted when void area is less than anl_min_void_area setting9 q9 n9 S3 A! r1 w [6 I0 G6 ?
1209347 ALLEGRO_EDITOR PARTITION Import partition that has diametral dimensions will crash Allegro
9 Q3 \* w3 g5 q# j$ I9 f8 J1209897 ALLEGRO_EDITOR PADS_IN Pads_in will not translate design.
& i0 m6 [( o' g, ?5 j1209902 PCB_LIBRARIAN CORE PDV crashes reading part( a+ Q* p* m2 e% e' v0 i; p9 g9 t
1210183 PSPICE SIMULATOR SimSrvr crash with ORPROBE-3211 RPC Server unavailable Message
9 x w& o& m/ q9 k: n1210408 ALLEGRO_EDITOR EDIT_ETCH AiBT hangs when doing interactive breakout on bundles using latest hotfix.& ~/ Y0 @7 j* c Y
1210443 ALLEGRO_EDITOR INTERFACES Allegro Design Publisher does not create fully searchable PDF for some of the text that are present or certain layers. E5 @! B, M7 L2 w
1210876 CONCEPT_HDL ARCHIVER Archiver wrongfully deletes directories.
) L2 g5 q7 N8 @& |' f1211839 CONSTRAINT_MGR DATABASE Topology can't be extracted correctly.
, C! e- D# B3 ]8 Z7 ~# H1212709 ALLEGRO_EDITOR DATABASE No connect can`t be detected in SPB165S048* ^, i- x8 ]+ y" y6 z; e
1213752 CONSTRAINT_MGR OTHER "Show Constraint Difference Report" option at File > Import > Logic does not retain the last setting1 b) j. X- s8 g# C
+ W I8 }4 O/ O% h: A) A ~8 @% YDATE: 11-15-2013 HOTFIX VERSION: 0195 x+ ]" {6 V7 J4 C% e
===================================================================================================================================
7 V6 Z7 L p7 I$ gCCRID PRODUCT PRODUCTLEVEL2 TITLE
3 f& R9 Y# ^8 t3 r' s) b% d===================================================================================================================================
) @: q A$ c- Q5 f1176155 CONCEPT_HDL CORE Graphics remnants with 16.6 QIR 36 W, ] N( G9 r; {5 S, M, K
1178272 CONCEPT_HDL OTHER Verilog netlist does not include split blocks correctly
5 ]; d: {5 P- v6 _2 f, u* f1190782 FSP FPGA_SUPPORT Support for Altera > 5SGXEA9N2F45 device.5 c% i3 V* W0 e! N7 O
1194140 ADW LRM SYNC_PROPERTIES is not resolving issues a based sync_properties settings: d, j/ W' i7 \) o8 m# f
1195744 APD EDIT_ETCH Diff_Pair routing fails on certain Uvias in the pair.3 `& n5 e2 \6 R; l a0 L; R* K
1196704 ALLEGRO_EDITOR INTERFACES ENH: During ipc2581 export checkboxes corresponding to 縈iscellaneous Image Layers� should automatically get selected, g7 E. y4 f6 Z: F
1198340 ALLEGRO_EDITOR OTHER Multiple -product option on the Allegro command line does not access the second -product
1 h+ d" M/ N; m1198596 ALLEGRO_EDITOR INTERFACES When copper thickness is increased for the outer layers, step Viewer does not show correct component position., Z' @5 `# L' w7 x) H2 @
1199673 PCB_LIBRARIAN OTHER Component Browser fails to load footrpints if they are set with UNC path
( U( K: \. f' p! @' L9 C1199889 ALLEGRO_EDITOR DATABASE Allegro crashing with latest hotfix.
! f- d o, z8 i8 w1200303 ALLEGRO_EDITOR GRAPHICS 3D Viewer does not update after changing STEP model mapping
3 E6 n, z! T( [$ |7 y$ R1 W1200449 ALLEGRO_EDITOR REPORTS Allegro crashes when generating Net Loop Report.
" h! Z6 D( s/ m' a) \$ i1200915 ALLEGRO_EDITOR DATABASE Reducing accuracy of this specific design crashes Allegro R9 { e: e7 F6 i9 B
1201011 ADW COMPONENT_BROWSE Component Browser crashes in DB mode1 ?1 M3 w" Q$ ~0 f1 _! ?. ~ d
1201376 ALLEGRO_EDITOR INTERFACES Allegro hangs when trying to map a specific STEP model to a package drawing.
( m7 N1 E- m N, G3 h/ X: W! k; l1201897 SIP_LAYOUT IMPORT_DATA BGA Pin Colors not matching the Colors defined in the Symbol Spreadsheet after updating., p7 K0 D/ K/ I7 e; C1 h* T" p
1202709 ALLEGRO_EDITOR INTERFACES STEP File generated from Allegro is not overwritten when the variable "set ads_textrevs
% F `) u+ x" t) q1202820 ALLEGRO_EDITOR INTERFACES Different xml generation for same step model on S106 and S017
! \$ }* m+ y$ ?5 y$ A. A6 T* L1202842 ALLEGRO_EDITOR INTERFACES Step model invisible for one pin dra in allegro 16.6 symbol editor
6 ]4 j: j1 R$ o. [1202983 ALLEGRO_EDITOR SHAPE Shape voiding creates DRC with Route Keepout
* O& d6 ~ M; J. M% Q# D* J/ Q1203125 ALLEGRO_EDITOR OTHER Exporting STEP file with External copper enabled does not show all copper when viewed with Solid Edge or Inventor
9 D" r$ }% ~* y1203236 ALLEGRO_EDITOR INTERFACES IPC2581 output with crosshatched shape is not correct4 z# V% y( S3 l# [2 f8 F/ Q
1203995 CONCEPT_HDL CHECKPLUS CheckPlus rule, local_signal_no_offpage_body, getting an incorrect failure.
, ~9 P" Y9 ]; |" C' t1204629 ALLEGRO_EDITOR SKILL axlUIDataBrowse crashes the editor or returns error
& S7 F) R5 L* Y5 e1204640 SIP_LAYOUT DIE_EDITOR Concurrent co-design update fails" D6 o$ k. s$ I" C3 r
1204881 SIP_LAYOUT BGA_GENERATOR Pin numbers are messed up after deleting a pin at a staggered bga) T) h4 W" E( q7 }3 n/ F! R
1204885 CONCEPT_HDL CONSTRAINT_MGR Cant assign discrete models after the wrong model was removed.+ O" ]/ t* ?' E# \
1205374 ALLEGRO_EDITOR OTHER pdf out command creates incorrect drill Symbol Characters placement in pdf file when setting film mirrored.
& G- H5 ?! v) H |1 u1205729 SIP_LAYOUT DIE_EDITOR update of codesign db fails on exit from die editor
# o# Y+ z1 z: L7 E8 I1205801 ALLEGRO_EDITOR OTHER Tool crash when do export IPF.6 j1 U" v p! T7 f
1205881 CONSTRAINT_MGR OTHER In CMGR , Objects > Create crashes Allegro' e: o& k6 f9 O
/ W6 W0 _8 B5 L' `. I$ v' YDATE: 10-25-2013 HOTFIX VERSION: 0184 w- R7 C0 ^ t' |
===================================================================================================================================
' a% o1 {) i( i2 t; KCCRID PRODUCT PRODUCTLEVEL2 TITLE
% S" o4 b3 _; ]" ~* d+ D===================================================================================================================================& @/ G% c0 z8 Q* T, y. v- R
1118303 CONCEPT_HDL CONSTRAINT_MGR can not prdefine default units in HDL
0 w1 U; }6 \8 G4 T4 s: G0 R; P8 u$ t0 v9 x1174901 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl
6 M7 e! e& U8 B6 B% {3 d1176990 CONCEPT_HDL OTHER DEHDL BOM tool doesn縯 see similar names.
: T' M) s& v) H1179665 GRE CORE Plan Topological Crashes after around 8 hours of routing.# J2 L' E/ U% c0 m
1188193 CONCEPT_HDL CHECKPLUS CheckPlus not recognizing PIN as a base object.$ r* f. R* k9 _# O( ?
1189100 SCM OTHER Replace part in SCM using ADW as library fails
4 C4 I- N9 e, R5 [: B6 K9 a. N7 M( K1189507 SCM SCHGEN ERROR(SPCOCN-2009): Package error after second schgen run with Preserve mode.7 w8 A, V [2 j/ Z' n) ]4 g
1192391 CONSTRAINT_MGR CONCEPT_HDL Restore from definition deletes local objects in other blocks
) P1 `( m; k1 @ \$ |; l% H) _1194597 FSP OTHER Pin definition problem
N6 ]/ t/ ~ r1195202 SIP_LAYOUT LEFDEF_IF Cannot add .lef files in IC Library Manager. Getting warning message WARNING(SPMHLD-52)
t& }7 K0 D/ \# H1195309 GRE CORE GRE crashing during Plan Spatial.
. x- Z, q+ A5 @1197262 ALLEGRO_EDITOR MANUFACT Angular Dimension created in symbol is placed w.r.t. board origin and angle is blank
9 u R2 h8 r. P- x6 V9 U1198521 CONCEPT_HDL OTHER cadence DEHDL issue - Note for Hotfix_SPB16.60.016_wint_1of15 L8 o/ U: c: Q4 O+ l+ g
1199219 ALLEGRO_EDITOR INTERFACES Question on STEP Model export which uses PLACE_BOUND layer for any symbols that do not have STEP model mapped! t3 w P; k- Q$ I
1199235 ALLEGRO_EDITOR SCHEM_FTB capture's behavior is redundant while creating pcb editor netlist
( o8 x* c7 F' O$ Y1199323 GRE IFP_INTERACTIVE Crash when importing logic# q" a& `1 Q" e
1199368 SIP_LAYOUT DIE_EDITOR Refresh of die abstract in die editor with this design takes over two hours
! \: q8 X/ y# p7 r) y) U1199760 ALLEGRO_EDITOR DATABASE Allegr won't display Soldermask Top layer
y, w2 \, r' A0 @% U$ Q- n3 V$ k1 R: P
DATE: 10-10-2013 HOTFIX VERSION: 017- e& Z1 F4 V6 e$ B( u- n
===================================================================================================================================- T* h8 B1 t. n0 b) G% M0 z
CCRID PRODUCT PRODUCTLEVEL2 TITLE' M+ Z, Q9 p: S4 T3 `6 p% l- [
===================================================================================================================================8 |- {" R0 |, f& V
735992 ADW LIB_FLOW Create Test Schematic does not use the correct package type
8 ?% H0 f1 f$ x! h" V1121403 FSP PROCESS "Assign to Pin" not getting obeyed by Synthesis.
" |$ T# X4 F0 Q, F, N5 P9 B1141844 RF_PCB DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing( {0 P( `" q# `# b- d
1169269 ALLEGRO_EDITOR DRAFTING Dimension placed on package symbol moves to different place when it is placed on brd file.+ j2 A* I- u/ O1 f( j6 s! |
1170488 ALLEGRO_EDITOR MANUFACT Dimension text(on .psm) move to different position, when it is placed on .brd.
9 o* F/ }4 u J9 f! z1173345 CIS CRYSTAL_REPORTS Crystal Report - Display Parameter dialog for export option6 }; a' E( x" K3 b& b- M
1181759 SCM LVS SCM Crash when doing update all that executing import physical command.9 Q6 h* B$ z$ H- J: _ R& }
1182499 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks (all pins and via) drill.
& u: }* n+ C% V4 C& Z7 i4 g1184682 CONCEPT_HDL CONSTRAINT_MGR Net Constraint not transferring to layout from schematic/ u! A% t) ?0 p5 p
1185524 F2B PACKAGERXL Enhancement User would like notification of pack_short in pxl.log; F& t5 b& j0 E1 |* P
1185902 ALLEGRO_EDITOR SHAPE Update shapes dont clear some diffpairs in HF15: k- O3 T$ n' x/ o" l8 ~. K# ?
1186152 ADW LRM Part Status for Deleted Part in LRM is distinguished with other part status
+ n# t8 `, n' Z Z& f1186387 ALLEGRO_EDITOR OTHER DXF cannot catch offset value in s047 hotfix.
6 \$ t" \. W$ w( y @8 X; Z1186805 ALLEGRO_EDITOR OTHER Exported STEP file missing multiple components placed on board: P7 l0 r4 e( p$ J8 o
1186818 ALLEGRO_EDITOR COLOR Custom color not retained during dehilight4 c2 t7 R# z5 Y) C, s
1187196 CONCEPT_HDL CORE TOC not populating (page 1)3 f6 d7 u- t# k: R! l6 N. W* T! |
1187667 F2B PACKAGERXL Existing hard LOCATION property in drawing was left unchanged
! y$ o7 w) y% v4 r1188264 ALLEGRO_EDITOR MODULES Some fillets not regenerated in module created from a board file.
6 h. B4 t) ^4 `/ W1190144 ALLEGRO_EDITOR OTHER Fillet shape is not genrated around cline
) i! S/ X( I/ u1190210 F2B BOM The bomhdl.exe fails - MFC Application has Stopped Working% i- K7 _+ n6 U4 D) r% ~/ r
1190618 ALLEGRO_EDITOR GRAPHICS Enhancement for Visible grid
! I+ ?5 n" y: V1190813 ALLEGRO_EDITOR INTERFACES 3rd party netlist file in TEL format fails syntax check but imports successfully! O6 F6 U& s) w( F( K/ I
1190895 ALLEGRO_EDITOR EDIT_ETCH Route delay meter displays violation when sliding diff pair
* ]6 r/ V& V- b6 h1190908 F2B OTHER DE-HDL aborts if dummy net is being cross-probed from PCB Editor
* g) z/ ?8 X; ~* o/ |) Y6 u1190990 CONCEPT_HDL CORE Mismatch in .csa and .csb files5 n1 ~% t( y5 H4 |7 n. z( w b
1191008 CONCEPT_HDL CORE Remove Binary File feature doesn't work
9 D* }8 y. z: \1191514 SCM PACKAGER Packaging error PKG-100
( r, _! l* g) T0 {: q) [1191517 ALLEGRO_EDITOR DRAFTING Metric +tolerance when using dual dimensions is not displayed correctly
# j. @" D. U! {( K0 W1192561 ALLEGRO_EDITOR GRAPHICS Padstack with offset is not showing correctly in the 3D Viewer.5 P9 M. f6 S( ~5 c
1192916 ALLEGRO_EDITOR EDIT_ETCH Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.
# N. K5 v# |( t2 d- v1194197 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks.
; Z+ M3 Y% `/ j8 S3 V: m1194239 PSPICE DEHDL Associate Model does not launch from DE-HDL6 }1 @: k( u) j; V2 L( U5 G t
1194736 PSPICE SIMULATOR Design causes RPC failure when run consectively
* ~3 D; @1 ?# d! ~( ^4 q$ t1195139 ALLEGRO_EDITOR PLACEMENT Components disappears from board file once they moved
4 d! H8 v. P% T6 M7 d n) j& O7 L$ F/ w B x
DATE: 09-27-2013 HOTFIX VERSION: 016" x1 f" K, I6 E4 x) z' s* J- ]
===================================================================================================================================; {8 H0 ?4 r3 r4 V
CCRID PRODUCT PRODUCTLEVEL2 TITLE
0 h7 n) L, ?* O/ E2 \===================================================================================================================================6 Y2 d# Q" j# L7 ]
548538 CAPTURE NETLIST_ALLEGRO Enhancement:Include mechanical parts in Allegro netlist
' G9 f1 O( M7 [1 B1076579 CAPTURE GENERAL Display value only if value exists P- e: N1 C& w7 j
1083904 FSP GUI Need Filter in Change FPGA dialog to select desire FPGA from the long list.
' w- ]! P( d& {1089313 ALLEGRO_EDITOR INTERFACES Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility
0 F$ p8 ?& n# ?* c0 x/ S, h1095728 ALLEGRO_EDITOR EDIT_ETCH Slide to grab adjacent elements when extend selection is enabled! `( S. ~* `3 K: r( X
1102698 SIG_INTEGRITY ASSIGN_TOPOLOGY ECset will map on single ended nets but fails when the two nets are define as a diff pair.5 x$ Q7 Q7 `% K( D8 u
1104071 SIG_INTEGRITY REPORTS Shape Parasitic value changes for bottom shape for changes in top shape
- ~1 T, g z9 F- X7 S+ t1117731 FSP POWER_MAPPING Ability to sort in Power Regulator forms8 L5 H/ q( d1 g: R7 F0 o: D# t) p# _
1121539 FSP CONFIG_SETTINGS Cannot configure special FPGA pins (temperature diodes)* O3 N' T7 r& d, E2 W. v+ S) Z4 l x
1122721 FSP MODEL_EDITOR Partial copy-paste overwrites the complete cell in XML Editor5 Y1 i' k1 W: |* j) D- [
1123238 FSP TERMINATIONS Report functionality for terminations defined in the complete design.. X, c+ O3 T- P f% G% c
1123364 FSP GUI Clicking on column header should sort the column. t4 `8 N' ]- h+ t0 T* |- k) b
1123403 FSP EXTERNAL_PORTS Improper checkbox selection for 緿o Not Connect� or 縀xternal Port� column; E, P2 Q( |( f* {* S
1125611 CONCEPT_HDL OTHER display unconnected pin in schematic pdf.5 F% W) O9 l; z0 k
1129871 ALLEGRO_EDITOR INTERACTIV Wire Profile Editor can't read mcmmat.dat in working directory.
. k$ n* L) I% m8 y* a1133688 ALLEGRO_EDITOR GRAPHICS Enhancement request to enable 3D Viewer to show STEP model from .dra file.& I+ A& C/ g5 G+ E
1141747 ALLEGRO_EDITOR GRAPHICS 3D view dooesnot displays height if step_unsupported_prototype variable set* i4 g: ?! e1 q/ L* D0 c
1142215 SIG_INTEGRITY SIMULATION PULSE_PARAM set on DiffPair wasn't used for designlink simulation.
. e# {: g9 y. O- f B1142798 ALLEGRO_EDITOR INTERFACES Step file output is incorrect in step viewer when composed of arcs and line.
, @6 Z5 o" Q5 z; ^+ d! k1142894 FSP GUI Ability to RMB on a header and select `Hide Column�3 h, @1 i' p7 M, a- p
1142940 FSP EXTERNAL_PORTS Issue with checking/unchecking "Do not connect" and "External port" cells# }* b. }7 f- Z6 J
1142949 CONCEPT_HDL SKILL Usage of "Preferences > License Settings� in FSP& C/ |7 \; K9 `
1143091 SIP_LAYOUT SYMB_EDIT_APPMOD symed: When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract$ y" x; X6 |( j) v2 m2 b, W' h
1144371 CONCEPT_HDL COMP_BROWSER Component Browser search results are inaccurate
% c+ ?8 A5 {3 y- A! {1145033 ALLEGRO_EDITOR PLACEMENT When aligning components with options in Placement mode displays no busy indicator
7 K2 p- l' d% ~1145286 CONCEPT_HDL CORE Directive required for switching off the console5 X y( A3 t L0 n6 @$ V; w
1145800 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl.% Z. i; B. `4 l; t8 L$ Q0 p, f
1147899 ALLEGRO_EDITOR SHAPE Autovoid two overlapping shapes that share the same net" l- F! g& L: j8 p4 z8 @5 [* i
1149996 ALLEGRO_EDITOR EDIT_ETCH Routing does not follow the ratsnest 'pin to pin'.- i N4 I: S9 n* Y, @) ?. w
1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.1 i# w6 X$ n! D& R; m
1152577 ALLEGRO_EDITOR DATABASE slide removes cline seg
# X2 B4 v+ _: Q% \1152751 CONCEPT_HDL CORE Option to double-click and copy the Netname
" H6 B5 R1 |3 X8 m1153220 ALLEGRO_EDITOR INTERFACES ENH: option to supress header/footer during PDF Export
2 X4 a& t- C) Y5 @5 W& i E4 k! j& V7 v1153625 ALLEGRO_EDITOR INTERFACES If Symbol has place bound bottom, the step model shows incorrect placement.7 u" _9 t1 z" J4 X+ H
1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form
/ _( d0 d+ K/ Y" Y$ {# C1 R1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties.% {5 Q5 r4 S0 d: d3 }; Z- c2 o# t7 }
1155161 CONCEPT_HDL CORE Add Signal name: Suggestion box overlaps with the typed signal name that is typed
6 h6 i; A8 O; }6 b2 P) @1155922 CONCEPT_HDL OTHER How can I use the batch mode for PDF Publisher and print a variant overlay?9 f( w7 D% t: O" U0 I# U' o3 E: e
1156858 ALLEGRO_EDITOR PADS_IN PADS Translator: Missing drill on square PTH padstack
0 `. T! c% U1 \' N2 v" S& W1157362 APD 3D_VIEWER Need a way to color multiple nets in 3D viewer from APD/SiP.
" S. `/ o2 b9 ?! z8 Q2 _1158130 CONSTRAINT_MGR ANALYSIS Constraint Manager do not display the Cumulative Result in Reflection Simulation( h% H% n$ i1 c- P$ S
1158210 ALLEGRO_EDITOR SHAPE SIP Layout happens crash while users move the shape with route keep-out5 t% b( p2 ~) L Q
1158452 SIG_INTEGRITY GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle1 A: b) `2 `) U7 B# i
1158827 ALLEGRO_EDITOR EDIT_ETCH Slide a via in pad automatically add cline back to via to pin.6 `1 q+ M0 [, v2 u% b. i, J. G
1158871 PCB_LIBRARIAN IMPORT_CSV PIN TEXT is not automatically added when importing the .csv file7 x+ K" v9 G5 u* c# w( T. n
1159738 ALLEGRO_EDITOR INTERACTIV Selecting the Cancel button in the Text Edit command does not cancel the text." Y0 ]( ^8 w0 \7 W
1159878 SIG_EXPLORER OTHER Ecset mapping dont follow topology template
# M. I7 x ]3 Y. }- m9 f& j$ f1159971 ALLEGRO_EDITOR MANUFACT Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file
/ B- A$ k$ Y0 E3 Y1 s) E1160017 SIP_LAYOUT DIE_ABSTRACT_IF Add text to clarify shrink operation" O( K/ Z8 i; P& Z6 J5 c' }
1160507 APD EDIT_ETCH Script not playing back what was recorded when sliding lines( j1 b! |* ^; ~' [7 v9 V
1161261 ADW TDO-SHAREPOINT Schema for TDO-SP fails on Japanese OS
$ m+ Q: M1 t! r; L4 o7 E g1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
( o6 W# n' Z( m1161636 ALLEGRO_EDITOR DRAFTING need new function for PDFout : hatching shape' L! ]5 ?: g. i9 [
1161777 ALLEGRO_EDITOR OTHER default line width for PDF output
' [( X' W( C t1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
! A+ A7 _* l7 y0 ^6 u4 B: y1162562 CAPTURE STABILITY Capture crash on second attempt of pspice netlist creation in 16.67 n2 u% h* c/ B5 A, V
1162629 FSP PROCESS "Load Process Option" under Run does not work properly
0 H" f1 c* Q- h+ a q1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE
+ F( T) _& T# L* K; \6 J* m1163149 ALLEGRO_EDITOR DATABASE Autosilk creates Illegal arc to corrupt database
7 f9 ?, y8 @3 U, F! U4 B7 m/ L1163439 ALLEGRO_EDITOR COLOR Duplicate Views Listed in Visibility Tab.
* |3 g( [, I6 h4 b9 a5 K/ j$ g1163521 CONCEPT_HDL COMP_BROWSER System Architect crahes on replace2 S9 j, Y2 B9 B- R, u4 `6 z
1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin2 n7 y. e2 l% D- f: Z `6 ~
1163902 APD EXPORT_DATA Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?
8 E0 h% c5 `3 K: U9 S( x1164337 CONCEPT_HDL CORE Cannot delete attribute filter value in PDF > General > Attribute Filter list
) y) P5 q# I! C1164365 ALLEGRO_EDITOR INTERACTIV Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol
% P. w# [' b V" Y; n1164769 APD VIA_STRUCTURE The replace via structure command does not accept a single canvas pick.
! i: }: Y; K6 y: D0 S4 m$ x3 x* g1165026 ASI_SI GUI EMS3D exist in Via Model Setup of SI base.: H! E" V5 d2 l' X
1165561 CAPTURE DRC File > Check and Save clears waived DRCs& r' B! H6 f, ]& c
1165631 CAPTURE STABILITY Capture crash in the hierarchy tab of Project Manager window
3 k5 y) B, i$ O% G1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)6 }% _+ I' P9 j9 y
1165911 FSP PROCESS Editing group name in protocol causes incorrect Process option checked4 Y% |& z1 y+ y. f$ Y
1166026 ALLEGRO_EDITOR DATABASE Running DB Doctor removes net name from vias
$ ` I1 B' C' V1166034 SIP_LAYOUT OTHER SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle
$ v9 O9 f) G5 d5 U1166074 GRE CORE GRE crashes during planning phases
, B9 A3 A" J7 s; w; q! x8 r1166319 ALLEGRO_EDITOR PLACEMENT Swap not succeed4 l" w0 L, B- \
1166484 SIP_LAYOUT WIREBOND Bondfinger "Align With Wire" problem during move
f' d8 H J4 s1166530 ALLEGRO_EDITOR INTERACTIV Bug: Mirror in Placement Edit resets the options tab for Edit > Move/ j7 T5 B, t+ e0 a! O; y
1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue
( n- x1 z3 f- e5 L4 i0 t" C$ S1167847 CAPTURE PROPERTY_EDITOR Implementation name length greater than 31 character causes capture crash
% o+ B7 c. E- D- C1167887 F2B OTHER Improve message on symbol to schematic generation
2 [' v9 B: E. B4 V# P) W1168369 F2B DESIGNVARI Variant don縯 appear in increasing order while Annotate.% W0 H% P+ f* d" A' l0 V
1168629 APD OTHER Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD1 X( @* H, p- J* O0 R. l" W
1168678 ALLEGRO_EDITOR NC Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.
6 T9 g: E8 K% S2 m# Q/ \1168798 ALLEGRO_EDITOR INTERACTIV Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk
2 d# y& m7 m: u5 q1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check5 i* U! t& C2 ~
1168864 ALLEGRO_EDITOR CREATE_SYM Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty
& t. ^: k! p2 a) t7 u1169213 PSPICE SIMULATOR Parametric sweep is giving incorrect reuslts
Y: w/ \* m- f1 m1169436 FSP FPGA_SUPPORT Add support for Cyclone V CSX and CST parts
' I4 Z9 T6 ]8 F. M- ^1 V1170108 ALLEGRO_EDITOR INTERACTIV Enhancement to preserve Rat T location for Topology assigned schedule& `, [1 Z& X. `* `: O5 W
1170313 SIP_LAYOUT LOGIC scm adding additional pin names and unassigned property to codesign die chips file7 r% ~+ i" B6 k
1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window.
2 j9 ?0 ]2 j4 d1171747 ALLEGRO_EDITOR PLACEMENT Allegro crashes when doing a gate swap between components
# R, b" {; y \1172183 ALLEGRO_EDITOR INTERACTIV Alignment modules fails on equal spacing" j5 P4 m1 A9 v0 q* V
1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via
5 G; s3 L1 v3 }1174067 ALLEGRO_EDITOR DRC_CONSTR Soldermask to shape drc does not show if the layer is a PLANE.+ T0 {7 i# i! ], f
1174338 ALLEGRO_EDITOR PLACEMENT preview has rotated pads8 o/ l- Q9 G3 h. D7 {( x$ p4 w& I
1175307 CONSTRAINT_MGR ANALYSIS CMGR fails to report RPD DRC for accuracy 4 - mm* o W' H4 O7 u/ Y6 R8 z+ B& J* f. O
1175537 ALLEGRO_EDITOR REPORTS net loop report crashes Allegro. Design specific+ X9 q+ o: c+ I' z; _. Q) u% b
1176126 ALLEGRO_EDITOR INTERFACES 3D viewer doesnot change models units dynamically; C8 S3 r2 }* K( M! r
1176281 CONCEPT_HDL CORE Option to Auto-hide excluded modules
/ x# t( e) m: d- S1176413 ALLEGRO_EDITOR MANUFACT Q - testprep parameter settings is not retained, what could be the cause..* x. X9 C, S! c) Y( G, M" B: Q( V6 K3 g
1176791 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl Z3 C" q# z( Z0 @, n, ~
1178052 ALLEGRO_EDITOR SHAPE SIP crashes during shape degassing.
/ A" Y! u8 C7 i1178158 ALLEGRO_EDITOR INTERFACES Export step file creates step file of same height. J. V7 ?* d, R3 G1 s8 b
1178201 ALLEGRO_EDITOR GRAPHICS Large oval pads rendered as oblong hexagons in the 3D viewer
9 [. A* |' w6 e1178671 ALLEGRO_EDITOR GRAPHICS 3D Viewer in package symbol editor not displaying correct place bound shapes.* a8 @: @- _" l" P! Z
1178725 ALLEGRO_EDITOR OTHER With fillets present, rat lines do not point to the closest endpoint.( r9 k3 d7 v' `+ T
1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.7 w7 D b2 l- W: U6 u: N- u! H
1179093 ALLEGRO_EDITOR SHAPE Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.
" L, s! |$ u4 P8 a2 \9 @- o; X. n1179109 ALLEGRO_EDITOR OTHER DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version! {- {/ q) H7 a* Y, `3 ]0 A
1179571 ALLEGRO_EDITOR ARTWORK Artwork crash and artwork log report Aparture missing
2 p- }# v3 A- @& ]! }5 T. O2 x1179636 SPECCTRA ROUTE Route Automatic will not start if NET_SHORT are attached to a mec-pin
+ F* |% F9 z! z: ~1179659 SIP_LAYOUT DIE_EDITOR die edit on co-design die losing c4 bumps
+ X# A( N# f/ h3 r5 M, A @1180306 ALLEGRO_EDITOR ARTWORK When trying to create Artwork the tool crashes with no error messages just a little X box7 M. Z/ a; `& C2 ~! Q! F
1180573 ALLEGRO_EDITOR ARTWORK If one layer has warning, all artwork films are "created with warning".2 k' l( B5 Q6 x8 R# V+ q
1180960 SIP_LAYOUT PLACEMENT swap function is not swapping logical paths in sip layout!
/ n3 x$ U$ z( U2 z: `* h" F1182534 ALLEGRO_EDITOR SKILL axlLayerPrioritySet() not working with v166 s013 and up9 a- M) }2 T; }* |4 X2 e n
1182560 ALLEGRO_EDITOR PLOTTING Creating plot 2nd time casues Allegro to crash# K/ Y# M$ `& x& m. o( o" C; {' _& l# a
1182616 ALLEGRO_EDITOR PLACEMENT Application crashes when attempting to place a high pin count BGA) h( M4 ~! h+ [5 {! ~ Y% l2 m
1183752 CONCEPT_HDL CORE Unable to modify location properties within a read-only hierarchical block
f2 t& B+ j, H/ e1183774 SIP_LAYOUT DIE_EDITOR Die Refresh hangs
! b' C7 B# T* G" h% Z6 y1184178 CONCEPT_HDL CONSTRAINT_MGR Ecset xnet members lost from electrical class when restore from definition of subblocks
' |8 T) b! I6 P1184787 ALLEGRO_EDITOR EDIT_ETCH Allegro SPB166 s 015 crashes during normal add connect function.% e& F. K% X2 d/ \
+ `) I6 s- t# v8 o# w2 j8 s
DATE: 08-22-2013 HOTFIX VERSION: 015$ K9 K; z' E9 z9 U) }
===================================================================================================================================
3 `# ~' {7 ~9 s! c5 yCCRID PRODUCT PRODUCTLEVEL2 TITLE
6 n0 s* @6 V3 _: C4 `* l& P' Y===================================================================================================================================1 C A+ Y8 }# w, B: l
1156102 PCB_LIBRARIAN CORE PDV severe performance degradation on Linux platform makes PDV counter productive after some time3 Z, O5 g3 e1 Y! }0 B
1165756 CONCEPT_HDL CORE DE HDL 16.6 adding ASCII character to properties
^4 ^" U w) \0 @7 x7 ?; k1169896 ADW LRM Library Revision Manager makes updates but the interface never returns to the user$ Z* N+ z5 @; p! O- s2 e( e
1170635 SIP_LAYOUT WIZARDS BGA PIN NAME doesn't sync with PIN Number# e& k# ?% a. i6 S1 h
1171061 ALLEGRO_EDITOR PLACEMENT Place Replicate Apply cannot place module
# ]' W; l$ C8 o1171415 CONCEPT_HDL CORE Mismatch in the interface ports in design bw_hybrid for block a38410_scsp
6 v/ [) }# U5 d9 \# Q: C1171598 APD WIREBOND Cannot load xml over 65 profiles defined in file.2 h$ f6 ^ F0 ?/ z
1171713 ADW LRM Blank lines appear in the LRM - RM-Clicking causes LRM to crash2 h' }3 ]1 F$ a
1172576 SIP_LAYOUT IMPORT_DATA AIF import fails with Error: symbol is missing refdes
- o6 C5 N+ r# a1172938 ALLEGRO_EDITOR PLOTTING Export IPF probrem
; m9 ?, B; f) _7 [: e" Q5 D! E4 s1173190 ALLEGRO_EDITOR ARTWORK Not able to Add/ Replace film_setup.txt file in Artwork control file.
' W' \: h4 _, L+ w: [2 b1173750 ALLEGRO_EDITOR REPORTS SIP tool crash when clicking report "Net Loop Report"
5 j9 ?' n6 E+ i, C4 P/ n, r1175582 ALLEGRO_EDITOR SKILL axlDBCreateFilmRec error undifined function# f& Q A% M+ P1 L
2 f' c! a$ J* {. I' h h! h5 z2 KDATE: 08-9-2013 HOTFIX VERSION: 014$ O5 H, d! K5 ?5 T2 G! O2 S% o$ U. p
=================================================================================================================================== N5 Z. U$ O& \. A
CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ t8 z/ V3 Y- t6 e2 r# x===================================================================================================================================
. N- l( P' V! `" m) c; }1155569 APD MODULES P1_U1 and P1_U3 Die pins are missing after Place Module." X9 v' i# F& i
1158528 CONCEPT_HDL OTHER Dual Monitor issue: Retain Hard Packaging option is missing and attribute test distorted
9 D. Y. w: e9 V7 Q* C, t" s1160968 ALLEGRO_EDITOR SKILL Text Subclass change difference in Edit > Change and axlChangeLayer Skill command
3 h( k% ^0 ~4 [& U7 @ X0 v1161986 SIG_INTEGRITY SIMULATION Flatline waveform seen when via model is set to detailed closed form or analytical solution
) d& b4 W+ n3 H% T% M1162323 SIP_LAYOUT DIE_EDITOR Die Editor is incorrectly leaving an unassigned function pin in the die during refresh from die abstract5 Q D N( h5 x0 T5 N
1162752 ALLEGRO_EDITOR SKILL axlDBChangeText doesnt recognize ?layer as a valid argument as documented F8 }) U2 ]) H! ?6 z- X
1165002 GRE CORE GRE Crashes during Plan Spatial giving "Memory Allocation Failure" Error.3 s2 }, s7 H- p7 E
1165469 CONCEPT_HDL CORE Import Design loses design library name5 i2 N" y3 ?7 C9 K* v& ]. _! J
1165708 ALLEGRO_EDITOR TESTPREP Test point router failing when attempting to insert new TP via's. s& ]6 E1 o2 b: b; Z0 t
1165801 CONCEPT_HDL PDF Pin texts of spun symbol overlap in publish PDF.
! K: `$ p2 F; _( H! D1166020 SIP_LAYOUT WIREBOND Bondpads created with shapes do not follow the orthogonal pattern when adding wirebonds.: x3 j5 U5 R3 y( b
1166371 ALLEGRO_EDITOR DATABASE File locked for writing in 16.5 cannot be unlocked in 16.6
$ G7 [& ]# ]( j1166482 ALLEGRO_EDITOR INTERFACES Step orientation for y-rotated component is not exported correctly.+ `* s# Q2 P0 M; w" s2 n
1167519 ALLEGRO_EDITOR DATABASE Uprev dbdoctor does not log warnings about renaming properties.
! H$ y" `5 S q6 F1167588 SIP_LAYOUT DIE_ABSTRACT_IF do not create a new pad stack for each I/O pad, t" n! c( i9 _: o- V1 n+ v4 ~
1168496 ALLEGRO_EDITOR SCHEM_FTB Export Physical Crashes when netreving the board9 m- f2 _( t. a5 p6 L& u* R6 ?
1169510 SIP_LAYOUT WIZARDS Netlist in Wizard is crashing with this text file where the Net Name for one of the assignments is blank, meaning dummy: a; k+ E( l# E. }, v; c) e/ w
1169593 CONCEPT_HDL PDF Published PDF file's hyperlinks do not work fine when user click 1D10 or 2A10.3 E6 g' L3 S/ s# Q- C$ R1 A
1169984 F2B PACKAGERXL Error Mapping cset when packaging but not in CM Audit
2 Z4 C* u; E" c2 P9 q1171008 SIP_LAYOUT OTHER SiP Layout - Beta feature Void Adjacent Layer Shapes - changes or modifies "priority" of other/all shapes- w8 `( y& _# J: z( J# F! G
1171411 ALLEGRO_EDITOR OTHER Enh - Break in Step 3D view in latest hotfix v16.6s013* k f \6 _4 k! H0 y4 T% c3 v
9 m" H- V# E0 j8 \DATE: 07-26-2013 HOTFIX VERSION: 013
: X8 A8 s- ~" v9 F: a7 V) c===================================================================================================================================# ~/ v' t" V4 ?1 U# w
CCRID PRODUCT PRODUCTLEVEL2 TITLE8 `8 g- R y. O2 Y8 ~
===================================================================================================================================5 V' E* }- J& |3 I/ _
111368 CAPTURE CORRUPT_DESIGN Capture - will not produce allegro netlist with 10.0
& O* o7 {' Z6 y- Q. C2 O9 u! P0 i0 S134439 PD-COMPILE USERDATA caCell terminals should be top-level terminals& s9 e4 y: i' \* i% ^0 j
186074 CIS EXPLORER refresh symbols from lib requires you to close CIS; ~8 x8 t, z8 X4 ?) E: |
583221 CAPTURE SCHEMATIC_EDITOR Option to have the Schematic Page Name as a Property in the Titleblock+ x+ `( X) e( C# S
591140 CONCEPT_HDL OTHER Scale overall output size in PublishPDF from command line
4 s9 D3 ?" B- j3 l2 g' b801901 CONCEPT_HDL CORE Concept Menus use the same key "R" for the Wire and RF-PCB menus
1 ~( r. K! R" B+ b$ t& {% K813614 APD DRC_CONSTRAINTS With Fillets present the "cline to shape" spacing is wrong.
: D, o3 j: L9 {/ G: S1 g881796 ALLEGRO_EDITOR GRAPHICS Enhancement request for Panning with Middle Mouse Button
y) e/ S3 z1 V& d887191 CONCEPT_HDL CORE Cannot add/edit the locked property
0 o9 W9 O9 [" C7 D911292 CONCEPT_HDL CORE Property command on editing symbol attaches property to ORIGIN immediately4 w- ]! i- W) P, i3 {
987766 APD SHAPE Void all command gets result as no voids being generated on specific env.- F% n! M: r: w7 ?7 k* ?" D/ H; A7 B5 D8 T
1001395 SIP_LAYOUT ASSY_RULE_CHECK Shape Minimum void check reports lots of DRCs which are not necessary to check out.
1 l/ M, r5 Y p$ m( j7 M5 O1030696 ALLEGRO_EDITOR INTERACTIV Enh - Allow another behavior of PAN movement using middle mouse in Allegro
4 a# Q7 S( t9 `1043856 ADW TDA Diff between TDO and DE-HDL Hierarchy Viewer is confusing to the user
) u( }5 \4 y7 U! [1046440 ADW PCBCACHE ADW: ImportSheet is not caching libraries under flatlib/model_sym when the source design is not an ADW project9 w3 Q* ?1 I& t2 W8 Q* S+ ]! ^
1077552 F2B PACKAGERXL Diff Pairs get removed when packing with backannotation turned on& i! ^7 j1 T9 L
1079538 F2B PACKAGERXL Ability to block all 縮ingle noded nets� to the board while packaging.
! G8 r& _/ N1 n9 }( G9 G# k1086362 ALLEGRO_EDITOR SHAPE Enhancement request to autovoid a via if shape cannot cover the center of the via.
- q8 B. i, q$ ]" v1087958 PSPICE MODELEDITOR Is there any limitation for pin name definition?
0 d; s- a" n, j1087967 CIS UPDATE_PART_STAT Update part status window shows incorrect differences
% C# P$ I8 d# x7 p S1090693 ADW LRM LRM auto_load_instances does not gray out Load instances Button8 r1 ~: s ]( y6 V. @& w v
1097246 CONCEPT_HDL CORE ConceptHDL - assign hotkeys to alpha-numerical keys6 t# \/ p7 f. q* e; m; S# d
1099773 CONCEPT_HDL CORE DE HDL goes into recursive loop if a custom text locked at site level is deleted from Tools > Option5 f3 y/ Y" D. B. U* [7 o, n& F* q
1100945 SCM SCHGEN SCM generated DE-HDL has $PN placement issue
4 R4 x. @4 i% ?9 r" f5 [ `1100951 PSPICE SIMULATOR Increasing the resolution of fourier transform results in out file
0 H( Y; Y ^9 [/ L) ~: Q4 J" [1103117 RF_PCB FE_IFF_IMPORT Enh- Allow the Allegro_Discrete_Library_to_ADS_Library_Translator to output in its original unit- c( l5 e% z; C6 S+ V
1105473 PSPICE PROBE Getting error messages while running bias point analysis.7 r8 n+ r' t. \! N5 T1 i3 U2 ?
1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr./ m( b1 {- ?, ]: B. b7 [) H0 g
1106298 ALLEGRO_EDITOR INTERACTIV Copy Shape uses last menu pick location as origin and not the Symbol Origin as specified in Options.
7 R' e6 J( A& h1 ^1106626 CONCEPT_HDL CORE Concept HDL crashes when saving pages4 h* v9 O9 E# ^4 ~& `% x( V
1107086 ALLEGRO_EDITOR INTERACTIV manual void with arc's goes in wrong direction during arc creation
( e2 _, a8 m* u# j6 O4 B" z: D; g1107172 CONCEPT_HDL OTHER Project Manager Packager does not report errors on missing symbol6 q% ?( o+ ` @
1108193 CONCEPT_HDL CORE Using the left/right keys do not move the cursor within the text you're editing' e: H R( K; H/ u
1108603 PCB_LIBRARIAN VERIFICATION PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm( S' \+ _: ~4 [6 y2 ]5 {
1109024 CIS OTHER orcad performance issue from Asus.
9 Y3 Z; }, S- d5 ^- F1109109 CAPTURE NETLIST_ALLEGRO B1: Netlist missing pins when Pack_short property pins connected) x4 q6 u' r3 T# ]
1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerber lines for fillet.
' [9 k/ O4 a' N. T3 `1109647 SIP_LAYOUT DEGASSING Shape degassing command enhancement - control over what layers are counted in even/odd layer sets.
3 w; G9 p! B% M2 N6 \! d- r; f1109926 CONCEPT_HDL CORE viewing a design disables console window
: j3 W- s" C/ t+ @' \/ d1110194 SIP_LAYOUT WIREBOND If OpenGL settings for display of dynamic net names is enabled, should be visible while push/shove wirebonds.
a, s, [# ~% y: ~. O4 H1112357 SIP_LAYOUT WIREBOND wirebond command crashes the application
9 o( l7 \+ a9 [& \1112395 CONCEPT_HDL CORE 縗BASE\G� for global signal is not obeyed after upreving the design to 1650.. |6 u! R+ Q( O B
1112658 CAPTURE PROPERTY_EDITOR Changing Part 縂raphic� value from property Editor Changes Occ refdes values to instance
5 }8 ?6 T; S$ @' g$ n3 w1112662 CAPTURE PROJECT_MANAGER Capture crashes after moving the library file and then doing Edit> Cut
# e0 {+ K' P# ~1113177 PCB_LIBRARIAN CORE Pin Shapes are not getting imported properly
1 Q3 E; `* P8 j- X1113380 ALLEGRO_EDITOR INTERACTIV Change layer to - option for package type .dra is not available in 16.6 release
; {( W Y {6 J; Y( n& \1113656 SIP_LAYOUT WIREBOND Enable Change characteristic to work without unfixing its Tack point.9 } N$ e0 D! }8 L9 P, m [7 w
1113838 SIP_LAYOUT DIE_ABSTRACT_IF probe pins defined in XDA die abstract file are added with wrong location
, @- L7 _1 M1 A8 A% |' c6 w% I5 D1113991 CAPTURE GENERAL Save Project As is not working if destination is a linux machine
3 ]+ U1 }5 z( @( Y1114073 APD DRC_CONSTRAINTS Shape voiding differently if there are Fillets present in the design.
/ r m1 f/ T3 B' P0 G8 D1 B3 q1114241 CAPTURE SCHEMATIC_EDITOR Port not retaining assigned color, when moved on the schematic
( s% k/ T: t8 Z1114442 PSPICE PROBE Getting Internal error - Overflow Convert with marching waveform on
+ z- z0 r, o, A- K [3 d1114630 CONCEPT_HDL ARCHIVER Archcore fails because the project directory on Linux has a space in the name
$ P; e+ m# ]9 u. F8 a: j3 c, x/ C9 d+ S1114689 CONCEPT_HDL CORE Unknown project directive : text_editor7 j3 ^+ A5 Q ]0 Y1 L" s7 V9 c6 P
1114928 F2B PACKAGERXL 縀rror (SPCODD - 5) while Export Physical even after change pin from A<0> to A
: _' v4 Z+ U, z* g# S. p) ~1116886 CONCEPT_HDL CORE Crefer hyperlinks do not work fine when user use double digits partitions for page Border.; k ]( c+ c5 \& l5 x% V3 b& `/ r: R
1118088 ALLEGRO_EDITOR EDIT_ETCH Should Plan accurate and Optimize be removed in 16.6?0 k* v% t ^4 I0 W1 D8 \
1118734 APD EDIT_ETCH Multiline routing with Clines on Null Net cannot route in downward direction
3 a3 [! T# q8 [6 r4 @* M* c" O1118756 ALLEGRO_EDITOR SHAPE Shape clearance parameter oversize values getting applied to Keepouts$ L/ A* n9 K* A& W) [% u
1119606 CONCEPT_HDL MARKERS Filtering two or more words in Filter dialog box
3 c) P! p9 j% R G5 r1119707 CONCEPT_HDL CORE Genview does not use site colors when gen sch from block symbol
2 c' t5 b9 T7 s7 A( S1119711 F2B DESIGNSYNC Design Differences show Net Differences wrongly
" v- m6 \5 [7 R/ `1120659 CAPTURE PROJECT_MANAGER "Save project as" does not support some of Nordic characters.
2 o+ W8 M8 P: ?2 l5 F1120660 CONCEPT_HDL CORE Save hierarchy saves pages for deleted blocks.
5 P/ L0 j9 y8 x1120817 SIP_LAYOUT SYMB_EDIT_APPMOD Rotate Pads commands not working while in the Symbol Edit App. mode
]6 f/ z/ B) W4 T" r; e7 W1120985 PSPICE MODELEDITOR Unable to import attached IBIS model0 X/ I' z- _2 Q/ B
1121171 CONCEPT_HDL CREFER PNN and correct property values not annotated on the Cref flat schematic
; S+ m% p$ L E% s+ t ~1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.# I# i% G/ k5 f" E
1121382 ALLEGRO_EDITOR INTERACTIV Undo command is limited to two for this design) Z& i3 f' I; ^+ o. }' s- d
1121540 F2B PACKAGERXL pxl.chg keeps deleting and adding changes on subsequent packager runs
0 @6 k9 w: `* H1121558 ALLEGRO_EDITOR MODULES Unrouted net and unrouted connection when module is placed of completely routed board file.1 p% ~) k1 p* Q# R' L$ Y$ }
1121585 ALLEGRO_EDITOR OTHER Drill Hole to Shape Same Net Spacing with Dynamic Shapes shows wrong result.
8 b% w$ \* U' Y9 \$ }; M1 O& k1121651 CAPTURE SCHEMATIC_EDITOR "PCB editor select" menu option is missing8 c& k; e8 ?, i
1122136 SIP_LAYOUT PLACEMENT Moving a component results in the components outline going to bottom side of the design.
; o0 u) P# X/ N" z k4 {. v& G1122340 CAPTURE NETLIST_ALLEGRO Cross probe of net within a bus makes Capture to hang.4 u7 ?/ F; ]* H
1122489 CONCEPT_HDL OTHER Save _Hierarchy causing baseline to brd files9 e u& s, C( S1 x0 y& L! F
1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically+ m" Q: N& C5 l& ?0 | q
1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one- | W7 \$ m$ C" ~) z& B
1123150 CONCEPT_HDL CORE property on y axis in symbol view was moved by visibility change to None.
2 W+ S/ U7 p& W. v: l1123176 ALLEGRO_EDITOR UI_FORMS Negative values for pop-up location is not retained with multiple monitors (more than 2); x2 J! j3 G& c: K' R! m+ V
1123815 ALLEGRO_EDITOR GRAPHICS Embedded netname changes to a different netname
( i$ h+ S$ i5 H! O. Q1124369 ALLEGRO_EDITOR INTERACTIV Sliding a shape using iy coordinate does not work indepedent of grid.
9 A2 r5 m" m+ b2 d1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5
( d2 s& ]+ R' b/ d% L1124570 APD IMPORT_DATA When importing Stream adding the option to change the point
# M. d; v2 F3 Q! F- j( r1125201 CONCEPT_HDL CORE Connectivity edits in NEW block not saved( lost) if block is created using block add
5 o) q8 Q4 P! v1125314 ALLEGRO_EDITOR INTERACTIV Enved crash during setting of library paths in user preference+ N. r5 e) O9 h4 _' r6 p& Y- M
1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux% K, B1 }5 I, R7 }
1125628 CONCEPT_HDL CORE Crash on doing save hierarchy
9 f) o& t$ |! @+ Q3 a3 `, E8 S9 {1130555 APD WIREBOND Wirebond Import should connect to pins of the die specified on the UI.
9 j! u ?/ ~8 E9 c7 J1131030 PSPICE ENVIRONMENT Unregistered icon of Simulation setting in taskbar! C- S* T( k# f9 m5 _ F* ^/ w
1131083 ALLEGRO_EDITOR INTERACTIV Bug: 16.6 crash in changing the mode in Find filter window
4 E% L' W4 n- x* {1 {( d4 n; w1 q1131226 ALLEGRO_EDITOR PLACEMENT When Angle is set in design parameters while placement component is rotated but outline is not.& S4 E7 g7 |! r; r
1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.) f( [% ]4 V9 u6 A' o, C I
1131699 PSPICE PROBE Probe window crash on trying to view simulation message* h% B7 g' T, n8 w2 \
1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.) O% `! g4 F+ h
1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.) B e* b5 [* w& }) p* m% H" {
1132698 ALLEGRO_EDITOR EDIT_ETCH Slide Via with Segment option with new Slide command
& t+ _; ^4 Y$ `: ^1132964 ALLEGRO_EDITOR SHAPE Same net "B&B via to shape" errors created when adding shape
3 j# t) `, ` t! c8 \1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top1 c! q1 Y& ^1 k. B
1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.
8 T$ |: J- U9 M& A G& ]2 V1 [1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property
( U* l9 k8 J7 G1135118 ALLEGRO_EDITOR INTERACTIV Mirror and other editing commands are missing for testpoint label text in general edit mode.
7 P5 d; Z9 ^! o) w% r" }9 Y1 H5 `1136420 CAPTURE GENERAL Registration issue when CDSROOT has a space in its path+ L! P* Q% e3 G K0 p1 y
1136808 PSPICE STABILITY Pspice crash marker server has quite unexpectedly
, w2 S! f6 s+ e, ?( u1136840 CAPTURE SCHEMATICS Enh: Alignment of text placed on schematic page
3 K9 n. o+ |0 q# J$ A7 _1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs
: X- e+ I6 r0 N: K/ E# r1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness& j3 K) \6 h! ]7 v
1140819 APD GRAPHICS Bbvia does not retain temp highlight color on all layers when selected.
0 j+ f- t- J. Y1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped
1 B2 e$ V# r5 u* I7 f' x- D1141723 ADW PURGE purge command crashes with an MFC application failure message' G; I6 I* ~. y3 \3 q
1143448 CAPTURE GENERAL About copy & paste to Powerpoint from CIS
* _) ^- t& O3 o# ^5 t1143670 SIP_LAYOUT OTHER Cross Probing between SiP and DEHDL not working in 16.6 release
' k0 R' O" W* N, }: y( ?1143902 ALLEGRO_EDITOR DATABASE when the shape is rotated 45 degrees the void is moved.
0 E: \ s, H7 |5 O- A1144990 PCB_LIBRARIAN CORE PDV expand & collapse vector pins resizes symbol outline to maximum height
% }+ y9 I7 P% a1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed1 K) B# |. Q& Q1 e- e$ s+ ^
1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case' n6 D; w; b! X
1146386 ALLEGRO_EDITOR INTERACTIV Place Replicate Create add Static shape with Fillet shape7 ^* u. l+ ]9 ?( c: ?. `3 A
1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail% ~1 Y/ @9 j* ]2 A" I1 K
1146783 ALLEGRO_EDITOR INTERFACES Highlighted component is missing from exported IPF file.
4 O) j3 D2 }! [4 e; G1 Y! D1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block' P$ G- Y5 _8 d) u
1148337 CAPTURE ANNOTATE Checking "refdes control" is not giving the proper annotation result# V3 k6 p `" p1 i7 A
1148633 SIP_LAYOUT INTERACTIVE Add "%" to the optical shrink option in the co-design die and compose symbol placement forms
& p! a" J! Z9 ?2 [& `: i1149778 CAPTURE SCHEMATICS Rotation of pspice marker before placement is not appropriate$ n5 ^6 B8 ?7 G
1149987 PCB_LIBRARIAN PTF_EDITOR Save As pushing the part name suffix into vendor_part_number value
- m' w/ Y P7 c K! `5 p" V/ F1151748 ALLEGRO_EDITOR OTHER If the pad and cline are the same width don't report a missing Dynamic Fillet.
( f; B4 u, {" \1152206 CONCEPT_HDL CORE ROOM Property value changes when saving another Page2 U, u, I6 L" ]( n7 _1 x0 ?
1152755 CONCEPT_HDL COPY_PROJECT Copy project hangs if library or design name has an underscore! o% y, I+ v; ]5 B+ J
1152769 PSPICE ENCRYPTION Unable to simulate Encrypted Models in 16.6
8 h9 v9 o- C. N/ B/ ?1153308 ALLEGRO_EDITOR DRC_CONSTR Creating Artwork Getting Warning "DRC is out of Date" even when DRC is up to date0 w1 j8 v: V1 \3 c6 j# J' q
1153893 F2B DESIGNVARI 16.6 Variant Editor not supporting - in name( C, w% L, }, M( U
1154185 SIG_INTEGRITY SIGNOISE Signoise didn't do the Rise edge time adjustment.
) o/ j! t: c6 S$ I6 Q+ A1154860 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend$ [2 ~' v% g) R. y* M8 _; P
1155167 ALLEGRO_EDITOR EDIT_ETCH Via structure placed in Create Fanout has incorrect rotation.
6 R* f7 h" J; b7 x4 o1155728 CONCEPT_HDL CORE Unable to uprev packaged 16.3 design in 16.5 due to memory' s) a# S5 n; C1 v- B+ q9 G2 h) c
1155855 SCM SCHGEN A newly user-defined net property is not transferred from SCM to DEHDL in Preserved Mode5 l3 A* c, `8 s( J9 v9 O/ R$ j
1156274 ALLEGRO_EDITOR INTERFACES Exported Step file from Allegro is wrong" X) ]" C8 R, m; X! D3 r1 L
1156316 CONSTRAINT_MGR OTHER Break in functionality while creation of pin-pairs under Xnet in Constraint Manager
7 a& \* b! ?/ k5 B( G1156351 CONCEPT_HDL CONSTRAINT_MGR Loose members in Physical Net Class between DEHDL and Allegro
. a7 m, y p! s: K0 N1156547 ALLEGRO_EDITOR DRC_CONSTR Etch Turn under SMD pin rule check through pin Etch makes confused., K2 g4 Z; |: y. A K$ G& L- b5 _
1156779 CONSTRAINT_MGR OTHER Electrical Cset References in CM not working correctly
: O8 f6 W: j: D3 G1 k1157167 ALLEGRO_EDITOR SKILL axlPolyFromDB with ?line2poly is broken/ B9 u* T; n0 d3 q' ~
1158042 ALLEGRO_EDITOR DFA DFA_DLG writes the dra file name in uppercase.
5 |7 O0 U' _- A) o3 t" |/ n1158718 CONCEPT_HDL CHECKPLUS Customer could not get $PN property values on logical rule of CheckPlus16.6. ^+ l3 x4 h, w+ I- v1 X
1158970 ALLEGRO_EDITOR SCHEM_FTB Changing LOCATION to $LOCATION in DEHDL does not update the .brd file
- C& u' |3 d+ F( x8 T' [5 G2 ^1158989 ALLEGRO_EDITOR INTERFACES pdf_out -l creates a PDF' }- `7 N, y" X
1159285 APD DXF_IF DXF_OUT fails; some figures are not exported% |6 c2 ^- M6 }8 I
1159432 ALLEGRO_EDITOR SHOW_ELEM http:// in the Show Element in 166 do not have HTML link to open the Website; v' w) \/ u" I2 f+ z( `1 T
1159483 PCB_LIBRARIAN SETUP part developer crashing with
: {2 `: A7 E3 S5 N1159516 ALLEGRO_EDITOR EDIT_ETCH Unable to slide cline segment with new slide.4 s/ \: {; C/ s' I7 j8 C( C6 B: h
1159959 ALLEGRO_EDITOR GRAPHICS 3D viewer displays clines arcs incorrectly" d6 G! Z* [- g9 j1 {: Y1 O# x
1160004 SCM UI The RMB->Paste does not insert signal names.
7 R" d3 [) J8 j) t, l& ~' }1160410 ALLEGRO_EDITOR DATABASE Lock databse with View Lock option is misleading9 N0 m6 n* h7 F; E' R
1160529 SCM SCHGEN Schematic generation stopped because the tool was unable to create an appropriate internal symbol structure
- Z) J5 V5 Q8 H7 u: ~7 p1160537 SPIF OTHER Cannot start PCB Router* q! ]/ D) e, v
1161363 ALLEGRO_EDITOR SYMBOL Getting error SPMHGE-73 when trying to mirror symbol
& [+ M8 w& ^! G: @/ Y# ^/ C1161781 CONSTRAINT_MGR CONCEPT_HDL SigXp crash when selecting ECset in design
6 {( P6 W' k5 V( I4 [% y, X, G5 D1161896 ALLEGRO_EDITOR DRAFTING Tolerance value added for Dimensions is not working correctly (HF11-12). V$ _ J( ?% u% H# ~
1162193 SIP_LAYOUT DIE_ABSTRACT_IF shapes in dia file not linked to the die after edit co-design die) o1 g# w0 w( P7 S W G
1162754 APD VIA_STRUCTURE Replace Via Structure command selecting dummy nets.4 z- X' J& ?4 `+ G0 e7 C: n
( X, M' A' J0 ], o
DATE: 06-28-2013 HOTFIX VERSION: 012" _5 I3 h% u6 j
===================================================================================================================================+ q5 q, G' Q7 P
CCRID PRODUCT PRODUCTLEVEL2 TITLE/ y6 T7 I z9 p' c2 S
===================================================================================================================================
, n! k+ n* [/ T% T- U' z& e914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD
& l: k ?6 b; I6 E& _1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files
6 r% ^2 t3 G! c7 Q: T8 f; s1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
?) @) M- d8 i- `1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.6 ? {1 N7 V+ e3 w6 ]) n
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line9 @4 d+ K- H4 R, c) g) u, {
1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.# c2 U) K$ ~1 L- c. W
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.+ h n5 t+ ?# [. X% [ M
1151458 GRE CORE GRE crashes on Plan Spatial5 k! i9 S/ O+ ^: }7 M' W
1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy; H: I0 \* c' ]0 H' M. e. E
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]
0 r6 c" h7 P/ x& X1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design
+ E8 B) \5 Z; b. O0 y* B9 D8 B1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger
) Y' L3 @5 A$ {; Z1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.- L, S' R5 f8 h5 u) F
1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places; B6 B2 s* C% f& m, ]5 u; Y( ?
1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail. f; {2 p7 O: o9 |
1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.
( r/ P9 ]% \' r8 ], `/ J1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer3 a+ v: g( R+ M, i, Q# m% T
2 a# m9 M( ~6 N4 H) W" G3 P3 l; FDATE: 06-14-2013 HOTFIX VERSION: 011
/ K8 ]! ~4 }8 O===================================================================================================================================
( O" s1 o7 N, OCCRID PRODUCT PRODUCTLEVEL2 TITLE% \$ m7 k+ X, b' l: l" ?5 Q$ m
===================================================================================================================================1 |1 ?+ y+ p: T3 d5 J
982306 CONCEPT_HDL OTHER When plotting a PDF publisher output the page coming out half inch bigger in pdf, {5 S) n2 q3 J3 e- K6 D! }
1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers/ o' U: L$ B, k X# S- g6 Z
1093375 ALLEGRO_EDITOR PLACEMENT Align Module with Zero spacing value space the modules further away the modules should be nearer
: |4 s# z: `+ r3 m1103201 RF_PCB FE_IFF_IMPORT Wrong permissions to map file during IFF import
$ u# h7 h* Q- r" M7 u" r1106900 CONCEPT_HDL COMP_BROWSER Component Browser performance utility should honor CPM directives for include and exclude PPT1 e0 t, X* G$ ?1 \( f4 h
1110178 ALLEGRO_EDITOR EDIT_ETCH Line Width Retention should be controlled via setting$ {1 F" A* j- t f
1110323 APD DXF_IF DXF out is offsetting square discrete pads.) ~9 U8 ~) @# i
1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board7 Z9 a% o; k" k9 Q4 u8 C
1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.; `+ x* s# R! q
1139338 ALLEGRO_EDITOR DRC_CONSTR The total etch length does not seem to work for Xnets after setting the variable "retain_electrical_constraints_on_nets"& @/ ]: u6 q8 r+ Y
1139361 ALLEGRO_EDITOR DRAFTING Angular dimension tolerance is incorrect when plus minus tolerances are equal.
O9 S. m! ]9 U: T$ w; x, @1 h8 h0 ?1141882 ALLEGRO_EDITOR EDIT_ETCH Allegro Crashes during diffpair slide
3 n0 p+ z% A- Z0 H' ]! I, P1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero
8 W, i$ {7 K* |/ ~/ N/ u9 x1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP0 B! s+ o3 T* }$ S
1145243 ALLEGRO_EDITOR NC Duplicate drills found in the NC Drill output* @, @7 y& `. D$ @ y3 Y7 a$ s
1145260 SIP_LAYOUT DIE_EDITOR Enable "Copy" in die editor
2 {3 ? P& c" T! T* Q) N7 r1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL
3 x/ @. U% A7 F3 P' ~8 n9 p1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.0 J) t2 X9 g" ]7 h% ^4 K/ ]
1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added$ Y* B; z8 K, }
1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps
9 H3 K; U7 f" ~3 I8 |1146865 ALLEGRO_EDITOR DATABASE Allegro crashes when trying to place mechanical symbol( @+ {' j, d8 H) U: I
1148513 ALLEGRO_EDITOR OTHER Importing a subdrawing file causes incorrect net name assignment., N; u, M; j. j& T4 G
1148734 CONCEPT_HDL OTHER Logical Symbol Text is turned upside down after extracting PDF by Publish PDF" ?( R" v4 J0 `/ p" ], _! `
1149025 ALLEGRO_EDITOR INTERFACES IPC-2581 imports cross-hatched shapes as solid
: M% A7 d- v* \* T) \# D7 \: ~1149948 APD OTHER Stream_out hangs on this design -- hang processing merge of overlapping shapes using poly_deletecolinear_only()
2 k2 G4 J; v# U0 `# x( ?1150274 CONCEPT_HDL CORE Uprev from 16.3 to 16.6 is not preserving RefDes6 I( P* T) ~# N3 h
1151450 SIP_LAYOUT DXF_IF DXF export from CDNSIP missing symbols" z. t: R7 P9 P% a4 ]# G9 s
% r" W: D7 J h$ S; T
DATE: 05-25-2013 HOTFIX VERSION: 010) U" U# M/ x7 e' T i# s* w, F+ O
===================================================================================================================================
- X6 G J7 W0 k% q% z3 \7 v- ~CCRID PRODUCT PRODUCTLEVEL2 TITLE9 @7 d. T$ r$ c8 c- p( |: L+ `
===================================================================================================================================
; y2 O( z; p( @2 r- W% @& O! Y1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer6 P- S3 y+ F3 r: d
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
5 o" `2 h1 Z9 n1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files
- u! v0 e) s8 ~1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
' y3 x! O. ?! ?8 w- i) Q1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6; b" A: |0 O e% R# ^- L6 n" U$ Q
1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border
& Y. E- X8 ~& B- g `0 W4 K$ b! @1131775 ADW LRM LRM error with local libs & TDA
3 i3 r8 w) t0 t) _1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
8 P+ `8 ?0 E: }5 @+ ?4 ^* X1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo$ _4 i; D' K \0 d5 H
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
5 w! a" E# X' u1 d& F4 D" h1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur" S8 x1 q2 J2 B0 s$ A' ~
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
4 a1 k N, P& }1 P1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.4 ~4 q4 o7 ]* @
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
! k8 c1 i7 @, u) o% z1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
a% L. y# ~2 Z& @! E$ y! W1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
- k1 G# U2 k9 @2 h2 C% e1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.9 R: a# c- w- m6 x. ?5 b+ }/ D" o
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash6 K; e7 c$ H4 t$ `" }* V
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF; @& B k: U9 [/ X
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
0 M3 M0 u) o6 q/ g! _1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor! R. k- W7 w% z% J
9 ^: H- X! e6 s7 }' }9 ^5 `9 qDATE: 05-9-2013 HOTFIX VERSION: 009
7 O4 h& |8 G" l6 `. D& F===================================================================================================================================/ e+ d; u# `& ?9 u
CCRID PRODUCT PRODUCTLEVEL2 TITLE/ L! S' P8 ~* u6 o* B5 @
===================================================================================================================================
* `: E U j5 |7 W4 a8 \* f961420 ALLEGRO_EDITOR PLACEMENT Regardless of the aspect ratio for room of side The QuickPlace by room command could be placed comp
# K: ]' f1 O6 |7 L; K/ k1079862 ALLEGRO_EDITOR SKILL Ability to create IPC2581 layer mapping file by Allegro Skill function' z; n! h3 |# z0 C6 O8 {. A
1080734 CONCEPT_HDL CORE Repainting of grid lines during pan or by moving window show as solid white lines instead of gray da
9 e! I% E9 }" X; _5 X+ Q4 E8 Q1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB
2 J. [# E3 q4 W. o1107547 SCM OTHER v15.5.1 tcl/tk code not recognised in 16.6
" _ n) K2 V; T' l1110209 CONCEPT_HDL OTHER We can move symbols and wires off grid despite the site.cpm grid lock' v; ]/ C3 [2 l. z- {3 D
1117825 CONCEPT_HDL OTHER SHOW_CONSOLE_ON_LAUNCH throws an unrecognized directive warning in the schematic editor
M+ H; T3 ^% ?: X/ B1118874 ALLEGRO_EDITOR INTERFACES Oblong pad shapes are not shown with correct orientation after DXF export from Allegro1 }& N; Y+ w1 D9 S4 M
1121873 ALLEGRO_EDITOR INTERFACE_DESIGN Importing Bundles from Net Groups does not allow any further editing.+ O8 Q. E0 C+ }: }, Z0 F- Q1 Z
1122933 CONCEPT_HDL CORE Newly added Toolbars are getting invisible after re-staring Concepthdl6 ]( y7 `$ y, [
1124587 ALLEGRO_EDITOR INTERACTIV The Shape Expansion/Contraction command should also be available in EE mode.
$ |0 v/ t0 B: \" {! v1125895 SIP_LAYOUT LEFDEF_IF Tool crash while moving the slider in the Filter options Macro tab form of the co-design die library manager
1 [( T! ^7 L H F1125962 F2B DESIGNVARI Custom Text in Variant Details dialog box is inconsistent
, s! U, C5 X- d% T/ X1126096 SCM REPORTS Two nets missing in report
$ R2 ]7 N% Q2 a# T. n* \! w1126134 SIG_INTEGRITY GEOMETRY_EXTRACT Attempting to extract topology hangs APD
7 K& W6 Q1 a: E( K% Z3 z1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.
+ y; N2 m! s( |& |1 d" W1130280 ALLEGRO_EDITOR MANUFACT stream_out command in 16.6 seems hard coded to look for a design called stream_out.brd
# w! S+ O) Q$ v) e) [; p1130737 F2B PACKAGERXL Error - pxl.exe has stopped working
. g9 c! u& I" V, A1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters( j7 S: q! o ^3 F7 m$ c
1131764 ALLEGRO_EDITOR EDIT_ETCH Line segment will not slide using the New Slide., {$ T' b) [6 H6 t: z6 C/ }
1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.3 R$ j, \4 u \/ c7 c: \0 H: F/ H
1133311 ALLEGRO_EDITOR SKILL ?origin switch is not working correctly with axlTransformObject while rotating shapes
+ q% K' W! i' V1 [7 Z# Q1133893 SIP_LAYOUT IMPORT_DATA netlist-In Wizard crashes/ r" i6 B2 L3 L6 V+ C% ]
3 A% @9 k% E1 M" B" j: J8 \DATE: 04-26-2013 HOTFIX VERSION: 008
$ [5 `+ k8 Y7 k0 i% W===================================================================================================================================
+ D" e& Z/ i% g- P% w3 d. vCCRID PRODUCT PRODUCTLEVEL2 TITLE8 O1 C4 Q# y2 g7 Y
===================================================================================================================================
" z9 I9 G5 K$ j8 Y% Z; \876711 ALLEGRO_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit
8 S) e) a+ n6 R6 ~# `1080386 CONCEPT_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation4 K `+ x6 `/ i; o
1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device
. Z( k* C3 s7 h1 _& [1 n/ N1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
- ]" \$ b: Q" Z) K1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section; z4 j0 z% ]8 T
1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running1 ], F2 c* m" U4 G8 }
1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.
9 i$ N1 d; c8 L- e+ f( X! r& ~1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence
5 @4 o% u h) D1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.) Q) j2 z; N$ k/ z; k( E
1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason2 b9 ]0 b& s/ ~0 `- o
1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.
; d- [8 [0 t. c" I* v' n3 W1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?! g. m6 J# R$ F; }% `* w- [# c
1120414 ADW LRM TDO Cache design issue7 C6 X- A/ B# \9 c9 x2 t
1121044 SIP_LAYOUT SKILL axlDBAssignNet returns t even when no net name is assigned to via
5 A, r, b; [ i9 f0 N$ v1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups, n4 R9 e$ c0 E# S
1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it' M; h+ Q$ \' O9 r. y
1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.: a( B9 o. _5 R, v* `0 a- u
1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced' |: |( d6 g' m. t+ m
1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.
+ q1 Z1 @% R2 y7 q( b% z1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable
- o2 Q/ K) W. u1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file
9 T7 y+ y, u$ d* n1123816 CAPTURE PART_EDITOR Movement of pin in part editor# x4 G- i+ o2 ?) s) ^/ {, e5 N5 E* z
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50
' E$ Y' m& E2 P' J5 e( c/ \, E: M& \! j
DATE: 04-13-2013 HOTFIX VERSION: 007
( n( P0 q; _4 A0 M6 ^===================================================================================================================================
, R7 z9 v6 i+ n" K. nCCRID PRODUCT PRODUCTLEVEL2 TITLE
1 k: f8 D3 u: O+ ~4 |5 t===================================================================================================================================
- L/ w H! {6 g6 n+ _/ k; d1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die5 [6 ?3 Q! ?, P( f X W& `& h
1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.64 \- |" o, [4 A! G! {
1112295 APD DXF_IF Padstacks� offset Y cannot be caught by DXF.
/ U" ?" q, Y; F1 j1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components1 \5 ^8 S; F$ J! V1 w. X
1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
& a- f2 j% N: p+ }: B1115491 ALLEGRO_EDITOR SKILL telskill freezes command window
; N b% e; V7 P- L& O8 O1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.- T! X `1 [2 u' P2 K4 i2 e/ U
1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.
1 d: p/ o$ Z6 m1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear
: ^+ [9 r" X4 U- K- F7 s. A1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks. f" N6 }6 Z0 Y# W+ k
1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?
0 C$ z/ H6 H; Z* |" F1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh+ U4 N, D/ x5 k1 W. S4 f1 f" @
1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh& [1 M2 `% o% _+ P
1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors
4 c {1 h8 H. x9 ^; [+ c/ w1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6
9 S, I& }' V3 }3 j6 b1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently' X+ P8 l+ s Z! L/ H+ e
1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps
" a! T* i+ h1 f* C7 x. H1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks g, Y. F: s V4 C
1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.: C/ T+ Y. O% }# N& G
, W" Q9 H. F1 S& i5 C# |DATE: 03-29-2013 HOTFIX VERSION: 006$ b! T8 j+ U7 m: t$ [( }' o X# m
===================================================================================================================================! e, t, s8 m& ^7 |
CCRID PRODUCT PRODUCTLEVEL2 TITLE
; S! w+ H: ]; `3 c===================================================================================================================================
9 F* R1 U$ a8 v% d, ]625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.
3 [# ~% G2 w5 Q$ q# a8 l# B642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep1 ~$ t- f8 J1 a" ?1 S" L- y
650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape"., J5 t6 S4 ~+ a6 `1 p; `
653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend/ a$ C0 W$ N8 R1 m8 {8 u
687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect
4 t# }* l1 i$ y787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics" Q; P$ V" u g3 X; q* {3 x
825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other' a; E( V- S3 c& Z- d8 ~
834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming, g& x m" X4 Y0 Z' q/ f: n
835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
1 z' d a. n* t1 B. ?5 M- d868981 SCM SETUP SCM responds slow when trying to browse signal integrity
$ D+ M8 i' @* u! A6 Y0 f# h871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide# T& x! b9 e0 O- ], Q
873917 CONCEPT_HDL CORE Markers dialog is not refreshed$ q8 l0 I& t2 k1 Y/ s
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License/ r/ p$ d3 O- S' E6 ^/ Q
888290 APD DIE_GENERATOR Die Generation Improvement
8 E% q- S+ Q0 _$ v- c892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
& H# t! ~' }2 I5 m902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice+ V% X, Z. K: B
908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM2 E/ B5 w1 Q, `1 C
922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols, h) M; O4 C, F: j7 w1 d
923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences
9 d: R) J8 a3 q4 b! V7 f7 o935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC
8 |6 [. h# j( T* f# b" H# m& ?9 n945393 FSP OTHER group contigous pin support enhancement
) i- m/ R+ X/ P+ Z! H969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database
& e' r" \: E" P1 [1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes1 F+ m3 s1 `6 k6 l! I
1005812 F2B BOM bomhdl fails on bigger SCM Projects
/ _0 e; ?6 e2 s# h8 ]1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture/ C. g. ?- L. Q; c6 S- L7 O
1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names) L# G% S4 m: x6 S4 w
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net" j" l% r I9 G$ \! t
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical/ J$ k' I2 ^6 a4 F' J
1032387 FSP OTHER Pointer to set Mapping file for project based library.
3 S9 p- B7 ~; T2 v# f% x1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with 縋LL PLL_3 does not exist in device instance�$ q- ?1 U# ^3 Y" z. Y
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
7 j7 p1 Y4 a9 p$ S9 c0 ~ d$ |6 f1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding; g) g- n2 y4 h3 s. D; [: x
1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.2 k; Z" f6 I$ `' C; s
1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type0 k7 ^# @4 T: E# m
1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll, y, [* P/ v* a# ]6 @* y, a; t
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation
2 V, L9 q' N/ F. \# |2 Z( q) p6 ~1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects! x5 E7 ], M* {' N8 F
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus) T4 s3 @; W, Q$ G
1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts* p3 w# ?+ D% h8 `1 ~
1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs, b/ n* j( L, k* \4 X
1065636 CONCEPT_HDL OTHER Text not visible in published pdf
8 W+ D9 O2 p' J1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings7 c! g' d* F, B/ r
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary
% l2 B9 u2 v" _2 f1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
1 q$ L, Z9 Q- E1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic
! m+ k4 k& G X1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down6 Z+ t! b0 o+ Q3 K: K. M1 y, t
1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45" ?: G1 C5 y; b T' p2 j) }
1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal* M; k& I6 V0 U3 T0 N
1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
1 g% h* V* k3 L3 R1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.+ k* ]+ M+ z0 X; H
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)
! k, u" u5 G, l+ T7 Y1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die
1 ?1 P! }9 B4 d1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic, R5 U. I8 E. G6 r
1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut
5 }2 m0 P1 \4 g; B( H9 S0 R+ u1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects' t( S) }1 m! ?( x7 e# k+ `! X
1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format6 v' b- }& n) U$ F
1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net j) Z7 M! z7 W, a2 X
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic- c6 o- T, b7 e: L
1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible" I r6 m4 O4 T& ~ Z9 U2 q
1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.0 I3 ?1 f( i3 e6 h4 e* |% J
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.
/ A2 u2 s. h- s5 n$ {: ]1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors
/ G% x" c* \: Y: ~) @$ m j1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.- s$ f5 p1 d3 U
1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition+ a* O9 D1 b( @/ {- ?
1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor, j# R. b" @5 p$ I* b' @ H. R0 @
1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options1 n" `/ V& @$ F" Y4 K+ b. L
1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5
' P0 l1 U+ A& t/ J1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.- D& D$ U, B/ a4 r) `; u3 j
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate2 D% R" {& x/ x+ z5 C) U
1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3
; c2 X7 p+ s. b' A+ ]5 r1078270 SCM UI Physical net is not unique or not valid% S" z9 h$ N7 H% k
1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted; y& t/ g% |: {& e+ Q% @7 ~% n2 R
1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle1 D! q) V" s4 Q [( n* t3 D! v' x3 \
1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs
- B& [6 Z% o% X1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"
f5 @; S2 }7 g% p* k. M9 Q1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters
, ~! t4 v( B/ w1080336 CONCEPT_HDL CORE Backannotation error message ehnancement" V" z8 V8 Y _
1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license
4 u" j6 F# \% [. I [& E' F1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd) b5 N# a1 |' x9 N
1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error& ?9 S7 D* q7 ^& O# D& \
1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.7 z5 f( }5 l* E- \' X+ N* y
1081760 FSP CONFIG_SETTINGS Content of 縁PGA Input/Output Onchip termination� columns resets after update csv command
' K1 c# \! b, o7 h! B1082220 FLOWS OTHER Error SPCOCV-3537 f( D2 q$ u3 g6 ^
1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.! R$ A) [" Y+ `/ x5 b6 w
1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command" i+ ?. z1 Y8 n" E {. [
1082737 CAPTURE GENERAL The 緼rea select� icon shows wrong icon in Capture canvas.
0 R" V1 V4 v t4 A1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name
0 m" e; l/ H R% x7 i1 y. z1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way0 N1 E: b* j) h0 \) K
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher* U3 M" n- i1 w
1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI1 Z+ u3 i: @2 \" V( O, e$ o
1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
' O; O' M j% k3 ?; [+ m7 Y1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.
$ n S# ~: u7 o1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates! r s$ D, c. t2 S/ z$ Z
1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters( U R5 h, e+ P" y2 c4 i, ^
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.
# M* z/ [% x! F6 |1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results# H, e3 [& V l6 M. j+ R, T" s
1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.. Q8 R3 c$ E& P6 [- |4 h, f w; m
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update: u) Y V. q, N6 y1 o
1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO
8 Z* v5 e* r3 Y/ v1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working1 b5 c# K8 _$ P, ^, P2 O
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.
5 h) o) ]' Z! O& D. ~1 I- Y ~3 D% N1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design2 q5 ]$ `+ S3 p/ }6 O
1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated q0 U8 W3 }7 o2 g
1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins8 T3 _4 [( D8 g$ E
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity; {1 n8 d" f0 I7 u8 P
1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.0 w$ n( l9 b; I \& j. f
1087221 CONCEPT_HDL OTHER Part manager could not update any parts.: q$ o8 h' Z, p) L& Q2 D/ z
1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space
0 L6 p' w y" J' u6 L1087295 SIP_LAYOUT EXPORT_DATA Enable "Package Overlay File for IC" for concurrent co-design dies too
! M$ d8 g& {3 s* Y, D2 X% G$ R# E1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice/ K. D5 |( h7 k
1088231 F2B PACKAGERXL Design fails to package in 16.5% N& ~6 N" h5 z% X# L: c
1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.7 u! ~$ G- ]8 g5 n4 }& o
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor
! l+ ~# v8 m# F0 k# J2 t8 n1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager
2 x+ k1 f6 x7 Y1 u8 \' l' w1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?# g# \" `! e' J/ L# `2 E) J. U5 v: C4 O6 Z
1089259 SCM IMPORTS Cannot import block into ASA design
2 q6 E9 Z; |) Q1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form& O1 ^; n7 m0 w& C$ H1 ]
1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project8 B1 _ E; p5 f7 p# ^8 I* @
1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory$ k' h7 v3 u2 J/ l1 _
1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
" C" @/ j: X) F$ r! e5 M1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165
' z) U% _ t: i: z/ N1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message., G' e6 H6 K; A7 \1 m
1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22/ _9 u+ u l1 j/ |
1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.3 ?( @9 w0 v, u( O5 E4 s
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.+ p0 g( T. f; r6 h: e4 y- u
1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled$ i; a! [$ Q3 R0 v
1091359 CAPTURE GENERAL Toolbar Customization missing description+ y% q9 t: k, n2 u! C, n
1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
6 \$ g. m5 o b1 C7 Y4 E1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time
! r. M. R8 S7 z) l& s/ E$ E1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5
/ m/ S* {1 I0 B. ~! U1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design8 u( Z+ v0 C! G! Q( w
1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled
# Y% [; o: S- ~/ p+ b, U' U1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters7 r# n/ d% s, A$ M9 o
1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error+ g; I7 W. ~4 i8 D$ D
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder
2 {+ t! y* d s% e$ N1093327 CONCEPT_HDL OTHER Getting error SPCODD � 369 Unable to load physical part in variant editor
( m9 Y) z' i$ H8 w" L# n5 @1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
' I }* Q$ s/ p" R7 H! e1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time
$ Z' l8 Z& l7 a$ H8 X; X7 {" P$ M1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.
q% J; z5 q" b* c1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?5 A H8 b3 I3 R
1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic
: U1 z5 n5 K' E+ A1 N1 a# a# w8 t1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5/ s0 d2 p1 P: w; x( _
1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet6 S- K* [* r z, K" ~9 t) |) v ?: z
1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die# |+ ?$ n! [/ i
1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block) J3 h9 ^- s4 U! A- P3 @1 g
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3* ^$ A1 e$ \- Z0 l
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results* D- @$ L2 j' I4 x! j$ q
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import
4 @" ]: z2 i3 a: Q1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
7 q0 w$ B4 `' m4 C1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias' q/ P& ?% T( W a2 k3 ~5 ] Y% \
1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate
/ H5 t9 p1 x% Y# Z) A1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors) b# g9 V/ M; P7 d( Y# Q* g
1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL, h* B. k7 T! n h
1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.0 j. u6 I2 e5 E, l
1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side% ?, J l7 a( S
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command# h5 E. E: @& L; D6 e& w! F9 V
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.$ X3 m# s1 @9 g
1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives
8 p, f6 a" L. Z& [5 @1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork8 R# ~, H; V8 Q s# W' ] o- M
1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts( c( l9 B+ c9 i* N
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy1 g; M7 u8 U8 S% R2 X. @5 O
1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.$ a* ^) f+ w" A: F# K
1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties
, h7 [; [; P1 @0 }9 k8 y1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6
' ~% R9 W& C4 f) x1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad( j# a! T3 B; h% ~# f2 ~
1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3' ` u3 o9 S* h5 c1 t
1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad
* i* I r& e6 ^# B1103703 F2B DESIGNSYNC Toolcrash with Design Differences8 A, _ O) B, q$ O6 Z
1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view; O( d; u6 P0 e, V. y& ~& U
1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6
4 }" ^: a$ l# ]+ f7 B$ \1104121 PSPICE AA_OPT 縋arameter Selection� window not showing all the components : on WinXP9 x# b, j+ r" ]$ ~" a9 ?+ ?
1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly
; o |3 |1 ?: B' ~2 Z1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM
) m2 Y- P, a/ B9 E1 `" p" i& }* \1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.3 z S' P" q+ b/ c& I5 b
1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.
7 n5 _# ~" S% T* [6 M1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form
/ {7 F- A. D; q9 _1 k7 R1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part- A0 Z0 B, j, x% r, h% [. \& }5 j
1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked
! E) P6 G; @$ r1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax% g: d2 v+ Y; [
1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6
k+ I V( @& [/ G0 C1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only
; D4 A. h6 Y! j/ d( ^! c/ Y3 r1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid! G. Z( _" B6 ]: h, _0 c
1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.1 v& y2 L% Z4 h- S9 _
1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param X! L9 S" P; @* U8 D
1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish
* c/ k; e( z8 }" ?1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).$ u, d/ \* k4 i! u: \) D l9 u
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke
4 `; [+ c8 \; ?3 i) R. A0 B* N1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.- a& \. F$ \, X2 W: y% e) K
1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode* ~& Z- }$ E; I! \2 @
1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs
' q, s2 Y$ N, S7 b6 l: Y" W+ x1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6) I( k0 H& a: A: K$ p/ [6 W- k
1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.
( z: s. @: w; N0 t* ^& V$ E1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON$ I# ]5 d6 ?! e) @. t3 X8 Z4 T# H( L
1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.63 I @! K4 ]! t( U5 ~7 O
1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset
* x; `8 U6 J' \1 i- e5 y1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters
& l! ?8 G, S/ u! P7 T2 A p1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
* I5 i- r/ P% H. a, x, e1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP
0 H4 r0 t$ d }" \5 o A) q1 Z1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint: v4 L; H+ B" r+ R2 W; X
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan. J- D: F5 p# j! c
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.
1 B* }8 I% J* a1 u7 Z1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file$ I# r- T! d; w4 F
1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6& j) h7 K( f8 l0 C: a( _
* i: I4 u! Y4 n3 Q
DATE: 03-7-2013 HOTFIX VERSION: 0050 i& k! L0 j& b w: k1 H6 R% v
===================================================================================================================================4 l5 R( w. P& I. B4 ^8 y, p
CCRID PRODUCT PRODUCTLEVEL2 TITLE: U: [8 M! ]# C
===================================================================================================================================: l# d' }2 g/ j. f& U, Y( |
1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 1102
& s& s! L A+ E+ D o+ }, v7 ?1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed
- E( Y( _9 P& ]1 O/ G. M1 x! {1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently
. e( F0 _+ b& J, @) h3 Y1 y. }1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind
" b# |6 Y% |2 [* O/ c1 B1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view
9 F6 r$ f# e' X3 k0 [8 n1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed' F" m+ h ]; O( _4 z
1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM
8 G' V) J2 e2 X) @* b. p' G; s( q1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.6
5 c) P4 E9 a |/ w1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement.& J! m# e: a: \9 _4 ~) Z a9 Z& f
1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design
# Y& \5 k$ d+ X) ^/ P7 @& `7 h1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in OrCAD PCB Editor Professional
2 B2 ]7 H. j% P+ K8 f' m. x
" n/ J8 D( J2 ^- q' P; p+ ~9 F8 r6 rDATE: 02-22-2013 HOTFIX VERSION: 004
5 k/ T. w7 ]8 z' f6 [===================================================================================================================================3 O3 ~2 ~) t% \. R; Q R% f
CCRID PRODUCT PRODUCTLEVEL2 TITLE# ?! m- O1 h; A: M
===================================================================================================================================
( l p/ N) A% ], D1 S1081026 ALLEGRO_EDITOR GRAPHICS 3D Viewer do not show the height for the embedded component correctly# H6 b; _( V6 P3 @
1095225 ALLEGRO_EDITOR EDIT_ETCH The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing
+ Q4 s# ]3 V5 _" n% y' R$ _' C/ X0 ^1096356 ALLEGRO_EDITOR DATABASE Cannot Analyze a Matched Group in CM. ~. Z; X, y/ u. l" y
1097481 ALLEGRO_EDITOR INTERACTIV Allow replace padstack command in design partition3 q( B2 r9 \4 }$ [3 P2 g
1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend" z! D: Q3 h- i8 Q5 z
1099958 ALLEGRO_EDITOR PAD_EDITOR Library Drill Report producing an empty report1 H2 W2 r- m$ P5 w
1100401 ALLEGRO_EDITOR OTHER Invalid switch message for "m" for a2dxf command
# D& B* E, [' j* x6 n9 x# M/ f) L, I' d8 w1101026 ALLEGRO_EDITOR OTHER utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit.2 X6 G6 N. G. l2 |+ G+ z
1101064 SIP_LAYOUT SHAPE 'Shape force update creates a rat& ~# R0 }% U3 ~% J" P- p
1102798 SIP_LAYOUT OTHER Stream out puts offset pad in wrong position if pad is mirrored but not rotated.) {( Q5 Z6 X* m+ m$ l& T3 }/ p
" N/ x3 M( I, X5 `0 W7 q) U# C, \0 i4 l
DATE: 02-8-2013 HOTFIX VERSION: 003
8 Y1 ^& d4 G. r5 Z$ y i===================================================================================================================================
$ `2 ~6 \- [5 E0 [# E3 m. e& ^CCRID PRODUCT PRODUCTLEVEL2 TITLE" R. I" M% V4 W3 T
===================================================================================================================================
. J3 w s" U4 R) l5 C5 P1077728 APD EXTRACT Extracta.exe generate the incorrect result
7 q, K! {4 j! J1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF" N& P. R# }) L/ I4 i2 W/ K/ }- Y4 P
1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer- W2 \6 f' e& a$ R& P8 F) `" z) b
1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.$ n3 X. G5 a2 E9 A7 T1 N& H f
1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on
9 c$ x4 ]+ x8 u3 q' w# z! R1 L1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent4 P) ~% ]5 D" U4 I* X, m
1094788 SIP_LAYOUT WIREBOND Wirebond edit move command
' z9 K9 {' r& o: \& k/ F1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor
) n$ |$ H4 t9 P+ i1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn縯 show up after 縎uppress unconnected pads� option.
( S6 i9 C4 H- y& r2 ~0 d1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff
+ D A8 C0 W. |1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible2 ]7 i' T8 A) w& a% _% a o
1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF357 A' g* I# T9 c3 Q
1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.
5 @( D5 s$ n. N, A% G1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.0 V7 Z2 k+ }8 q% j9 o6 ^
1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.* [9 w- M3 w; a5 S4 t4 r* Z0 b
" E. }6 I( d8 Y
DATE: 1-25-2013 HOTFIX VERSION: 002
- Y) k+ B* v. K===================================================================================================================================& }$ r4 h! T5 w
CCRID PRODUCT PRODUCTLEVEL2 TITLE
: Q8 E' w8 _7 Z===================================================================================================================================
) b2 u* x7 W$ d+ e+ [1 S491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute% N: e1 \: A6 B. w1 F/ a0 I
863928 ALLEGRO_EDITOR INTERACTIV Segment over void higlights false "nets with arc"
* N: C7 D) g: D& Z4 v, A6 i% O1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes' ^- |% o& P; n0 j6 {, ?$ l
1074820 ALLEGRO_EDITOR GRAPHICS losing infinite cursor tracking after selecting the add text command with opengl enable3 S$ T7 B0 T+ R$ J' {+ {
1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33
" `6 C7 [8 W( }4 y/ s1076986 APD WIREBOND Wirebond Adjust Min DRC does not maintain the finger position in the same sequence+ B+ {+ F* N0 c7 c$ s
1078031 SIG_INTEGRITY REPORTS Requesting improvement to progress indicator for report generator6 D' \: \" i- ^2 U2 e1 K
1080213 SIP_LAYOUT WIREBOND Wrong behavior of Redistribute Fingers Command
. @: c9 m) Z1 ^1080667 ALLEGRO_EDITOR GRAPHICS Allegro lines with fonts not displayed correctly in 16.69 i. Q) _1 s& ^/ j* V
1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note.
; ~: w2 B. a2 _9 M s; y1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete. T9 I3 v8 u! u$ d+ y4 n
1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL./ M5 B' x y# y) |7 o0 l
1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0* n, J# a/ o2 h* d. K
1082595 ALLEGRO_EDITOR COLOR Infinite cursor remains white even we change background to white
0 a8 F7 a! `% t8 V1082704 ALLEGRO_EDITOR GRAPHICS infinite cursor disappears when using Display>Measure
! u' e, N5 n6 V2 P8 e( A! U1082715 SIG_EXPLORER INTERACTIV Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer
) \) ~- m5 d- m# v5 ~1 B6 X1082774 ALLEGRO_EDITOR TECHFILE Import techfile command terminates abnormally when importing a generic techfile.
: w7 V4 I r' C1 _4 k1082820 CONSTRAINT_MGR UI_FORMS The configure generic cross-section pull downs do not work.: _) o; x( f- f+ z" f% m V& r9 J& O
1083133 SIP_LAYOUT INTERACTIVE SiP will crash when using the beta Pad Rename command to change a BGA pads name.3 _6 C) i7 }! m
1083158 ALLEGRO_EDITOR GRAPHICS The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.6
2 ]" d! i* C6 H- H1 d1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout9 e2 t5 Q4 M" N7 Y. ~
1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file3 |6 q* ~% P2 x& O
1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing.4 Y' r' M, P- n
1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.; @; i, _$ H" |0 Z7 e' V
1084166 SIP_LAYOUT DIE_ABSTRACT_IF Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties
! I9 `! e, d! ?* }0 Y1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error+ C3 b, Z/ h; P( v0 f
1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric
$ b" s3 K' e8 w9 [! {9 t1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol.
2 E! x' n5 H5 c. ~1 x- a1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue/ M% q" {: G0 U2 N9 m
1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command
) ^4 P% _5 x6 J% A1085139 ALLEGRO_EDITOR GRAPHICS Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled
2 W0 N6 h" U+ k" {' Q6 n1085187 SIP_LAYOUT INTERFACE_PLANNE netrev with overwrite constraints fatal error/ e" n; N1 d# a3 y- t7 s3 A) M
1086402 ALLEGRO_EDITOR GRAPHICS Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled.+ ~& {6 ]4 m" T$ T' X* L
1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function; W0 L7 ^3 O3 c, [, h
1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command.1 B5 y2 Y" S2 B C/ r
1088412 SCM CONCEPT_IMPORT why reimport block adds _1 to the netnames?
/ {5 c0 D( c2 C3 p1088958 CONSTRAINT_MGR INTERACTIV annot create Differential Pairs out of nets that belongs to a Net Group
3 P. |! s% U9 f T( l1089336 ALLEGRO_EDITOR GRAPHICS infinite cursor and pcb_cursor_angle
) k$ f" a, Z6 y0 v0 k( e1090689 ADW LRM LRM: Unable to select any Row regardless of Status/ ]8 F# g6 |5 ~: c! p) Z6 X
1090955 ALLEGRO_EDITOR OTHER Cancel command crashes PCB Editor when add rectangle
% F/ B! \+ i2 s* x2 X1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas.
$ F. ~# h( T4 m5 h1091218 ADW LRM LRM is not worked for the block design of included project
0 v2 q+ Y* B- q& ?8 y1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads! ]# |+ t: q V% d9 C# M6 b+ z
1091706 ALLEGRO_EDITOR EDIT_ETCH Allegro crash while routing after setting variable acon_no_impedance_width
+ B) f6 N& N' ~6 c Z1092916 CAPTURE OTHER Capture crash
8 W0 p' e: Y* w1093573 ALLEGRO_EDITOR DATABASE team design opening workflow manager crashes allegro. possibly corrupt database( u+ R3 f3 p8 ]( @* d
' Y) k7 Q6 n3 ^3 hDATE: 12-18-2012 HOTFIX VERSION: 001
3 D9 t6 C; ~0 W' j7 G, e. H===================================================================================================================================* b2 ^0 D* v- \
CCRID PRODUCT PRODUCTLEVEL2 TITLE
V+ _$ L6 K2 ~- d===================================================================================================================================
$ y7 Q5 |& I$ I1 K2 I7 |) t# h501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap
( v; _0 `/ S. A) T745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched* O5 V. O; ~. Q" H; @" r7 c
825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted
5 O' c5 ], \6 x M& s4 x( P/ f, I871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash
1 }6 P @" R' h& |3 p891439 ALLEGRO_EDITOR INTERACTIV moving cline segments: m3 F, E7 F" M" T2 u, y' J2 ]5 g* c
898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore$ K( d2 O- u% x, N; p
923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties
$ v( Z3 A# R, F: I1 \& L: k( O938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic7 W& ~0 M3 z0 d: _9 |+ C
947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.3 X3 d w1 Q5 r' Z( x) M
968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
5 e, K0 g$ b4 q. F976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
+ o- w$ e4 e0 l0 z2 l2 I981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.- C( z: Y# {6 J+ y6 h
982273 SCM OTHER Package radio button is grayed out# n/ r! c1 Q" O% w
988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command
1 V! U% i. Y, p+ j9 W989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode' v" _& l/ p' W! Z7 b: T
993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).) z/ D4 Z# i" x! f: J+ q
996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections
4 z* T+ m" r1 R# d7 V997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
) c6 {4 p5 z) K1 { R; z1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model' r4 j% B/ t4 S+ C! v& v
1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs$ D: Q O3 {, u- A8 L( _
1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg
$ p+ _1 \5 V& l1 O2 X# W: ?0 L4 p& |1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.% F. T" f o+ v1 \$ ?' P# D1 n. a
1016859 SCM REPORTS dsreportgen exits with %errorlevel%
/ U0 Y- k7 z+ n' X1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin$ }4 ^* i$ ?' u( e y
1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs
/ c5 ?/ d4 \2 Q' @" m$ j8 X1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts! b7 k7 O" T; {- W. l
1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140$ S. Q" r# x" N! A& @6 q4 N1 ~
1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.; P* U/ [* B2 b7 Q1 x L, ]' @2 g
1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button& G. d' J- B2 k* a, G, |0 n9 N- M1 Y
1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out
/ y# i, d& H! O' t& p% B1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist
' k1 G( U5 v |+ w! t- o& n$ b7 Z1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed
5 h9 C' M3 b# m Y1 q- D- x( p4 W1035624 CONCEPT_HDL CORE Options pre-selected when launching base product
/ K1 i: }* W7 j8 q1 `. `; T1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly) |1 R- h1 r% Q- y: e
1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it., j) s( ~. s' F+ c9 [
1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)8 E* C! e( Z7 j. T
1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol1 `# v; I/ F, Q6 B5 H0 K
1038285 SCM UI Restore the option to launch DE-HDL after schgen.: K" x; z9 r3 o v0 O, j& }
1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."
* {9 z% ^' O F4 x1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro
2 F* E4 e# n+ `' L8 M$ p$ p5 l3 @1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected5 G, o" Y4 W( i; M% E4 w
1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing
5 |7 Q, D2 u0 ^3 H: z1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found." H6 Z* s" ^ b
1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.
, I/ _1 h, H( o4 H9 l% M1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu
2 {* u3 f9 A$ U1 v; R1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.$ @" {/ P$ h! z% X, K1 u+ J8 W
1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow
5 H# `, I. _" F3 e( M0 a1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory
% u: j! O) q( V* u) C1043903 GRE GLOBAL This design crashes during planning phases in GRE.
5 z1 d( J& X4 c1044029 PSPICE ENCRYPTION Encrypted lib not working for attached' P* t$ M; c3 k" n/ Z& ~! L9 F. u
1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory
" O* S! V1 I+ G: R0 f& G. u3 \1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.) ]5 q4 G' l* h" r6 j1 a
1044577 GRE CORE Plan > Topological either crashes or hangs GRE# r* W% g, Y% w) j
1044687 TDA CORE tda does not get launched if java is not installed
3 L4 R: M( i# `2 O( y( O* b1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die
0 O( l( e: r, ]* ]1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.
' \% K G! g* U) n, u1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board? t% Z! n$ o$ B2 a5 |8 {6 I
1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.
- v) ]) b6 }4 F( q8 F1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.
% ^) j g# W" u, g1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow
( c0 E+ p9 B* S, H$ g8 C1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.
6 e- E. k1 d& H- w$ H, v) z1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill
" ~+ c6 V& \$ R. B& x1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.
' v$ ?9 o$ @ {) G( v- _1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5# w2 [1 u8 g7 k, p& Z! e7 \
1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5
. f& D# c5 t+ q1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value
4 y @" p! c3 H1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version7 L$ ]! W* `8 [$ h" V! d/ ~
1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn縯.$ i" ]0 b7 H7 F
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.
$ m: I9 ]6 Y7 S- R, [+ S1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.% a5 I: d! S1 ^) L! k
1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes8 H/ R, ~4 j0 v
1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
$ t1 m. ^! d2 [' Z6 ?: y1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.35 f% D; e4 m: H3 ?3 U4 U6 X2 ^/ m
1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file2 g B' ~' _+ e4 e3 f
1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors
% a( D+ v. @2 n' D# p+ S1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.
0 ^0 E7 O! o9 C' k; D* d1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.9 \0 t' ^- F& ~
1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design
& f& i5 N. G" [0 Z9 {1 s; v1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs
/ ?! t- f0 `/ Q! G1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label
8 Y2 Z" H9 J l# C, u% X1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.1 b+ N0 k; f7 f+ e, T
1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy0 }1 \9 B9 |/ A( d! a# P) m
1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down" a2 ^- l4 {# @. |9 ~
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection
( N3 M# K3 F3 {! G% h1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.7 g( Y7 e/ @4 n
1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views0 U; \9 X5 {$ F" l
1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline
9 E1 Y2 ?$ T* j9 Z) k8 q1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.
- N$ q$ A, B* |7 l; O. B/ L! ?1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created.* O0 j1 F& y$ G
1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move
, [7 p3 e: T: O; A% [- h1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value& \$ B* m' s1 R4 R0 _
1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer9 y1 p" y* h9 S7 g# R( v
1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report3 Y1 ?! C( h7 {" o
1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.
; |8 @: U5 c5 D1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete
1 B! y( D3 n5 D0 F1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
. C# ~1 T- I, z1 E- ~+ }5 ^; W" a6 x1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets
, I4 M+ I1 J; N. a! N1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?: U% z$ P( `9 K$ Q
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values. U7 y2 Z( A$ {) W1 s
1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished.
$ g% c0 z: L$ t1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00
" G# O; z0 Y5 _& P1 b7 H1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
+ X Y" K- D; U% b0 i1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed.
3 z. C9 H! K z2 I1063284 PCB_LIBRARIAN OTHER PDV Save As is broken
. E% U8 U2 ~) g1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs
( ]8 _* W: @9 q1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.
, N+ Y9 ^7 X5 @+ P9 |* C4 L1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.
( X8 t% h, C/ [; z1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design! l( Q# K0 m- ?: f J3 V
1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV$ F8 o/ d1 @" o9 @% L) d
1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green.* V, a; s; k: K" n. h
1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X0 |7 r; A* r# ?1 r* n! U, O
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application4 @/ w2 v* t7 b1 o# k
1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report
) s3 Q, D" y5 d; h. g1 p1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
7 W/ S; K/ }7 ~4 m: ?1 M) w1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic: X, y1 S$ O4 g3 S' x @
1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.
# |; e/ q/ g3 F1 j( s& |1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file& z% K( s1 J; f
1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command* D" O o: o6 a4 j. W
1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended
# `( ?+ E4 ^% t9 A, \1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067
d! b; v# R* N( c7 [' X7 d! U; w |4 A8 {1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design) O4 b2 ?; S7 d1 I& x; X
1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify
1 `' ~8 l( A- @1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids
* J, A5 e' X5 s4 U: x3 Z1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes h& n7 M$ b5 v
1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow
$ I$ t; Q+ F- x- m$ U7 F# _1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal
& a! x9 p5 D/ l1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.: @ j2 d2 S- {( e" A. a
1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.64 f7 m; \$ e6 {4 k1 w& g- [9 p; a
1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5
$ J4 V. m4 [0 f3 n0 o1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode.2 u, Q7 F, R: R9 y3 F8 L1 r
1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
5 c1 E, i' f6 `8 X' j* V3 ]1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor& o' \6 D W, p, I) k
1073464 SCM SCHGEN Schgen never completes.3 |$ I4 B) h( ~
1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory
. ?- U7 @( L7 @3 I1073745 CONCEPT_HDL CORE Import design fails% P) F/ S8 ~/ k! s1 Y: e; K- ?
1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'
: }9 y. C+ H' j: V1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE
) l' D! ?1 ~7 _1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist* ?* z6 h3 F. \4 o
1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter6 r+ @- W, V& e4 R; k
1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
! B) w2 J! V1 `1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.
1 |& z+ l9 U5 ]; N: i- c/ k1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI6 ]3 j9 \6 B9 ~2 m* F) Q
1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block% I: R! s- n& R! p/ Y8 n
1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer3 q8 |: R8 _6 _# |' Y* P- I3 ~% `
1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces* L" [1 P4 D% u- C
1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2
/ K0 }) P1 y ]) M# Z- w+ ^* @1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix4 B0 U5 }/ |1 T8 q: D$ b
1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
4 G. E2 j2 X% N1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top
) `. \$ T3 \' k: Y6 S+ }1 O; n1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas. j E- \' J8 V. K' I
1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value9 T' J! ]8 X# d% b
1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.66 o4 T6 ?4 @ ]7 U& ^$ k0 o( U2 d
1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey: L4 Z: I+ l$ I, u
1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database
) ~" E* v) ^4 l- ~/ F1 z1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset
* r% F2 n1 X0 E1077169 APD SHAPE Shape > Check is producing bogus results.
+ G5 I" k. b& I) c# o1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board.: @; X+ U: b" c, X
1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim* ?" {! f* i! q# \7 x# V
1078380 SCM OTHER Custom template works in Windows but not Linux1 m* u: B, \' z! k g# u; O! V
1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.! w1 K% N$ M- ]- | @! `
1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide
2 o# S! E7 U) v( Z [1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping! }- z3 N! X& W- T$ l
1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"7 T& q( P/ t$ ~: o+ x5 w! @5 K
1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text
1 N K# Q3 I) f0 x. }" ^1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control
' [% m! k7 G( z, I2 q8 k1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical.
) t: a/ S- k( v" `. ?0 e6 e1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.! o, k$ a: F! z
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发表于 2014-7-31 09:06
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