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本帖最后由 dsws 于 2014-4-28 12:56 编辑 7 q0 r& u2 h5 m( z
1 q/ Z1 A8 R* r; o链接: http://pan.baidu.com/s/1dD9XLPB 密码: ujuq( Q1 K$ S. a# u6 Y( Y2 s
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c2 J! i; W; p8 h# n. V) f0 M: | |DATE: 04-25-2014 HOTFIX VERSION: 027
! `; X& F) L# t3 X' C9 G===================================================================================================================================
% O" H3 ^* z; m/ b+ i3 f$ f1 g- RCCRID PRODUCT PRODUCTLEVEL2 TITLE
/ @# p6 X' e$ n) F===================================================================================================================================3 J% J+ Q* g6 p( O6 [% f9 o
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM4 |* B- o0 z. Q: d: Z7 Y
481674 allegro_EDITOR pads_IN No board file saved from PADS_in( ~+ s/ i: A1 l) \" G, x0 e
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
' t, X6 q- Z0 v7 M9 }1012783 FSP OTHER Need Undo Command in FSP5 y. {6 @( D Y3 [" ^
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.' Y0 M3 d. b' d, M
1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
2 \5 _% n" C1 n1073231 concept_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
* V8 D- ~% R* J1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups% e0 Q4 b: b( E' ]! l
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash8 D. _. ]$ q) [& V
1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command7 E* u! O4 @9 s7 A0 [) I6 j0 G# ~4 L
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
7 g+ k* l+ g7 f8 x1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present& _5 Q5 X- w" c" a* u
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
( M3 H9 q. M* s) ^1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings
$ D& V3 t9 z% U$ t: |3 I8 D1 K+ z1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
. Q# R) e# X# l* B6 \& o. j1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
" W$ s% `3 i7 }; f: C7 G" l6 \1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
3 q" Y4 `, O1 C# j" J. T h1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates0 @5 F- ~* Y% i' y" }1 P& M- ~
1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime# H3 x+ s( O( A' v& r6 \/ \
1208478 Pspice PROBE Attached project gives overflow error with marching ON.
# U) p* I8 J4 {1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol
; d _0 Q; S& G1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed' C; _% C! ~- f
1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
( i! s' l" K, n$ K5 }% L1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers" v8 A& ~# ~9 n" ~
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?/ k) l4 Q9 p" C8 Y& l. T
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.3 Y7 h3 v3 p: r- d- I0 j5 n3 Z
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values3 W; R) ]$ H- ~8 \* o J# x" Q
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging! ^7 P+ G$ M- s
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
0 Q& ^+ S( ?' J4 c3 ^% S1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added
# @4 C/ }& U8 a9 Z% W1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.5 `& a$ c ~( k; o
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
* P, l5 b ?" [: f: C5 H8 N1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux2 I5 H# o+ W& { ]1 x! X7 u8 V
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
; a; h3 }0 c, ]/ C5 ^$ h1221182 ADW TDA Team Design with SAMBA0 k/ i; c( T2 S- N- {, P
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair2 E( E0 F- d. ~3 m* G; [! T
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened. }! d, N3 }2 `
1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?/ g( {7 m+ Q# i" {
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
) A; i i* F8 T1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
4 k* ~2 t& I0 v% w& V+ X7 Y/ g1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
5 a: }+ ?6 y2 G. g' g& o/ N1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor r' e% ~+ N1 m0 f3 e
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.
. D: S8 x: y! O* L$ G0 R& j1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path, Y: u5 l" K6 g* V2 D2 Z( N) b) W
1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin
8 ?. ]* Z8 l: d$ c( g' H1 [1225494 CAPTURE DRC Different DRC results for Entire design and selection2 z ]+ e9 I! O! ?; Q _/ n8 T
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property9 b9 O$ `! |( N, i! q1 n; r
1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
- n# p5 L3 v; q) d- t1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
, y9 P" K3 z. {5 N- W1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal+ c/ ^; f/ j ?# L$ W
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file1 W$ q3 o$ [' P! W9 O: o
1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors4 m8 w- |3 B |; P
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
7 k# R! c3 s% j# v1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration0 B- z( F; J6 s4 _8 `5 u1 |. k
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part
5 F6 \! j* e; C' p7 O1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case. L# O5 y* z$ s7 H" p3 b- \) v
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins
! { B) F# A4 A: t- ^1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection) B/ D. h! v( ^. @& _
1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time." M( f b d ], D6 g" G8 y
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
# z5 r/ V- T( o7 ~! O h' R, n, G1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).4 V$ _7 I- G4 M6 y
1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM& @; B& i% d! r
1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
% U, S' c# s% k; W1230432 CONCEPT_HDL CORE No Description information in BOM
0 T& c9 d( C. |. ^! y" w7 ~$ c1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes) }( D- t; R, i( S8 ^& `* x, n1 T
1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files: c# N- Q q0 C" x0 ^
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands; r8 u: R1 e* V! b
1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets8 j# S# |" R5 {$ ~' K
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
! p0 B- D; {7 J+ z, t# _1232100 CONCEPT_HDL skill Unable to execute the SKILL commands in viewer mode
, E) x$ c( U+ Y" `1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical% L a) ?3 B3 A7 |' R
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode
( M3 i. ]0 x' I/ c' W& y4 p3 X1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files
5 c% ]/ }& X1 D8 B1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy
- r8 U! |; D; X- M3 z# N" b1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved: X" ^/ X5 m# o8 k9 F/ ]8 W
1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect
- j5 x3 }2 V3 n; D3 b: G9 L1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set% U8 m: B) W" F& B
1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
, C- m# w) S+ t& i/ t" ?6 W1236161 CONCEPT_HDL CORE Import Design shows the current project pages7 q* ~2 X( g$ ~* \: f, q; [/ {4 \
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.
% \0 P4 c. Y6 M" O0 o1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
: {! {" \7 P; Z" z9 h5 W. v' k1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file
/ W; U C* J# k# l- f6 e1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape
. _! u$ A, o( K9 w V# q% F7 }1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming
" R7 D" x& F' K, Q1 J& E: |; C1236781 F2B PACKAGERXL Export Physical produces empty files
* Q; p9 B$ D' M4 r0 n7 D7 d) J& `0 M1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
) \ F4 V: C4 k8 |1 N$ @9 w% f1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
7 w0 E- a3 I- a/ V1 B+ o0 U( G1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition: x) t# M/ `( Q) J: C
1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
9 L* u- _. v/ _4 _ y8 Y9 M1238852 CAPTURE GENERAL signal list not updated for buses( ?4 h: N, p: m2 n+ \3 k
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes' d( f2 r6 c% e. T, ^! ~# N
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
' H+ [5 h) y. V5 \1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE. i% S3 D F# u6 W
1239763 PSPICE PROBE Cannot modify text label if right y axis is active1 r: ~4 G) Z" r: I* ~* X! T) W
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images
$ x* x5 c+ N( r( x1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
* s( S7 o- G0 T; _4 ^1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
- X% L/ R6 i4 u3 z: x1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file
9 Q$ N7 R' Q% H9 Y7 u4 @% _1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable6 T7 X6 b! \6 H* T ~5 s& d% M, u9 u
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy
1 Z9 k8 o( ]0 T3 |1 }4 [1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms8 e W2 |# K% B( t( F4 Y5 i! J1 H7 ]1 ^
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working
' t! u0 z% F! Q" D$ D1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
" w& X* s1 k" t/ _4 ]; n6 {1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard4 K1 N( I7 `# r9 t
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
! K/ Z# e' J1 R" a1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side: z3 _$ M& g' ~7 f! A9 F9 E
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer7 U, t+ T' L z4 Z* e" V( s
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results. I5 S( |1 {( u6 V
1243609 CONCEPT_HDL CORE autoprop for occurrence properties" d6 M8 U" H, h2 A2 e6 b1 T
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI8 [0 f$ f+ T: V
1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
7 o0 ]" Z8 _: N1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
( v9 b: ?& E& |" q1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
. J: ]" d: F5 p! n" X" e1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is& ^5 i4 S) Y- H" E. n+ [" m* c
1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design2 X+ d% d- m- ^' H
1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?+ ~/ S* M: x/ [) I
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
A9 T/ K/ ]+ ]7 h$ O1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters3 s3 W$ D1 Y1 }% Z, w8 J
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown) f. R8 j& N; F5 B
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
, w& ^2 h0 z9 u& v( \7 k1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL s# y% l; l7 Z+ ^5 S- E
1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained
; f+ y" ?1 X8 e b r1247462 CONCEPT_HDL CORE Text issue while moving with bounding box+ |0 k$ d- c+ ]3 k* X& h% a0 P
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered
# `* E0 j9 @& D" j" T2 U+ m1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
3 ^6 R- {$ D$ a+ {, y1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts5 l# t+ c2 k* o" c8 S( H; X7 e
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.7 y1 w8 O% i* Y& M. ~( E- \
1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
0 e3 [4 ?& E9 I1 h6 l _& R; w1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly
( n& g4 p! E3 F5 `9 D6 C& [1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.2 G& S/ s L W+ V
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
% M! I( O3 V) D" {$ k1253424 SCM SCHGEN Export Schematics Crashes System Architect
% s/ W n" Y8 |0 a3 _" C2 o4 M1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled
n0 {: K" J- d7 A' L6 M1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing$ p) D& ^; v7 M% R
1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
7 G( R1 U% h* a. C$ Q8 T1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error$ x% E d3 F' J6 V8 Y
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
( R' r+ x* C$ @1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation8 b9 o& R5 i/ W" j) J: x2 Y! Q1 a
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects
* R( J2 `/ `8 u) l1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
9 [; \7 q0 v& ?# p2 W, l6 l1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
/ V* W0 O9 l& ]7 S3 r. k% r1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
y' D# c L( |' R0 g1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
. H) A _9 T+ Q' n1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design; P' I) ]4 L# I5 w
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library( U# e8 |7 e( B, y- Z) C( p
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long+ b& S+ l/ m5 ~) B$ t6 ]
1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash
+ F& d! N- t" E: r( A1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
+ p* X8 {* a" r) ^1258029 APD WIREBOND The bondwire lost after import the wire information" I% [1 R3 A' [, W! o
1258979 APD NC NC Drill: There is difference of number of drills.- ]8 [6 s. T# W5 M( B( A* } n
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement; s+ ]1 f. Y5 M! V
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.! e1 L7 r% S( M2 b1 b3 ~: C( h" E7 ^
1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"& A0 O0 O J; t/ M
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines
C/ z$ C) E" \* j0 T3 s$ u8 _4 y1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void4 [& L2 \+ f5 w, `
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss( A* w+ x m" P2 C$ f9 D
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发表于 2014-4-26 15:14
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