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本帖最后由 dsws 于 2014-4-28 12:56 编辑 9 W5 w7 q$ }0 w A; C
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链接: http://pan.baidu.com/s/1dD9XLPB 密码: ujuq
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9 S& R/ r, X7 N6 D$ t. ADATE: 04-25-2014 HOTFIX VERSION: 027
6 U# g" a! k) D8 s1 |===================================================================================================================================5 ?: J3 u. e# S
CCRID PRODUCT PRODUCTLEVEL2 TITLE% A2 D6 i+ ~4 ^
===================================================================================================================================
8 o) z# X [7 A308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM9 E- _$ v; W* I5 }
481674 allegro_EDITOR pads_IN No board file saved from PADS_in" k0 H x9 D, P4 J
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
3 P; o- \; @( W( U! ^; w4 X1012783 FSP OTHER Need Undo Command in FSP! E: W5 P! Q% q, k- @
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.9 O- b, m% P" v4 u2 s
1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved0 y( ^) I' x# u% c( o
1073231 concept_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
Q" v6 }) K4 t1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups2 z' ^" Z$ [( @' Q! @' O+ a. e+ \
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash" S" A. e: q( v5 O- ?1 ^
1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
- Z5 x* K! k4 H; V o1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode* j' b/ K) w( k/ A+ l9 [1 p
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
; y6 f& [4 O4 d1 {' a9 j1 H* B& [1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.0 S7 Z# w: `9 e* `
1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings
( v3 z7 L" H! o2 n& ?1 u5 G1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
9 k7 ]- I, h+ W" m8 m1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
- l6 h0 h2 L5 @. m9 z1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part." u' ]2 \# ?- @* G/ P2 ~: P
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
$ o" w' I% E4 X1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime3 d7 w% o8 _+ Q
1208478 Pspice PROBE Attached project gives overflow error with marching ON.
- j+ W7 \) `3 r" I/ q0 ^& X) c1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol0 ?- u0 B. y2 D, k
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed- c8 [5 x- j- X9 X' W* y7 c% M
1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape% j8 a; m$ s Q' U7 F( x& Z$ }
1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers
6 Y% ~( N, d! J9 z# O1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?7 N K% R' Z+ C) J" T
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.8 ~" @$ S; f/ `: L& ?* @
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values
U7 z* W5 F/ F9 Y! P1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging r% Z4 Z/ ~0 _% M5 K
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information9 D8 T5 ?4 O1 r3 u; L, D9 b9 g
1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added
) R& z% ?% }- U( Z9 x' ?- |& b1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
& H# D; {8 B& x' F9 t; F/ C+ ~$ d2 k1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes' `) j6 S4 F8 _0 G Z* p
1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux
: u. i5 S* a' `2 Y# ]1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.2 m" Z- s9 l- X$ s
1221182 ADW TDA Team Design with SAMBA+ r% ?4 x* u: n. u9 w, L; ]6 ]
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
& }8 w1 o2 c. n5 n4 t0 J1 ~% }8 L1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
" d: \5 m/ ? G* R& Y1 \1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
$ Y: Q6 t. x2 D1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
2 g9 B0 c( ]6 v, i7 B1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
" W$ f- z1 M0 v" S1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.. K* G: a" d/ t) H+ L( [5 E
1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor
. O( S5 [$ F7 ^; I* R1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.
( f. K3 l F8 u G: P1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
9 b$ k& K+ j( c5 [& P, m" H1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin) I Q" R3 `+ [( v9 G- R& p( @
1225494 CAPTURE DRC Different DRC results for Entire design and selection
& \! a! B: b+ ?1 F1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property8 w6 J" W5 M7 T/ k" H* A0 u
1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
, C. u) ^3 _5 ~1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet9 s% V3 e5 s9 a8 `! [! O
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal0 {7 l7 C; w/ ~( @5 _5 x
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file) U8 s. b1 s2 K/ S, z1 P- f) t9 T) y
1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
0 R/ v1 F* A, O9 _$ u8 B7 N6 z3 ]1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
; t) }. q W# O+ R4 Y0 D6 w1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration
9 O* N, p: K/ C7 U2 c1 f1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part8 i& v9 N5 Q- S+ k
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case
- H' x l7 A$ k& C; _0 s1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins, e; C7 B7 Z9 R% L0 q
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
$ {/ J2 G% W4 q2 f1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.! q2 u/ R9 F; ~6 w- N/ S
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
+ |, Q" p% I# _+ k( Q/ D1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug). g9 |, f, [2 ]' D! C
1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM q P& S& I6 G* R
1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
& a+ \ E, U. W7 Y1230432 CONCEPT_HDL CORE No Description information in BOM8 @1 m/ O) }- E6 N: e2 x0 ^
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
|% b) P8 [1 [; ]3 Z3 u1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files
" `/ I6 o$ b& K4 {0 k) c; O1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands9 Y% m5 N/ V6 c/ p9 j1 ]- a
1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets
" t6 M2 M( @% H1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.9 I" _) F' Y! J/ M4 c
1232100 CONCEPT_HDL skill Unable to execute the SKILL commands in viewer mode. o9 {: {* x. R* M( \
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical7 q/ l7 A z5 `) B. L' g
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode" f+ l0 f% ^, G3 I
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files
0 `6 T: m7 A5 W) E% G1 G: }# q' x1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy
, v' m8 C. |# w1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved/ D6 c8 |8 b& ^, l
1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect% `/ J1 s6 x! ^) K6 U, c6 M
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set* c. F- U! v( ~: X" h- m
1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
: Y2 U1 R9 g, w* j5 x9 {1236161 CONCEPT_HDL CORE Import Design shows the current project pages# o* w* Y2 f; z/ t
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.( z% \) }0 h9 b( |
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
R4 F1 c, j9 Y5 y1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file, y) y% w6 _3 S8 `4 c
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape
5 [! T" `7 D; }4 [1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming
& ]; n4 n e& s" k5 A! l1236781 F2B PACKAGERXL Export Physical produces empty files4 V8 t$ [% f5 H" Q* Q( r
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run- \* m! F% c# i
1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command: m* b4 g. Y0 p& C! Y3 d, [
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
: M7 M& f8 W) f u5 B. D1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager. M4 L2 O) x' R' w
1238852 CAPTURE GENERAL signal list not updated for buses. H3 N% b0 U3 p+ k7 D
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes: v, X/ K1 X+ s& s$ m1 t2 _) }
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.2 x! P" s8 @8 ], ~! \# K
1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE# @! n3 @2 e/ v
1239763 PSPICE PROBE Cannot modify text label if right y axis is active7 v7 v: L4 N. g
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images
% |2 w) R: Z$ d4 I; R- ]6 N1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
/ Y: [' X4 M1 O* i! U1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing7 r3 M" }) |8 B9 h6 l+ p$ A# u
1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file5 |: q5 j: g% L q/ W$ h
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable3 s& Z4 k2 {* c; e @* D6 X: d# [
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy# p5 Q$ p' V2 T! [& c
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms u) x6 d. g0 S& J& Z5 c7 H% P
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working* l; T! ~# a" k8 Q' j0 `9 z
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
0 j8 e4 M7 {! ]+ s3 p2 r. I/ z2 n1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard( p. i( R* f, k; {6 k4 d! v+ n% Z+ k
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
; T8 C! v. h/ _1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side9 y& a0 [0 v l7 K) i$ f
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer
, M) X9 T7 \& z% I/ S, v7 |1 R! W1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results0 u+ {* Q3 o1 m$ \! s8 W
1243609 CONCEPT_HDL CORE autoprop for occurrence properties( S7 r3 H, c5 Q
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI; o8 t" q. W4 o" n
1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.% T- s8 R1 A+ C1 @
1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring" T9 l" v6 v5 L: k" F/ u# F; G
1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
1 R' N+ V/ t( A/ P. a1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
0 m9 _3 M& a+ S; ? L4 p1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
* S! a0 s" C9 h8 i' p) |1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?
" l# M+ `% G% l3 P* o+ h Z9 F1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character; h1 X- p* y* K5 N
1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters0 k: f; q/ ?2 z9 N5 S
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown( b$ J: }. W. a
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number+ r; E( q, [! C. N
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
3 q" S) N f7 O C# _1 s% m1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained
7 A& g& a) A- N1 j1247462 CONCEPT_HDL CORE Text issue while moving with bounding box$ x2 X! F/ |; P9 y) R0 ?
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered
9 r H; B! V; s. d' \8 E1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
4 L# G' T& c' O& N, Y; v+ h1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts5 _) G( |% \: |* a
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.% @0 w6 c# j k; j+ Q+ b0 u7 X* W
1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
; {0 j( I( B; T1 e3 X, j1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly3 q5 d* p- O7 ~6 G/ S) e
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.3 f1 R- C8 E* b3 L
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
) l% L" D% U( {# s9 V9 n. X1253424 SCM SCHGEN Export Schematics Crashes System Architect
, ?- \1 g' d8 D& A/ g1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled
. b2 K5 `, K1 N; d1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing1 S6 |% x a& y8 z2 n t( u7 x
1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
" l9 ?! `: _4 q2 f' X1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error
. V7 f. R; u i# V2 }1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.% g* O2 v) {, @. M- M- o9 Z' Y+ b; `% C
1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation6 w4 N, k$ p! _# P _( x1 F
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects3 G" }& b6 M, ^& x
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
; `2 Y$ n) F( F" [& d; j% @6 F% |1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided/ X9 Y9 o- W4 l3 z8 \% p2 G, q
1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
% t1 V' z% k7 \3 \( w1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool) P/ T# h& u* _* f/ p" ~2 f
1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design
1 g$ _$ m& D$ D; r- J" S1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library4 _5 o0 v+ u# Z* \: l6 i4 Y3 w4 `- l
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
5 T# m* G/ {1 N+ a$ }$ ~1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash$ g3 |2 ~- a3 d8 m
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time- u3 P& ^/ s* L, l( s5 g. C* l
1258029 APD WIREBOND The bondwire lost after import the wire information
4 |5 F- ^2 f5 ?: }1258979 APD NC NC Drill: There is difference of number of drills.
, y; e6 L! G5 D0 ^" S$ c4 n1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement
+ u; H) G, `: C1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.8 M& }. ]) k0 G2 s& |
1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"8 X9 U A {; P; I3 F; p
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines# O/ H' {& r+ z |' N4 w) T A
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void
* _" j* ?% L7 D6 t& W- }+ [1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss2 v& {- H5 x9 }) Y
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