|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 dsws 于 2014-4-28 12:56 编辑 , D9 } Y! |$ L, j+ S8 N5 G
5 I. R8 i; ~) t" h$ g u! c
链接: http://pan.baidu.com/s/1dD9XLPB 密码: ujuq
+ ?% R2 k2 c% u0 E# B, I1 q) ?8 ~3 o+ G) I4 `- a2 t6 I: [- Y
4 H1 D6 f5 Z5 g
DATE: 04-25-2014 HOTFIX VERSION: 0270 Q5 h; ~+ O z: a f' C ^
===================================================================================================================================% ^/ S# W. U# } T: `0 P
CCRID PRODUCT PRODUCTLEVEL2 TITLE
2 t) @+ I" w8 D/ ]# z8 S) ]===================================================================================================================================
/ P, k) V) i3 L7 s- K/ ?308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM+ Q! j& |( U1 W* |' Z
481674 allegro_EDITOR pads_IN No board file saved from PADS_in, n% M; G& c: b; y7 K
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
8 D: W" E0 ?& P' p1 ]0 O1 l) G! `1012783 FSP OTHER Need Undo Command in FSP! Y( w! }% e3 b; U6 s, W- u1 N/ j( d
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.1 Q; J" l6 \7 Y$ m
1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved6 ?4 N5 \4 V' e) k5 D m, `+ F
1073231 concept_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.7 f6 ]$ q( a' ~6 J
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups
% Y' z3 x- l2 c1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
; |; l: |& I" r k% g) A( w1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
2 V9 {) h' f" j1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode. I6 B f/ J+ X+ k
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
\; g; A" \0 p" j: D0 ^1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
$ O) ?" `5 k7 ^1 g4 I& P. M1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings+ b5 E4 I( Z9 k5 i. C; M
1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
% K: S3 V0 K- h9 x/ Z& C! T& Q1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
: E1 D( C( `, d8 g# n+ x1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
) ?; `- ]8 J$ Q0 n/ P% ?6 L1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates$ F- z }2 z9 p& t
1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime0 P- J7 m7 c/ A' I; x/ g
1208478 Pspice PROBE Attached project gives overflow error with marching ON.( e3 _& O0 t8 N( D4 _
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol
% p1 M1 O, o( d' j" J. {6 D; P1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
% j. [3 q7 L5 K/ w3 p( f1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape) x/ K9 \( l; @# p( e1 B
1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers, X- {8 l; P! L& f5 l% n
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?
+ T/ M$ J- Q# q! P( _1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.
?8 K- \$ b: L7 o* K1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values1 ~8 V# } d' |
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging7 c# K2 \: s7 _- b: z+ D8 w
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
4 |3 Z$ F9 o, o+ w" c/ C1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added
4 G5 {% S+ K; i& K& r1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
9 {3 C+ ], ^: `3 k1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes& |/ y& g" M, S* L3 c
1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux
) ], W- K6 Z" v, K# n1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
, s7 ^9 y2 @! q1221182 ADW TDA Team Design with SAMBA
/ F% A3 j7 A% n! x; S% [- b9 u! _1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
E# B' ?5 V5 g( U8 Z, c1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
; ?. C1 w6 z8 m+ R3 K' d' c1 e# B1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?7 V; `$ f" Z+ g, g0 X) I+ N
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts: m2 x; A8 K9 M1 `- Z; K. Z
1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
& ?) W- Q7 h7 F/ T1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.0 v. m3 r- ?) P5 g5 b
1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor) y, y# r" |: a& k3 W1 w! L6 |
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.
! i( n1 D L- j7 T1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
# P/ g5 q" ]$ n e/ G4 w& Z H1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin# a( D2 d' b( v) H0 w* ~
1225494 CAPTURE DRC Different DRC results for Entire design and selection
; B7 x5 b# s+ Y$ ?: G1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property' l' Y$ Z s$ s
1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
: f0 }0 r/ b/ d- R1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet1 V, \' b" r* ^. D5 ~8 `
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal
9 u# m+ |, g/ b2 ^1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file7 A& b- v! D0 F9 O8 w- j7 d7 d% n- B
1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
# L+ A) x/ @; E1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,85 G( V, L, }2 A$ z
1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration
5 `+ H' N/ Y; f! }- L- h' ]) r* `1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part- p% {3 |, ?6 j+ Y' R
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case0 Y8 p% R% x: c4 u1 N+ E8 x
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins
6 ]/ u8 B2 Y3 v# e8 T5 F1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection/ r; f9 M3 p/ ^* q J) s8 X
1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time., C8 G- @+ u8 n5 r6 U
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
7 Z0 d; O+ _0 w- p/ c1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
3 f5 k$ g; O8 w; U0 t B) V" q1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
3 O' S% D$ R. j9 Z5 @1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined7 V7 o6 P/ }; \4 r
1230432 CONCEPT_HDL CORE No Description information in BOM3 N3 I a5 Z- I+ n d
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
' o0 l+ F% ~* P q: _1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files
2 s% v D: h6 J8 R1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
, R, u& L) G& P; Z; N1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets; I3 L+ F$ O3 I
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
4 C* W" X; |# F" j7 m1232100 CONCEPT_HDL skill Unable to execute the SKILL commands in viewer mode* H$ R8 C9 ~' D) _& G# Q! w
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical
! Y& R) t# _' T6 d1 |1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode1 w( e+ Q' Z7 k3 N% p& `1 [0 V( n
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files
& U" q3 e7 ~, L; T8 i/ R1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy( B. ^ `+ o' E/ w
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
3 p ^, k% c. L4 V! G2 ^! s1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect
6 G/ d1 v/ K9 A5 S7 g3 g1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set$ I* h1 i) m+ t5 D$ E
1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
3 u4 p0 P. Y8 r6 a1236161 CONCEPT_HDL CORE Import Design shows the current project pages) W! b5 J5 Y5 t# o4 u
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.
- Q5 k$ [# e& O1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
& R L" e5 \8 d% l) H# I5 R1 }- D, H1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file7 R' B& f: c# W; S) j( g
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape; l' _% w/ ?7 [( |; e! p1 V' z* |
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming' S2 Y) P% V% t' I; d% S" s& {
1236781 F2B PACKAGERXL Export Physical produces empty files5 \. B- ?$ u9 s5 k. p8 A/ J
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
; ?) |; Z& M1 A4 O* ~: X/ b1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
! S% Y; I- u3 `9 L, f4 R! C; I1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
/ |# n0 x# e1 P4 ^% W1 o1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
/ \' Q5 P T8 D4 A& l. X1238852 CAPTURE GENERAL signal list not updated for buses
" S5 n/ ^& D4 ]0 o: _9 L1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes* G3 a1 q* o* w
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.0 h6 k/ c8 R3 ~5 W" y) r* M
1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE% b8 q9 Y5 a& f4 i; `
1239763 PSPICE PROBE Cannot modify text label if right y axis is active; U, Z/ T5 q2 R/ F5 W0 @7 Y
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images6 ^+ z( p6 ~9 z( F g! N. F1 r
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.9 b$ O! u( T, x9 q5 f4 Z% Z
1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
+ a1 n# e }4 C) m6 O" c1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file6 w2 W$ b f# r: L T D4 f8 Q1 T
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable
5 P( ^/ `2 {. Z4 e1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy
" J9 x" z% K( q; b O0 N1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms2 Z6 Q% _9 M/ c: ^, Z& w, A ]
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working
- c6 l$ K" K& p* Q7 n. d$ G1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.) ]+ g/ v# Z) z! D0 c
1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard2 N" o% i* x% ?/ [5 \
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning* }' y, h1 C0 ~8 Q
1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side
( v! V" h0 f: p% X$ N1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer
[$ s% Q# R- O$ s; L1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
4 ~/ C- T+ e, V4 R* r, D1243609 CONCEPT_HDL CORE autoprop for occurrence properties3 j' J& b* Z+ O O9 m
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
; \( G8 L; G. r1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed., H/ f$ v) J% P$ d
1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
N$ ]2 P( q2 h. R' Q1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder/ ^% Z! K/ q) ^: T' L- y
1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
9 g4 z- v% U4 x7 Z, C2 }4 Z1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design. [: d6 b2 l3 v5 n( T! a$ m% i& U
1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?# Q2 n& o( G# {4 D$ W1 g/ ]
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
H/ r8 E8 Q5 E$ g3 c- k1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters# Z! |$ S& n- N' n
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
; H. @6 P5 d! D8 v1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number$ a% t2 o# y8 ]" ]. _
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL" O/ H9 ?: ?; p5 |
1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained8 q7 I" ~5 w9 b6 {9 ~' f$ j L: y
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box7 I- H0 Z$ s* [: E
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered
; r! c+ \1 ~4 ^ T) W1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
: Y$ L9 }6 b. |( q8 w1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts6 r) L, E* [! X: m' g
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
" J) b# `, N' m& J+ o# C1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint# u( q$ T0 n) w* f
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly; W3 @$ y. I; o, E1 m
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.4 ` h/ }0 V# j( y2 }( x
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies0 B% O% Q( U" B/ [) z/ a
1253424 SCM SCHGEN Export Schematics Crashes System Architect. S! r0 f& L9 b1 W4 v" {
1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled
( U6 C! A) f, ^; D) s1 L1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
7 X- x) ?: F, D, y1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
+ t: F$ {8 W6 {. k1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error
: j8 @: @: e$ i# I) w1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.0 n# x0 o. J- Y+ ?9 f1 H- ~1 I; e
1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation) p, _" Q8 O+ G/ r) C: c7 X
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects! e- R/ b$ c7 g$ o @+ x5 q) Q7 y
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
* V, I; U o- ?# q' t4 h/ q1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
+ I3 C7 {) ^5 [( I1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE, |' m) S1 r$ ~5 K
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
$ i. k4 R; g: O c5 `1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design5 Y6 p' H: E# J/ m4 [( u
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library
6 F0 P/ c- e% Y+ B3 ?) f8 H1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
: c) t/ U' s8 o2 [" v! f2 G1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash
9 {6 L& E& U7 k+ l6 B1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time( H5 s! [8 ^3 E& \) {7 o
1258029 APD WIREBOND The bondwire lost after import the wire information
# I8 G# O; R2 ?' }! C% J1258979 APD NC NC Drill: There is difference of number of drills.; }) H- P! W d; m& J! U
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement
/ b% b2 d& l! e2 ~8 {1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.6 K1 M$ F# g, }0 r% E2 t" n1 R
1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"7 t( h1 h- ? v6 B# p
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines5 O0 W: p( E! T
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void$ [ F: w% g# l4 J
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss1 [; R( Q4 ~) I/ R# l) k
& Y: W! J& H3 `% J5 j
|
|
/1 
发表于 2014-4-26 15:14
收藏
淘帖
支持！
反对！
楼主
