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本帖最后由 dsws 于 2014-4-28 12:56 编辑 . Q+ W7 h, M& o
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链接: http://pan.baidu.com/s/1dD9XLPB 密码: ujuq
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2 H5 I6 X$ u* w+ Q/ ~DATE: 04-25-2014 HOTFIX VERSION: 027
3 m. M, D& T. _4 c===================================================================================================================================
# Y3 X7 v1 W: I0 e- L9 S; TCCRID PRODUCT PRODUCTLEVEL2 TITLE
6 X# A" W5 X8 D===================================================================================================================================
+ t7 J a. Z: z/ b308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM
/ q# m2 h! @( H5 j; d481674 allegro_EDITOR pads_IN No board file saved from PADS_in
4 _5 Y3 S" j" X- M982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
3 l2 ^8 s% Y+ s) k) s9 ^. ]$ I, R1012783 FSP OTHER Need Undo Command in FSP* V5 J/ |- s8 @: n8 L+ ]+ k# c
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.6 j$ D5 d9 Q2 c' Y1 U8 ~$ N' }4 v
1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
: x2 e C. _! j) g0 l/ I; I1073231 concept_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
8 r4 ` A# ~* d+ X1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups9 A4 \, w! k4 F7 S; I' b4 a
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
5 p9 L& a4 f) g8 M! q1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command& @0 j k4 @7 q4 _3 o7 A' h
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode$ X* w: o% p4 C0 f8 d: a# b
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
+ ^0 V Y `9 x, o# n1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
# z6 O4 d, h M0 p( z7 V4 d1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings2 ^' ?( D& Z5 f' G
1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
0 ` O3 |+ W. q: w9 A1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV9 ^5 D# B U. {1 P! s% _
1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
% f9 J5 i& D3 y. A1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
; p2 R+ h5 o) k: b' g; Z: D2 O1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime
4 R$ _/ w7 ^) a$ F1208478 Pspice PROBE Attached project gives overflow error with marching ON.
% Q5 j0 e W! o7 k- Q9 ~6 D1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol
1 ]. l# Q/ J/ |& d3 l1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed& s" s/ S- [+ P
1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
+ w$ B& i f1 Z" b/ x7 }) k7 f1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers8 F5 ^( Y4 [8 j0 a
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?
z& ]3 m/ \/ c F3 G9 w1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.
2 K# L' b: _% c1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values
" t( k$ s4 Z4 f0 N+ k, ^* h. h1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging( |# f1 ]3 z5 ?3 O
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information* U* x' c# Q7 q' h: e, `
1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added
5 A+ Q; T" e0 ~$ l- H1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
) ?! C+ w1 o* E5 D9 F1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes" d) ]- O( E# F
1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux) y9 o& K( @/ m0 T# [( V" F. r; ?
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided. m5 Q& r' @7 O! \* M
1221182 ADW TDA Team Design with SAMBA
' H! @1 M# G5 L& M6 z3 V+ B1 ~1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair; I3 a7 b# V( G2 R! e. K9 C( y3 f
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened6 F' G/ k$ a( g z) y
1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?- ?8 R. k/ r3 ?$ f& [
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
7 F' R. ^" w+ z) y2 O1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms2 j2 s/ \6 K; f& g$ d, \
1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
! P, d- J2 ?5 R1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor
. _! [% s1 F( U3 ^ ?: e i- `1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.& p2 |- L' f" z# c
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
" @9 B8 o9 ^+ s3 i( f1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin
$ W, P: S, _2 i8 Z+ n+ R) J6 C6 d1225494 CAPTURE DRC Different DRC results for Entire design and selection! N/ v- \3 x) R. _% p0 Y8 e! m
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property0 z) Y) s+ ^6 }5 U$ p. g6 k4 z
1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet( z7 b# z Z. c! y% {- u- R5 u1 M
1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet( d7 f, E8 c( N2 a4 \ B+ H+ Z
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal6 |/ _1 ]( [% T( G5 P- ?7 j
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file4 D; C% Z% k$ D- x6 V |' c/ ]& D @
1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
2 R) j8 U3 ^) u* g1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
8 b/ f1 i! C/ P( e7 K& ^1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration7 J/ B5 h0 V. d0 \; z2 N7 v
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part, m( g$ H3 L' l# D9 u8 O; `
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case: T3 ^% g7 Z) X+ M( d$ }7 z; X
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins0 Z1 _7 g* T" }; o2 r
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection2 F* u& v: ]! I4 ~0 M
1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.5 }: v8 V9 k2 s7 V3 A7 J. h9 X, [) A
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility., \0 N/ a3 [" p
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
+ g& J4 x8 P& N! L6 S3 l+ R1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
$ S1 U+ W% Q) y0 [$ w* u6 }1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
: }4 ^8 ~, G/ x( [: V1230432 CONCEPT_HDL CORE No Description information in BOM2 a2 q# r$ j8 B, j6 N
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
5 F, U! N& J6 l1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files
/ w9 v, o+ e* N [$ A) f4 z p1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
7 q$ K6 I8 g# z- @1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets
1 Z# O% L5 ?5 V1 J5 W: r, x4 G1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.9 Y2 H7 K8 e5 k4 U1 f
1232100 CONCEPT_HDL skill Unable to execute the SKILL commands in viewer mode( s6 z* T# X, W9 \# k& D* L- E
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical4 S0 u# H7 w6 q+ N1 O; w/ e, I
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode
" j$ w0 P$ O& c) C8 D( _$ B' z$ K1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files/ w* Y. W/ L& `" N& T9 D( a8 ~$ r
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy
/ J4 X. G: ?1 j% ? r1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
3 i7 A, a5 h3 Y. w1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect: S8 `. S& i6 A$ p3 s$ a5 X+ I& Z
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
. e" `: l7 p9 z1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic0 j. Z. l. l$ W: ^/ R& U& ~4 E
1236161 CONCEPT_HDL CORE Import Design shows the current project pages
% f# Q) a, f8 {" s8 n1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.
$ T/ o2 N7 A( H1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
3 K- t, e% T& ]7 g1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file$ s: P# I: m" b5 X
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape4 e9 }7 p3 o- Q ]$ }
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming
7 t' [% N+ g0 M) v2 S/ \1236781 F2B PACKAGERXL Export Physical produces empty files, { t, ~% U1 |, V3 k" r% q
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
3 v$ M; D1 [3 f% ~) h/ I% [3 ?, @1 ], U1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command1 U! j/ n: k* e0 L% V( a
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
8 \6 D+ n* V* Y; h; G* `1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
- f; \: H0 m! i( y1238852 CAPTURE GENERAL signal list not updated for buses
( @" g+ ]0 s1 B* z" n1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes$ K4 o; @; T! ], i5 V& `3 C
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
( [# D E4 Z2 s7 x. q1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE5 `0 o: g$ }' a# @8 I' C
1239763 PSPICE PROBE Cannot modify text label if right y axis is active( J( p" e# N4 P( G
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images0 s W# X* M# D& C0 ?
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
8 B6 a8 o+ [9 o" I g1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
: t3 w9 R) k& w- S- Q9 t5 s" E, c1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file
, N4 r) s$ ?6 Y9 ^, |* E1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable
+ b w- B% c9 e. ? z$ ?1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy
, ?, o2 k3 M8 s( z* e1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
% k1 O* ^; ^6 H6 a# y) J6 k& x3 G# f1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working
; T5 ^/ F% G; B- h4 H9 S* y1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
( }; m( O3 d+ \$ c1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard0 p. G9 a* k/ N2 v& B! } q
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
5 v" J) s2 Z8 x' m/ w! b s7 c1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side
% X! n- W! ]% F, y- ^1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer1 I& ^/ n+ f. i7 N( l& }- l3 n6 k2 e4 E
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
2 i4 j. e+ S5 k2 }1243609 CONCEPT_HDL CORE autoprop for occurrence properties
0 y6 D! Z$ n( O" w$ i3 H0 q. G6 G. |1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
$ j. R/ Z3 u5 u6 e1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
, C L) c* ?2 c( j1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring4 e% q4 n& k- `& ]0 a
1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
( f# r9 \ j% @( {7 k) S1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
9 n, W( A% c4 i$ k; {1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design7 Z- i. o8 d, P, ? }' B$ W9 Y
1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?- h7 o a: s2 d2 \0 Q
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character7 C) R3 {& ~6 N/ O$ @! Y: g9 j
1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters3 I# j; i* } D+ p
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown% U9 _& ~" i6 H9 y9 r
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
0 K4 q5 X" P( T" I) F* T3 f( C4 N8 ?1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
4 H$ N5 a ]$ y) U1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained' Z$ |3 j) T3 o1 K d" x& o# b4 N
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box
/ _/ H9 b' o6 X1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered- j- C. ]& J- _& }1 `8 |
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components# |9 w2 R" t ?6 ~. z2 W! e
1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts2 [* s$ z2 v! T8 C/ e: G
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
3 d% J, L, F1 U+ z1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
5 p8 I H* \% W1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly
3 q2 T; S$ V7 f8 v8 O: H1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
) s. I3 V+ D! @0 J1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies% \8 b& U8 o5 k
1253424 SCM SCHGEN Export Schematics Crashes System Architect4 ]8 L- n/ j \
1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled
- O, w3 H4 V8 r3 j: E6 J) Y2 v& O1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
5 f$ z# V" k& P" m& w1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
: [ [: o; G2 J c2 p1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error
1 m5 ^- a. t( P1 ~1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
) `8 P5 j7 j8 ~7 i: J+ x, W1 v1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation
1 [. \$ ?8 |4 h* o- Y8 a G6 m7 |- c1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects& [1 M4 c' [/ r* w; A) M2 r* \& \ p
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
0 E5 Q @& J- ]4 h: {3 v) J1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided( R) @+ u' b! @1 Z: J8 l
1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE; I" Y z8 L; I6 E+ u: D
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
0 [$ Z E; u! `1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design1 S1 }6 d' g [
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library7 s: o" J/ \' c/ N
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long) Z8 c: d' h9 X1 L1 B" V
1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash6 d& W9 Q) H6 s/ K# }
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
* I/ R, i4 x$ {; H1258029 APD WIREBOND The bondwire lost after import the wire information
9 p+ B; |, n. p0 x1258979 APD NC NC Drill: There is difference of number of drills.
j" S z' N$ N$ D; v1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement" J5 A. L- J- A: D* m
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
6 v8 q: ^) L! w: j+ `1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"
& x; E. Q6 H1 O5 v( l W1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines" e2 i5 R2 z9 R0 [
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void
! G/ o6 h2 \2 g% V# o5 Y5 H1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss- c1 ^; J& `! A; m& j3 I
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发表于 2014-4-26 15:14
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