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http://dl.vmall.com/c0fu1auqa8
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DATE: 02-14-2014 HOTFIX VERSION: 023
5 ^ ]6 N# l) ~/ G1 W, j H) @0 r===================================================================================================================================1 R3 j7 w6 Z! ^
CCRID PRODUCT PRODUCTLEVEL2 TITLE
9 m) C+ p# O( v. B* C) H===================================================================================================================================
. M, B. X$ g G% ]' B. Y$ ^2 r1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.- b5 P% l5 f- P. F
1202715 SPIF OTHER Objects loose module group attribute after Specctra r- _7 _# b4 o8 Z7 c7 e
1203443 ADW LRM LRM takes a long time to launch for the first time
' S5 E+ `/ j" W" t, k1207204 CONCEPT_HDL CORE schematic tool crashed during save all
% @+ l4 M+ c/ C4 t' q0 a1 Z1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter
7 N, ?+ {9 q, H+ O' g$ Y1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA: { `2 g& u8 j6 S
1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
# ?1 i- j; F' ]0 H1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr) O, u2 p- n& b6 L7 x% @
1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.- s( ?+ n; J H: F$ D7 N7 p4 b
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
. q; B# o2 P- _) F6 h0 p2 _1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.; e5 ~0 C6 I$ J) e9 H
1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I77 W5 v8 `" z5 k+ m' d W
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's
) `, G+ R# T( O) F9 E4 A6 u% E4 _1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
( z* z5 t& O+ n/ L/ t0 j0 s- E1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes* J& P# k0 J! j/ J
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form$ w: t/ K& o7 H- I& U
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
5 i- J: [! p) A3 B8 h( `/ l; |9 O1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX, f8 T) N' s+ I* k! V3 G/ v
1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
; q8 g( t6 _7 Q0 t+ u+ s9 @1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.. g5 `; y) T& b+ I- U {+ B
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol( ~. [: f! b- j v
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues, w7 }( |, J1 N) k+ M
1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File5 @* X) S* u6 [' ~
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 16:44
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