|
|
http://dl.vmall.com/c0fu1auqa8. l* U: F- E/ Y* G" d2 M9 K
4 L. B+ N$ b# k$ o2 I
, ?' v3 U4 Q! p, f* L% Z1 l; t( c! k s
DATE: 02-14-2014 HOTFIX VERSION: 023
( Z# V# }+ N+ [$ {# l- e. H) I/ b===================================================================================================================================
2 c9 e9 x% ^9 L1 i: r8 t: yCCRID PRODUCT PRODUCTLEVEL2 TITLE3 N5 |( q+ x7 R; Y3 g+ `
===================================================================================================================================2 R Q) f9 f( |4 f0 h, j4 z
1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
8 H- c3 Q, v. u/ P/ u% p1202715 SPIF OTHER Objects loose module group attribute after Specctra$ _4 S9 {5 N C8 k8 b7 c
1203443 ADW LRM LRM takes a long time to launch for the first time
, i8 C% F5 h- t9 t! {( n6 X. w; x0 \1207204 CONCEPT_HDL CORE schematic tool crashed during save all
! z$ z1 j7 f. y, ~+ M2 n1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter& S) Q+ P0 y. O
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA/ y/ n) d2 K& l/ X+ W
1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side, P; ]. o; ?/ L3 v9 S1 [
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
9 ~) v( w: f( [4 H- b# T1 B y1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.
% I5 j8 ~/ W$ x; h& n* \1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
0 m0 S' }& H8 Q, h1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
2 e, u7 a5 J2 |0 l# K C, k1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I76 P9 [# u, }. e& ~0 R4 x
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's( Y' ~7 ]+ V7 }, R. ^( ^: P. |& m/ A
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
( K0 a5 u' Q( U% y- R2 m1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes
" P: \, t F* t1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form
- ]% U# u6 ]7 x( U" f( U1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
6 n) |3 x! y% `* d, j+ b1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX. s& M! j9 C5 c
1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.5 b" Y5 x- E x# f8 M7 ^& m. k
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.( j, \! K# T; Y% _
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol% h0 q1 t, V# x- f% K) ^
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues, f) n) r" S# R& [# M/ b+ o
1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File# F$ B1 `; W8 ?4 a- Y" Y) t
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
|
/1 
发表于 2014-2-18 16:44
收藏
淘帖
支持！
反对！
楼主
