16.6又出23号补丁了，求下载链接。

Jason022

16.6又出23号补丁了，求下载链接，话说这个更新速度比我的下载速度都快

steven.ning

http://dl.vmall.com/c0fu1auqa8


3 F  [% a. Y+ G- d' E* E8 @2 ~
DATE: 02-14-2014   HOTFIX VERSION: 023
; f  W0 w) `1 i! v& K+ p===================================================================================================================================
1 `- X5 l* I7 R# RCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
- v0 z- o8 E# L===================================================================================================================================
% c; m$ }$ _8 y1120183 F2B            DESIGNVARI       Variant Editor Filter returns incorrect results.
/ F7 f/ p7 @  J/ g( B9 s) o) J1 o1202715 SPIF           OTHER            Objects loose module group attribute after Specctra
0 w! p! ?/ Q) R, k1 T. U1203443 ADW            LRM              LRM takes a long time to launch for the first time
! [$ c+ v" a" E! \! o2 O' c/ P1207204 CONCEPT_HDL    CORE             schematic tool crashed during save all
1222101 CONCEPT_HDL    CORE             Pins are shorted on a block by the Block's title delimiter
% J* F, {1 k( d1 Z' z: Q+ X& O1223709 FSP            FPGA_SUPPORT     Need FSP model of Altera 5AGZME3E3H29C4 FPGA
7 _, b8 {0 ^: F/ ]1 `, J8 }* ~1224025 ALLEGRO_EDITOR INTERFACES       The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
) _$ R% y7 s* u: a' j1225591 F2B            PACKAGERXL       Aliased net signals starting with equals sign are not resolved correctly in cmgr
9 j( n  j: u4 H; @- F$ D  ]+ k* {! V& ]1226480 ALLEGRO_EDITOR EDIT_ETCH        Routing time is took to double increase when using the Add Connect because DRC is Allowed.
1229234 FLOWS          PROJMGR          Can't open the part table file from Project Setup
  w3 W8 n1 x: h* y- A2 f1229555 ALLEGRO_EDITOR ARTWORK          IPC-2581 not recognizing pin offsets correctly.
1229610 FSP            FPGA_SUPPORT     New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
! S; W, ?; X6 X0 p1229664 ALLEGRO_EDITOR SHAPE            Shape not voiding different net pins causing shorts with no DRC's
/ `- j5 X4 T- B  y/ ]* C1232601 ALLEGRO_EDITOR MANUFACT         Cannot add test point to via on trace.
2 a& v' \3 v. G6 n+ g1232772 ALLEGRO_EDITOR DATABASE         When applying a place replicate module Allegro crashes
1233216 SIP_LAYOUT     DIE_ABSTRACT_IF  Allow more than 2 decimal places for the shrink facor in the add codesign form
1233690 PDN_ANALYSIS   PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
9 [; ^* ?2 [/ w' @; t. d2 I3 o1233977 ALLEGRO_EDITOR INTERFACES       single shape copied and rotated fails to create when importing IDX
1 Q6 |  m5 f9 S0 Q+ `1234357 SIP_LAYOUT     SCHEMATIC_FTB    DSMAIN-335: Dia file(s) error has occurred.
& w# `9 t0 i5 ~2 d& s! M1234450 ALLEGRO_EDITOR INTERFACES       clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
, ?- Z. C; a. k3 Z; ~  [" Q1235587 PSPICE         MODELEDITOR      PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
: e7 Z6 a+ v. O; h1236571 ALLEGRO_EDITOR GRAPHICS         Allegro display lock up and panning issues
; n8 c: v3 L6 Q4 U; k) ?  C1237415 ALLEGRO_EDITOR INTERFACES       Multidrill pad is exported with single Drill in the STEP File
& s5 P' e( t2 t2 ]1237807 ALLEGRO_EDITOR SCHEM_FTB        The line feed code of netview.dat

wolf343105

还是等到第30个再打吧.

yinkzhdmi

谢谢分享！！！！！！！！！！

dongreenew

好快的更新速度

jingjisong

太快了，是好事情还是坏事情呢？？？

Jason022

谢谢分享，有人能转存到百度网盘吗？

amaryllis

才刚刚下了22，这不到一个礼拜又出新了，神速啊
/ `, E# Z# p2 Q2 l, f; o' s, V/ i- G谢谢ning

rockymohuan

这么快的更新不是什么好事情。。

steven.ning

Jason022 发表于 2014-2-19 08:46
! W, `- X# t: A4 F谢谢分享，有人能转存到百度网盘吗？

http://pan.baidu.com/s/1eQl7md8

inspiron1501

1229664 ALLEGRO_EDITOR SHAPE            Shape not voiding different net pins causing shorts with no DRC's
看到这一条，必须更新啊。

wu5163

我觉得下载速度跟不上更新速度

elm99

谢谢ls！

fanrick

更新太快了，坐等hotfix30

wangxs_song

频繁更新太累了。