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http://dl.vmall.com/c0fu1auqa8" A' n" v0 O, Y1 B' |5 }/ g
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DATE: 02-14-2014 HOTFIX VERSION: 023, @9 l" V) u$ b
===================================================================================================================================
9 S- O+ V6 _9 C% z' r1 Y2 O' bCCRID PRODUCT PRODUCTLEVEL2 TITLE
9 Y& u0 t2 h# R===================================================================================================================================" z4 R% d2 {- c
1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
8 y# {+ z5 _8 @8 Y1202715 SPIF OTHER Objects loose module group attribute after Specctra9 [2 O% x* s$ L1 L
1203443 ADW LRM LRM takes a long time to launch for the first time+ B7 Q( t }& L- s% X" @
1207204 CONCEPT_HDL CORE schematic tool crashed during save all9 b, Z0 n0 @% M! u& d, z
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter9 R! C9 g! I& |& k
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA. d& t X7 p% N& _ ^+ q! A
1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
1 ]4 h" f. w4 H O3 c2 _5 ]1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr/ X( w" U: b. H; j- E* V& ^5 i
1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.
4 t) E% F0 b2 ~1229234 FLOWS PROJMGR Can't open the part table file from Project Setup% \2 `' M! j* U/ ~9 P: ]
1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
& q; E9 r7 ~9 Y$ ^1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
/ n1 B. k" i+ K. Y: n, P3 Q1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's
: F& o- S! f) V1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
! t1 K# `! {/ {! ?1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes; ? T' T/ ?' i
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form
7 d0 I- E: q& p" c/ z3 O1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.( l c$ T* G2 U1 p
1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
7 N3 F8 ~$ p6 Q1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
+ U- ^$ D8 o" _$ @# C+ [9 j9 I1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
+ V7 i V6 S9 Y) S4 \' M1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol5 D. ?6 w4 P: R& V. _
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
# Y2 ^3 O. W2 A4 p7 T; _# @" M- l1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File
# d) k: ^5 ]( r. k# h7 b1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 16:44
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