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DATE: 02-14-2014 HOTFIX VERSION: 023+ ?+ _5 v* z, l2 v. u9 D
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CCRID PRODUCT PRODUCTLEVEL2 TITLE! T' o% F+ w. y9 g
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1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
2 S" u3 t. j- w6 S+ ^1202715 SPIF OTHER Objects loose module group attribute after Specctra
; R6 j3 K2 u- s8 H; u1 P* z& F1203443 ADW LRM LRM takes a long time to launch for the first time
8 a5 e1 E: d/ x, V9 t/ ]4 t% Y: ?1207204 CONCEPT_HDL CORE schematic tool crashed during save all
; p4 z2 C+ K. V" o# \1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter
! p) {: `$ A1 p1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA
0 T+ x, g# I$ O9 |4 s1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side2 y5 ^# x0 P' ]' o9 z6 E
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
& J9 x- l% n3 e5 g& K1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.- K" ~& ^ k4 }3 m
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
9 A, ?4 ^+ @2 i. q6 F1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
5 H3 }+ V) t- ~- R, v* G+ W# ^1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
7 q) ?, S* @! p3 s& g6 T' `4 O, R1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's
, p! j( {( Y, g+ l# c% j& P1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
- k+ [2 ^/ N, }1 F5 N E1 s1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes* v: p4 M9 F! r* c) a3 @& @5 ]
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form
8 z, S' n& O5 y; N- X. _% v! Z1 ^1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
u+ e9 p; O& {0 ]2 y( {1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
% B# i/ K" _% J1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred., u; e: z9 w, f$ \
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.+ Z- t* @- d) a# A
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
. [3 E3 j' g- t4 z/ s/ t) x- T1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
& \* h S8 X3 H4 X5 \8 {# t1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File9 ^/ u* G1 I8 O* r3 G- S
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 16:44
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