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http://dl.vmall.com/c0fu1auqa8
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9 p6 D' O3 A# UDATE: 02-14-2014 HOTFIX VERSION: 023 a2 _6 k) H" f4 I$ T8 `4 R
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3 E; Z- V& W+ }' ~# I( [2 y) X* eCCRID PRODUCT PRODUCTLEVEL2 TITLE
2 {( a* k$ J _# Q+ @+ t8 L===================================================================================================================================* G" R6 g' Y# s* O r
1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
4 X3 E4 O( D5 `1202715 SPIF OTHER Objects loose module group attribute after Specctra
9 G/ _2 C U* s1203443 ADW LRM LRM takes a long time to launch for the first time- m/ j# f1 h. b: f0 G; h
1207204 CONCEPT_HDL CORE schematic tool crashed during save all
6 Y8 N9 B0 m+ u \5 x1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter# [2 c7 x# a# _# U5 e2 Y
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA
2 A2 y# s8 c# J7 x8 @+ R1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
/ t0 H( l. g/ U5 C1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
% G$ g5 H3 ~+ S* \8 y0 o; e1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.) a; h. H% U. Y; _ _
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup, W/ U) U) Q9 O) i9 b! B
1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
9 o0 a/ M% x5 ]9 G1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
5 c& {$ g! L2 X- }- t/ u& S1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's
0 o/ E% V: y; }/ ^# ]! n" h1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace. O; N' E. ^/ S; k9 s
1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes2 K2 A6 K% R! D8 K$ g: g
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form; k5 g0 G4 B r y$ E( E
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.8 c( u8 m( a) X0 o- g
1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX: X+ n6 m0 ]8 x" i7 L4 C
1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
$ g& K- `9 c/ V/ k1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
3 l ^; T' ^! T0 }2 t4 [1 g1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol2 a8 O+ ?4 y' P* N/ e) E1 e
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues# @8 B ^. m) g! g1 Z8 _: m
1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File
2 g6 I" ]+ D' [' Y1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 16:44
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