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3.1 Minimize capacitance
. ^1 @5 _4 \9 C! d( E/ w/ _Energy consumption in CMOS circuitry is proportional to capacitance. Therefore a path that can be followed to reduce energy consumption is to minimize the capacitance. This can not only be reached at the technological level, but much profit can be gained by an architecture that exploits locality of reference and regularity. Connections to external components typically have much greater capacitance than connections to on-chip resources. Therefore, in order to save energy, use few external outputs, and have them switch as infrequently as possible. For example, accessing external memory consumes much energy. So, a way to reduce capacitance is to reduce external accesses and optimize the system by using on-chip resources like caches and registers.. H3 k% D/ t z2 P! l
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Routing capacitance is the main cause of the limitation in clock frequency. Circuits that are able to run faster can do so because of a lower routing capacitance. Consequently, they dissipate less power at a given clock frequency. So, energy reduction can be reached by optimizing the clock frequency of the design even if the resulting performance is far in excess of the requirements.
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Another way to reduce capacitance is to reduce chip area. However, note that a sole reduction in chip area could lead to an energy-inefficient design. For example, a energy efficient architecture that occupies a larger area can reduce the overall energy consumption, e.g. by exploiting locality in a parallel implementation.
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他是叫你減低半導體的寄生電容，不是叫你減少 Bypass 電容。& B. j# |) U# c+ F* X& I8 a
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這點「胖的奶奶」的表子實戰經驗是對的！
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发表于 2014-2-12 14:37
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支持！
反对！
楼主
发表于 2014-2-12 18:20
