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本帖最后由 紫菁 于 2017-9-14 14:38 编辑
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DATE: 04-26-2013 HOTFIX VERSION: 008/ r# J" b, l5 `& x, ]
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
. c$ D& D- v5 Y$ p===================================================================================================================================
: u: o5 E; l; N: W! q4 C876711 allegro_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit+ u, H' j6 `4 O4 s2 _: Z' r
1080386 concept_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation
9 `9 e8 h/ z* a5 Z1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device+ _$ O$ ^% F2 G0 `9 J
1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
1 c; g; F C& n/ u! O: v$ D1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section" R, Y' H" r$ ~: V/ m; h
1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running
4 ]/ o g9 H# l1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.
* N& A9 |7 c( X1 _3 P3 [1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence# a# I. y8 ~* @! a
1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.4 P% h, M C# a. h4 @( @( U
1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason
: z& l5 U! X4 w, X" w5 c1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.
2 F% }, j8 _" u8 L9 Z' k1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?
8 D$ G$ ]+ ^6 h6 y$ v1120414 ADW LRM TDO Cache design issue
; ?9 ^ V) ~ i( ?, q: E F N1121044 SIP_LAYOUT skill axlDBAssignNet returns t even when no net name is assigned to via
6 T2 P0 r+ y9 Y& r/ g1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups
, q" G9 s4 R5 k3 D$ |7 D+ L+ I1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it n/ ^& V7 f( P$ K* h) g6 n
1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.
: o0 ?) r3 M7 k5 [1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced
8 e2 ~0 A# q* L+ I- H6 F1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.+ f) _2 k0 s* e+ O* |. ?0 ?
1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable
0 ` o" q2 R6 a& x: ~* ~- q1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file
+ B1 F! v# H% j. Y1123816 CAPTURE PART_EDITOR Movement of pin in part editor
" O& y0 a4 Y6 B3 [9 N1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50
" T# U% S* M% B; M% m) KDATE: 04-13-2013 HOTFIX VERSION: 007% M# A3 {2 \0 _: k
===================================================================================================================================
C5 a% b1 u/ ~* N s. H: c3 YCCRID PRODUCT PRODUCTLEVEL2 TITLE
0 D0 h$ k$ F6 X2 V===================================================================================================================================
5 V5 X; u! P! |; N, S/ z1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die! ] {% k1 k' C( ?; w* h7 l: v
1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6& V* P1 B6 P( [; P$ _
1112295 APD DXF_IF padstacksї offset Y cannot be caught by DXF.
- M. h1 p% c$ o, M6 w: o. z1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components$ ^# n/ S9 L6 h' R" W
1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
8 H8 c( r& f2 M6 y1115491 ALLEGRO_EDITOR SKILL telskill freezes command window
7 k, L" o% s9 |& Q+ o4 N- W1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
& }) O5 s$ T6 i" L1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.
# ?( {% ?$ a. G" A4 F1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear
1 g0 g" F' w8 b3 p8 T: b7 ^1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks; P7 D' O* ~" p% J5 R
1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?
3 ]7 C5 ^, r' _3 K1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh: z. X+ D: n9 _
1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh
) F% j* S% A8 ?) P5 b1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors% Y% y6 \" R8 n- `+ T2 G& p; f
1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6
( {$ i# k% I% l5 y. o& r) [1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently
: T. M( C2 j& {1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps# t- P3 c2 l9 u6 O- G
1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks2 q0 ~6 _, X) c7 O3 ?0 p# X( L
1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.+ |# l( F$ y% k+ |
DATE: 03-29-2013 HOTFIX VERSION: 006& j8 B( {) e* K: R0 ]5 ~; w! C
===================================================================================================================================+ m2 S9 @: ]# b Y
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 P/ o$ ~8 C5 I; z+ n0 K; \===================================================================================================================================, `/ j& ?1 M4 f: ?. u
110139 FIRST_ENCOUNTE GUI Error in Save OA Design form! j) j \9 z' ~
625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.
' J; Y3 C! }% ], i1 U4 |! T% o% x ^642837 Pspice SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep( S, V. O: D! `0 U2 Y2 g$ m: [, N
650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".
/ E3 S2 M% F- a0 Q653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend0 m! |3 @+ W, F# C
687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect/ q, E3 ^: a- T7 P+ R9 b
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
- @6 ? L& r4 X6 `( u825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
) e. W# S* B& O834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
6 v4 t, ?2 |1 g: \1 _835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
: Q) C5 K. d- V4 y0 ~6 h7 X868981 SCM SETUP SCM responds slow when trying to browse signal integrity
) B% ~2 W w. s5 @871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide3 W3 L- _) F( w$ b& [% T
873917 CONCEPT_HDL CORE Markers dialog is not refreshed
6 a9 ^. J- C- ?887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License0 p. j2 B# \" q7 t! [( `9 E9 ?
888290 APD DIE_GENERATOR Die Generation Improvement
1 K+ A$ f& A# S3 m, Y892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
G4 M- E% R- L. x1 ~902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice
w K( N" o$ r: ~908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM
: a1 K' x5 Y" `3 I1 B' j9 I; ]922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols; z! ~4 s' `# C' H) ^* {
923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences
% e4 E3 I' w% j! }; G$ y3 l1 G0 I: \7 I935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC
# ^( }8 ~' z2 H- M$ n! {. v+ e4 W. p945393 FSP OTHER group contigous pin support enhancement, k- }8 w, J" a2 Q
969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database) C) g" M5 K; a! C6 q+ d. D
1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes0 W/ y2 F& V# n% d! P) K
1005812 F2B BOM bomhdl fails on bigger SCM Projects; A$ ~! d# J! g+ x
1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture- i) ` R j9 Z1 |
1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names, q# E+ {* T/ V
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net A) Z" q# e$ V8 q, A' {
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical7 V& n! j+ x4 O: F7 ~ K
1032387 FSP OTHER Pointer to set Mapping file for project based library.
) \7 E9 Z3 O6 N R) d1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with ї LL PLL_3 does not exist in device instanceї
5 c9 Q6 O3 U4 m8 l* a1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
I( \, z, b6 a1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding
" X Z7 U9 C: X! D, V1 h! L( d$ O1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.
) G- O( O3 T) J9 u. T9 ^1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type
1 R) s9 }4 E# v0 s1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll3 X8 S9 }' J/ `! I
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation
3 }1 @) E) X2 @2 c5 t) h3 @1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects
& B4 E5 B, s4 t; f# t- d1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus
/ ]( ~' t! C0 V5 g: m6 G1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts
) x; u, D% I/ r4 [9 ?8 s0 I6 h; O; ^1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs
3 ~1 K6 t2 v0 c( l, ]1065636 CONCEPT_HDL OTHER Text not visible in published pdf
$ Y& R A) D0 z* ^: d3 T. ?1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings4 O6 @$ R( Q: z7 V6 m) |2 m8 _
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary
5 f: I1 _4 c; }- f9 ~) f. D# E. t1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts+ \5 @* ~0 O3 x& I
1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic
( _0 [+ Q( U3 I6 w) t9 ~1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down& O- j* @ h t! J+ h, h
1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45
) ~! J3 e0 t9 s8 ^( u1 r( @6 h1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal
# Q0 B; E5 m# G" ^+ n* I+ f1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
8 v. h. Q$ ^, v1 Y1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design. [5 ]$ v1 v8 \- P8 O. k5 g9 Y
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)8 {( I) f6 Q- ~' G
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die
* k! |( x5 t) @0 e1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic. T- J* l7 Z* x9 X. E! s& N
1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut/ V1 G2 Z( K! \+ s% l
1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects
+ |* ?, t, u$ c5 A- m% F1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format( U: |! n# `1 ^8 e% t
1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net
9 v/ o: F+ n$ U0 ^7 _ E! u- [1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
+ Y0 x: ]0 X* ~: A1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
# S& d" F" U0 A! c1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.5 X+ a3 c& E6 ~, h3 f
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.0 K5 w- I1 w0 [: M! t
1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors4 ]5 W% J, @& l
1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.
) L" Z g2 u! U1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition0 J8 K6 ~0 M6 p# |( D/ K
1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor4 N0 D; H2 f$ l
1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options) `% z! A. ], D/ D1 y9 [
1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.55 Q+ A) ^2 ~( `) M
1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.' @! j# q5 o3 q# |
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate! K3 x1 R6 K+ o8 p
1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3
z0 X! k* W. d7 e M1078270 SCM UI Physical net is not unique or not valid
5 c, a% T# F. P7 c1 Q$ E2 K1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted
6 ? u" `6 Z5 v, F. l _* W1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle7 K. }6 B/ \; |- y
1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs
5 [& ]- `. ?' ]5 L, N# J1 E1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage", m! D, b; q* M2 a$ v& E$ [. i: `
1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters
. g) S- M; Y' m; t1080336 CONCEPT_HDL CORE Backannotation error message ehnancement5 i' X: B( n: U! ~3 Y2 a" x
1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using orcad license
6 } N7 c; f2 f( g1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd
7 Q2 x1 d! j* n1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error
3 U: h: H" X; s' N9 i: r1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated. v. d+ m8 l$ s8 O( o6 k' j6 |
1081760 FSP CONFIG_SETTINGS Content of їFPGA Input/Output Onchip terminationї columns resets after update csv command
) Z3 N1 V6 |) i, b# F1082220 FLOWS OTHER Error SPCOCV-353
" _! q3 B- [5 b. d+ ?, M: e6 x% g1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.: _2 ~' k" F8 S# Z! p- E6 x) G% X
1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command+ C: p# R( \2 j. {4 Q
1082737 CAPTURE GENERAL The їArea selectї icon shows wrong icon in Capture canvas.
% X: O d* o9 ?/ e1 N7 [/ A1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name
e% B0 v6 q7 t: P) X( K1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way6 f5 K2 A; u9 {
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher, @* u+ ^( m% i
1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI- `; j" s( }4 [+ m$ O0 \+ Y, c ^
1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file$ r x/ S7 H. j# o* q/ i
1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.
* I" N; `' M" _; n( J1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates
* K7 F& [& l3 V7 i: l7 d7 E: o1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters/ _" J5 Z# L0 x, x/ A3 O
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes." H! @& X, F8 W. e" s
1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results
8 @2 r! c. p, O4 B& q$ C+ Z- P1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.
# h& X$ e) S N+ [1085891 ALLEGRO_EDITOR INTERACTIV about DRC update
; ~/ g% V5 _' d& R v) s1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO
* d4 d3 X3 e2 E9 a+ w. w: k6 B: V1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working! L5 i% C* f+ |0 N* g1 _* V
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.
3 D: _! z+ N# g" A( b4 P1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design6 u2 F5 k: Q, H9 ~* d, t
1086749 ALLEGRO_EDITOR mentor mbs2brd: DEFAULT_NET_TYPE rule is not translated2 `5 A3 Q3 e9 T l; m7 x% K; e
1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins+ h _) {* q0 s2 l$ Z/ Z8 w# ]
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity
L" s: ^0 Z, U" N0 T1 h1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.9 I4 x X+ g% Z5 F' z( a
1087221 CONCEPT_HDL OTHER Part manager could not update any parts.
# b6 l7 }: u0 y4 p6 Q1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space( D, ]- Q- e; f) R4 |' x* `: p
1087295 SIP_LAYOUT EXPORT_DATA Enable " ackage Overlay File for IC" for concurrent co-design dies too3 n4 K' p+ O# M1 Z5 {: e) g
1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice$ S' z, w1 s+ _0 A
1088231 F2B PACKAGERXL Design fails to package in 16.5
0 Q8 j0 g) z5 H3 ^1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.! x4 _) O* G0 Q% D
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor9 q+ o% V* P9 _$ j' n! g& \
1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager" I3 ^& I% j3 \& l0 U3 G
1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?7 l% w4 Y! M# [ |5 m' q! e( C
1089259 SCM IMPORTS Cannot import block into ASA design
% m; Z( ?% u& D, T7 P1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form
+ H# M- g( \: X8 R1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project' t) x# P1 _6 W" R8 {
1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory5 P$ }: u3 ~' b) M( `; K3 D0 Y4 ?! X
1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
' u/ N! u; B9 u9 c# v! u7 h1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165
4 R) ?" N, g: t; J Y1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.
! s. n1 d' {$ Y9 h. D" [7 w" ?1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22
- w9 m+ N4 I6 q. H4 R1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.
5 C& p7 ]0 }- c- x1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
- Z- |. V( [7 a5 D" S) E1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled% n' T/ {* M- j$ x- W% s
1091359 CAPTURE GENERAL Toolbar Customization missing description$ c2 ~4 w" L$ M9 a' z% S
1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive, }: K# b# f0 f4 [* L
1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time+ r' U k/ G7 r% T8 V
1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5 C- e# O! ?) ]! r0 [ b
1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design: b. v: Z( D9 C# J" @. D2 G: d7 o% J
1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled ^: P" L- q8 V6 c
1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters- E7 b, Q( e' B) Q' E
1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error
. d( c. X# g' c% ]5 y1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder! I ~5 a( J1 A! e ^
1093327 CONCEPT_HDL OTHER Getting error SPCODD ї 369 Unable to load physical part in variant editor/ C3 a% E8 Q8 n; L
1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.7 |! `: N: z: u5 i8 X5 k9 I6 b
1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time( W/ G' d3 @: R$ Z3 A' q
1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.: n! K, ^2 n ^; c+ h- _% j
1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?# q% ]+ V/ K1 n1 o- z6 f5 h, O* T
1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic5 X7 V1 ]' y, C" H5 u2 N6 b# q
1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5
) X; K: s z1 h9 Z# z1 H5 }1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet+ c. k# k) b/ I
1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die: c) d2 Z2 ?4 q/ R/ U6 Q
1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block% p/ L w, L+ r& n
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3" d9 y. @ z6 H9 x6 h: K
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results
- R3 ?/ P; V2 r1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import
- I: N+ x5 f/ R. ?* V. R3 W1 u1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
p' f$ q8 J1 y6 M1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias
3 c% \$ m. D" }3 P5 F; ^1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate
+ n$ g5 {3 n9 O% T* j! ?/ }( I1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
. a, d. R# c/ O0 K! ?+ g. z; g! \% P% l1 l1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL" j/ K! A# Y. d) Q
1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.7 ?+ [1 s* i- c+ q
1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side
5 B* O* L" G, R+ Q- p1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command; m+ m8 T% C+ Y* ]' L
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.. Y' R! K y/ b/ Z8 V' W
1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives% {0 w, y1 P9 W# i0 f
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork8 R2 _* l* M" e) \% R) x
1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts
! _" \* ?! u5 A) n6 Y- X( M1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy" g) B. }- r! v/ y; j ~( V9 x0 v
1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.6 w$ L9 a @2 A/ p' P
1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties
" J1 z: C1 m7 A9 k. g' _/ t1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6/ h" j4 g& B6 H9 c5 `7 N
1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad7 @5 }8 ?& K$ M( V' k" I& g
1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3- H% H2 O' r: [$ o
1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad& k( N1 M+ w( ?
1103703 F2B DESIGNSYNC Toolcrash with Design Differences
2 Z: m5 [4 N5 N3 w! e' y( e1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view
3 U7 N& f; W7 _. ~% Q1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.65 ^, R, s0 `5 ^+ H; e
1104121 PSPICE AA_OPT ї arameter Selectionї window not showing all the components : on WinXP
4 u q* d4 y f9 u1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly f3 @7 @( @6 j) [0 e* b6 F
1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM" B7 l, ~9 y, x& }
1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.3 u( Q6 i# q7 y+ {3 @
1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.* l2 z2 A' W/ @! w8 [) G
1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form
8 Z( }- w3 w8 u+ d; ]1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part/ @$ J; ?* ^7 [( p$ H
1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked
: V0 d, z m8 a: u; A1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
% f3 ?8 j, t6 Y( D" v- d% }1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6
2 ]% @. ?+ l- _' G+ M: a. h' E* v1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only3 l) D" ]4 Y2 r! i: B
1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid
5 N8 s5 G. E# O( L6 z7 N1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.9 b- }- W: Y3 v D) m6 {1 i
1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param
/ Z. ~4 {$ Y% L, w' Z1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish
6 Z( t5 K) q( W* P( n1 J2 Y4 r! R. p1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).
2 F6 S) e0 \9 x4 n" L* v: j1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke. H; h9 u8 ]5 W& q6 j
1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad. @) s; J$ d0 w+ Y$ K
1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode
1 R. Q! N5 f0 \, P, Y v" ]$ l1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs' I4 S# h }8 s- E9 S
1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6
2 T; @1 w% b0 E9 b R6 E1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.# \$ c! ^0 A9 g) B: | [$ }# |
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON" \* v' F8 E9 z5 c Z3 ~2 o" H# z
1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6
- {5 @0 [" K/ O- Q1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset Z* y: x; I; s. t; y9 r7 W$ @* D- U& c
1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters
* E% o2 ^5 A3 w0 v6 Z% _1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend; y8 Y5 [; A2 y. s5 Q9 E
1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP
$ d4 b& n$ v1 G- ^1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint
2 p$ K: H# w6 ?% v1112774 GRE CORE Allegro GRE not able to commit plan after topological plan K; k8 U# p; y. X3 u7 V5 X
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.
5 ?/ g) U) Y$ U7 e0 _% L1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file4 P6 B* y3 u& [ Q
1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6
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