|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 紫菁 于 2017-9-14 14:38 编辑 ( ?: v1 x5 h: c: r, h. z
1 v# Q% W, D- {
DATE: 04-26-2013 HOTFIX VERSION: 008
: ~! z: q! K) x" ?===================================================================================================================================
' R' C( t' |: ] r0 c; }CCRID PRODUCT PRODUCTLEVEL2 TITLE$ @9 c8 l4 W9 B/ {2 T
===================================================================================================================================3 A) \4 `& a+ b) c l5 `
876711 allegro_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit9 h' K. p5 j. m2 m6 r
1080386 concept_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation, r: w8 v/ U* w/ N6 M/ j
1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device/ l, t0 L% M7 L) r
1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
* |: d- Y J' f1 z% v1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section D! l1 R2 Q+ f# K0 `; s0 d% m+ x! l
1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running% h n/ F) |2 ?
1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.0 ~$ w/ R0 N: M r3 s
1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence
: n4 k3 j) `8 D. A6 u b3 I+ _& S: l1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.
' E; _' ~$ s/ B8 @- U1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason5 r$ b2 s5 A! P+ ^. e0 p
1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.
7 M0 S5 f7 y8 t9 [1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?* a) D( q) z) o1 J; ^" S8 ]
1120414 ADW LRM TDO Cache design issue
/ _7 t s d/ [5 c1121044 SIP_LAYOUT skill axlDBAssignNet returns t even when no net name is assigned to via* ^1 ^' w7 I s0 T, ?
1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups
. }; {& S) Z4 o* X6 i! u1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it) L& g9 Z a2 s% A- a" o
1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.* x& m G' W# t* \# L$ j
1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced
" Q" r9 T8 o; Y6 x: I! t1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file./ E' | U1 Y5 ^5 n0 q- O
1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable. {( _7 a' [3 c: g
1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file
% c) ?& G/ O3 O1 w6 C" T4 O/ T1123816 CAPTURE PART_EDITOR Movement of pin in part editor: |6 J; p$ R q4 I8 [) d! `' ^
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50
7 O4 X% z* v- N* \0 bDATE: 04-13-2013 HOTFIX VERSION: 007
4 M+ {. ^2 D2 F9 M8 _ s+ B===================================================================================================================================
! {5 u3 N$ `' O$ LCCRID PRODUCT PRODUCTLEVEL2 TITLE( b1 ]( ] G5 R5 S8 v {' j6 J
===================================================================================================================================
8 `" f/ G- ]( V& I0 S1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die
2 C9 s% J! ~0 K$ a5 Z1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6+ O5 N2 t0 t o! n! ? J# D! W
1112295 APD DXF_IF padstacksї offset Y cannot be caught by DXF.
3 M* V! C0 g; g, o/ W, H1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components
7 s% d4 G$ K+ @( S0 z; @+ z1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
1 n6 J# x7 Q( E# k1115491 ALLEGRO_EDITOR SKILL telskill freezes command window F* M' R: ?+ C' k- t# @. |: f! i4 v
1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used. s( ~/ w4 _( o h7 N
1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.
- a9 f. ^- P {9 ]3 h ]1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear
1 g& V% g6 V* o: X* j9 Q) e1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks
' _6 d R) t2 P; ]1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?, O- L( _* j' }* d2 F f' q
1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh) A+ @; H4 q9 N6 Y
1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh4 H' E# V8 c+ W2 a9 E, D& {" I
1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors% K- G: f* `: q" g/ W* S( W- S8 {
1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6
/ w, n7 G5 A* D x+ _1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently
4 R, a$ R' d& |- g1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps; R# W9 U2 k2 k! Y; }
1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks+ f! B9 A) T, h# H; O
1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.
7 Z+ \, m, U8 W+ Z, \; Q2 c# g( jDATE: 03-29-2013 HOTFIX VERSION: 0062 q' H. w# H3 x1 {1 L) G k: B
=================================================================================================================================== R, ^% ~4 E4 W9 X, p U
CCRID PRODUCT PRODUCTLEVEL2 TITLE. Q/ W; | N* K
===================================================================================================================================
8 v3 d4 A- }: u- z% F110139 FIRST_ENCOUNTE GUI Error in Save OA Design form
9 K9 C: K% l! w; z625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.
' C: a! X4 ]: p: T \' I0 Q1 F' L642837 Pspice SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep% \1 k1 l; P# ~. P* w3 d" T
650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".8 Y: X. J% h* r) w; S' W
653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend, \; W( S" j7 i" o" a: z
687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect+ h u( u3 Q, |
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics" u N5 b; W. a% w
825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
2 } s$ F5 ~$ b% v! o" O1 X- X834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
7 ?5 T# t. f& R0 a) F835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
, q+ d5 w5 [3 `8 N: s: Q$ o868981 SCM SETUP SCM responds slow when trying to browse signal integrity7 E. }+ ^1 d2 u0 I P4 m
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide& O6 Y7 {2 P* d. ^6 @6 y* l( H0 l- Q
873917 CONCEPT_HDL CORE Markers dialog is not refreshed
5 [# T; m% M* [- a X7 S3 |9 \) s887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
8 Q( I5 Y, E: R888290 APD DIE_GENERATOR Die Generation Improvement2 s" o; m8 T2 Y( p# R5 k& p
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator" ]) {& p$ i, R
902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice
! ~1 G% B" t \0 M. b6 P+ l908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM/ x2 s# U1 L" z* I
922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols
$ r; x( r8 b4 E& J' D6 P1 W923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences7 v& {+ p9 Q! @6 a6 R: y
935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC4 A& ~% r! ?7 y8 `
945393 FSP OTHER group contigous pin support enhancement- ^( P& l6 n# m9 ?$ h
969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database& H$ f4 d2 P X7 x$ }( E, D" H+ ^( ^5 h
1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes: }8 g/ o; s' W0 T) J. U$ d
1005812 F2B BOM bomhdl fails on bigger SCM Projects
6 k( A( Y9 W+ a4 B1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture, G+ z/ q, M. w) f% a& k% E
1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names1 k- G: j/ X7 C4 r5 L% E
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net |: H/ m d6 \" g, f' A+ b6 l P
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical
) {- {- x% S4 [6 n7 [2 W& j. c8 U* ^5 E1032387 FSP OTHER Pointer to set Mapping file for project based library.8 r: [( W1 ^) |8 F6 c8 i
1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with ї LL PLL_3 does not exist in device instanceї
9 D0 Z# \& G7 [3 X. u1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
$ R. i8 l; G. T, }2 \1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding; F. X( {% X. ^( s6 N
1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.
3 _! D% S$ n& Q9 w" a6 y+ |: ?1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type9 O2 n, ^( w# f1 I
1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll i4 j2 d T, w/ ~ X7 p1 {
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation
; }, E2 _; j e6 e `1 e1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects3 m$ d( Q9 e: T: X/ M
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus
: ]( m( k: Y$ h& G, [) L0 k1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts& I2 v) c5 _( h S5 K
1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs1 q. \0 |+ ~ y" N( ^4 P
1065636 CONCEPT_HDL OTHER Text not visible in published pdf- z* e4 y; e: ]) L
1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings6 c0 L( S% `8 _- K" d; o) O/ w; Y
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary
0 q, o* [3 X% t1 x9 [1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
! h- o$ e" F5 G+ ]3 u& L* q% H3 q6 o1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic, b9 R% U$ K# T7 P$ R
1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down: m" i7 A$ `: c+ ?7 |6 H
1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45
* O5 V8 y' C. A. Y4 Q% Z1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal
2 Z2 D" V4 f! ~- W! F1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
9 y0 g9 q) B5 d! a3 e9 _' Z1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.
) A: z" H& V2 ` q: a1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)( y: b7 R- u6 O! H" F7 U
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die3 X3 c) T3 u0 g
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
. q+ E- Y ?) p+ h0 u$ Z9 M1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut
+ b) S+ N4 N. }) h# m1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects5 y6 b- F. y$ W
1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format7 N9 b, L& U; C
1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net9 S0 r3 L( T7 }' v
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
( B3 A! q" P( l1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
7 |& S, t( F3 n8 n# p% H$ }1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.2 l8 L' ?9 p' ~7 g3 ~
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.- k: Z$ E9 t+ e/ L: d L$ ^
1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors
- f# v8 C* d2 O- j5 w* b) B. i1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads." I" f4 C- w5 i- |- a0 a
1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition
3 U' K2 i9 a* A) A4 k2 x1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor
& z; e. s3 F9 Z3 W1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options9 f9 P0 q) \7 y3 N# U
1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5
3 D) s' N1 L4 K1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.
. g8 d6 m7 r: W1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate" j S& Q. A5 X
1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 39 ~' O( W( T3 S6 O5 X+ N2 `4 Q
1078270 SCM UI Physical net is not unique or not valid: i# D# f# Q: M
1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted
+ {& x( ^9 R7 p- |1 c/ T; h1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle
9 x' r! E8 N# b0 E7 \1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs
% I) r/ O5 G9 P0 G' |8 U1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"
! e8 u4 v7 A* g" D% o1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters0 Z: P7 W& A* h; q0 J7 H
1080336 CONCEPT_HDL CORE Backannotation error message ehnancement
, v7 u. ]5 I! D4 b6 V4 Z* K" P9 i$ ~1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using orcad license
1 w7 B! r* @1 I6 ^* v6 F1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd: {# b& ?# j2 I; ^" Z' k, g
1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error* |4 o' _* e% E+ M: g# V* A
1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.
; n) `& j ]& B) U1081760 FSP CONFIG_SETTINGS Content of їFPGA Input/Output Onchip terminationї columns resets after update csv command0 ]8 O! ]# y3 G* a: f
1082220 FLOWS OTHER Error SPCOCV-353; _ i/ R3 L j' a# `* F3 x+ {
1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols. a+ q0 B; O: z& E0 c2 |
1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command* z9 h `+ e) @! b/ N/ ^
1082737 CAPTURE GENERAL The їArea selectї icon shows wrong icon in Capture canvas.
* {5 U* L9 i) D& H1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name
2 ~5 B* X- s6 e' O1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way5 T* U0 E5 c% Z# L' k
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher
4 \$ O( g: [ F. F' a1 k0 B1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI: S+ c8 |- |2 s# y/ I
1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file3 t( A# b; ~1 c- L
1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.
7 a6 U; j4 @6 z+ Y9 e1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates) Z: l# J: h3 R4 A% K
1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters* @& {4 T0 E' ^5 w
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.+ u3 n2 l( r5 d% n5 k
1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results2 o% k$ K0 g" R' ?
1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.5 @/ B) \0 v' j
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update
/ t) U! {5 c9 I7 Z1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO& ~) [! E2 N1 H- `
1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working1 E, p8 T$ w/ |0 L9 `
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.
( C4 S/ V7 w2 d8 u; x1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design
0 E# r+ v. W/ i0 x7 K9 A+ A% O1086749 ALLEGRO_EDITOR mentor mbs2brd: DEFAULT_NET_TYPE rule is not translated( x' A8 q4 m$ E" x' U4 I
1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins
0 r" X. s5 E' Z- W4 V, O1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity
4 S D7 r+ c' C1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.
& E* D9 K2 h, Q( L- T! q) g1087221 CONCEPT_HDL OTHER Part manager could not update any parts.
0 e L2 @ n$ a& S" U3 e0 G1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space" O# V( o' ?1 M& B5 x$ Y" U# P$ a8 J
1087295 SIP_LAYOUT EXPORT_DATA Enable "ackage Overlay File for IC" for concurrent co-design dies too4 N& [( S6 t/ @% p1 _. z$ b
1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice
; p" C3 {1 G: f7 u1088231 F2B PACKAGERXL Design fails to package in 16.5
# a" ?3 P( `+ _5 ]& w7 X/ E1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.
8 U ?8 S2 a, b/ P1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor
' F! i$ h h* Q& u1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager7 M$ j$ W* n# [0 Z% b
1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?3 Y' r1 y. k- `( ~% F
1089259 SCM IMPORTS Cannot import block into ASA design
+ c. r. A) A* M/ ?. n& V1 P+ H1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form
$ V+ n6 E v7 G, N' Y1 C1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project! V% t: I8 D X- D, ?0 w
1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory
0 _" {/ A' H' F6 l7 b2 J( S( f1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
9 S# q4 | R1 v" G) f, g2 I& N7 S1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB1651 T" T) W3 T/ r; S( J
1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.% C, x3 B* b ^& e y
1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22: C8 T1 W$ ]. [
1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.
+ h2 N2 D9 ~! J. `1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
/ S7 ^4 F( Y# J4 E$ V1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled. Z4 Q t" }& F
1091359 CAPTURE GENERAL Toolbar Customization missing description
; |( w% G% }) |! @. s: c8 r6 g- s1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
X0 l4 E7 m1 U+ W1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time
9 m! {6 F) D' k/ M9 w# U( Z1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5& b9 R4 `) z' _3 g, f! |% h
1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design; W f; u% x' f9 J
1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled
5 @7 H% Z- R" R& q3 k/ _1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters
, r. \0 i, d% a* x# z1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error2 p; M$ V7 @" A+ D* F9 p# @9 Q8 Y8 H
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder6 h/ h0 a a$ g h
1093327 CONCEPT_HDL OTHER Getting error SPCODD ї 369 Unable to load physical part in variant editor4 z0 L# s2 F+ J# ]/ X/ r& a
1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
2 ^5 R: O5 {$ t( z/ Y' q1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time
* Q: I3 H: u7 `+ O) ^1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.
4 |# y2 c1 ~3 W% N1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
6 |" Y3 v2 y# f1 y1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic
2 M7 S# `3 d) B5 b0 ^1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5- E5 D/ {( T" u% ` e2 F
1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet. y! S+ X' f" q, q# p
1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die& r" i! n2 b4 h
1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block& N2 o) |0 O9 c
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.30 }& a4 Y% ]# v f, L: N& N/ h
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results
' a! Q* s$ p0 ^+ A1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import( L+ h6 n* F8 I
1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
; s7 u. P: R7 `" P/ g# ~) d1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias
4 W+ Y# \: L; U( m5 g1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate- X) q/ y: P1 R6 K6 i# k" p
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
/ T8 a2 M' w! `7 c1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL
) V$ d8 Q0 k1 A5 I# a; Q+ G1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.4 m: {) E) y- ^* D
1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side
( I0 U7 r. N4 L/ m1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command. v2 Q0 ?: ]" K; w; O! Q
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
) e# u" \, \; |! n G. i* W1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives J2 U! e; y m3 T" x; u& T
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork1 H, I( a* j3 O% x! f c% U0 P
1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts X& G; ]5 d5 g, [0 W) o
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy- d0 i- A) C9 |& l3 q( ], \
1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances." `6 `3 B( p+ ^2 G6 h
1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties0 m% V" w \8 m. u8 `
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6
% T7 F; H6 e1 X+ ]* U! n# G4 T: h' o e1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad! ~' p5 a$ l6 a* X0 V
1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
6 a, s2 u8 x2 k' X" u5 k7 B1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad
. S+ }$ e; y, W6 [. I- a1103703 F2B DESIGNSYNC Toolcrash with Design Differences
. a- G/ W K/ ]6 o) ?7 ~1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view
0 _. ^) P. N; i+ d* O1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.63 I+ T5 s& ?) Z0 u" V o9 b' A
1104121 PSPICE AA_OPT їarameter Selectionї window not showing all the components : on WinXP
" W4 C0 ]) I' o/ l. d. `/ g1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly3 B$ u. d2 A3 R% O v4 Q O Y3 r
1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM
4 D W9 q6 @3 y, z' K1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.
! c5 n6 T0 j0 s/ i0 D1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.6 T! X1 [, Q: ~( D! \5 R
1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form
" I+ [' T3 j0 C8 x- }6 X" [# W1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part
4 C- q: v" h8 E+ Y) }" _& f, F0 t1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked! Y. j: J+ E' _
1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax- j& v4 u0 T& @6 |) r/ F
1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6# S: n6 \. Q7 C& O
1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only
( T$ v9 o3 x1 s. Q. X1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid
, t7 {( L Q% B/ R5 s1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.
1 p, r% j0 F* Y9 _, R: H1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param
6 Q1 z4 B3 s) D: p3 H8 q1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish
f0 N& X5 x8 w4 \' ]9 K& M, R1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).% z. x0 h- k b) P- r9 s3 ]9 V
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke
' o$ P) a! ~. U4 b# s" V1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.) P" S2 ]1 ~4 q0 Z" P/ M
1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode
! ]! j* D+ E4 l# ?# C1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs
1 J( u1 X: J, y: F1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6
4 R8 g; R7 \5 R# h% c8 I1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.( S" @$ g0 M+ B7 l
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
4 B# H# Z1 x1 x) ^1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6
2 v0 Q) U7 e$ G1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset( K/ V& b h6 Y& K# n+ w8 e
1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters
5 l8 D2 A$ u3 q6 t2 j1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend8 s1 ?' a% i, ]9 A6 n5 q
1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP: R$ k" h; ^' i7 M
1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint
% t2 M! Y5 N" {. n& o1112774 GRE CORE Allegro GRE not able to commit plan after topological plan
% c) U- h2 Z: _: i; n! A# i; F1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.6 D: ?( c) E4 Q# [& p3 b' r
1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file" M2 \/ W8 X/ W N3 }
1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6
! f6 A! T+ {# E0 H |
评分
-
查看全部评分
|
/1 
发表于 2013-5-2 11:34
收藏
淘帖
支持！
反对！
楼主