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本帖最后由 紫菁 于 2017-9-14 14:38 编辑
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DATE: 04-26-2013 HOTFIX VERSION: 008
- k4 c$ l( i( w u8 N( K1 q===================================================================================================================================
; V, z7 o0 m, y. v/ [; VCCRID PRODUCT PRODUCTLEVEL2 TITLE& m/ p. a9 u. y- g- Y
===================================================================================================================================
& N$ j; l9 J6 q7 u) v( @876711 allegro_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit7 V9 B1 |0 [: Y/ k* C
1080386 concept_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation2 A1 b- |. F& D8 Z# p
1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device% ?3 ?7 i2 }) J, \! e7 A2 t
1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
( J" z& R8 `0 G9 L1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section
, g, X7 c5 N. j9 J1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running& P. s7 \* ~% S% @! a c, N
1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.
$ x' M% |$ |* V+ P, b1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence
( Q9 S# j7 @/ Z6 R2 Z/ |/ K) d, n% P1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.
8 w9 O7 {& m$ t) \' L/ s1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason" y9 K& s$ s: }# V# [' ]8 w
1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.
x3 r& t. N1 x/ {' M1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?( v3 h1 Q4 C. ?
1120414 ADW LRM TDO Cache design issue
- N8 u/ ~. w3 Q0 k# w' j; p1121044 SIP_LAYOUT skill axlDBAssignNet returns t even when no net name is assigned to via
0 E+ l/ o# G1 g# B. ^' R1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups a& Q* O9 Z& [
1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it
/ x5 n' R6 ? v" g+ o1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.
8 z7 g" \5 N5 F8 w) B1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced4 C7 a" p7 b$ ~) ^ G
1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.
, q# Q- C0 ^ f K1 F1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable
" q7 P, [/ J! Z8 J, _1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file
; N# p. U9 u& K1123816 CAPTURE PART_EDITOR Movement of pin in part editor
& ?1 F3 @& ?6 |1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50
y* Z* e S. m1 b4 CDATE: 04-13-2013 HOTFIX VERSION: 007! f6 [1 k( Z3 t9 }
===================================================================================================================================$ k& _1 P; Z+ l% w
CCRID PRODUCT PRODUCTLEVEL2 TITLE
6 e. J; f5 q/ f$ e) x! n8 V4 g===================================================================================================================================
+ P4 a5 {0 v( ]4 @3 m- O1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die
6 J T7 M0 M2 f6 G0 X1 O- A5 \: o1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6
& u' v$ B! C2 x& w. B. z2 ` E1112295 APD DXF_IF padstacksї offset Y cannot be caught by DXF.
0 \3 }. ^8 L& n' s, M' j1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components* ?# Y) O% s) S4 B# t8 s
1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly: z& S0 V0 m/ `+ T4 p1 A9 k
1115491 ALLEGRO_EDITOR SKILL telskill freezes command window
* R5 b& M( E9 p" J6 k5 v1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
" p }+ e+ _9 e* D; g# F C" ?1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.
5 Q5 Z$ ?9 T' \5 t5 [" \% r/ m1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear9 o; Z* G4 b# t `; U# @" o l
1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks
$ f4 {0 v* t3 J0 u1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?
* L( Z5 |. d# c! Y4 ^ Y) v1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh7 ]& h6 q4 K4 ~
1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh7 X/ P2 e$ p- D& H" A
1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors
) G& Q& _ \8 d4 y8 D1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6
5 ?2 k+ m; |) X7 B1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently
7 Z4 V) D$ W# p- q, X6 Q: I1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps( s) J! ]5 @% l! p _" U
1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks
% S' t/ v) X, }1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.- T+ {4 ^) T( d, ]: K
DATE: 03-29-2013 HOTFIX VERSION: 006
8 N5 l; i# O( z6 D5 F% }/ |1 T===================================================================================================================================
* d: L9 n* M" O: q( D( J" t1 t/ n/ {CCRID PRODUCT PRODUCTLEVEL2 TITLE
7 Q' Z' n" H. g f4 z===================================================================================================================================. }2 u# V, e7 `
110139 FIRST_ENCOUNTE GUI Error in Save OA Design form
& r' S1 S0 h: z. S: B" {3 O625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.
4 I* E; h. n3 c K" \642837 Pspice SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep
/ E8 w8 `0 t# Y: I D9 t7 i( f/ `, b650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".
$ ?+ H; W8 N8 w& S7 x9 K/ ?: S/ y653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend
& N+ l( _3 L6 E; `$ K" W687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect
6 {" N* h" y5 R% t787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics/ _" f) i5 `6 ^/ l
825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
) p) O" ]) q' N834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming. m. F: a5 s% B6 r, X$ e
835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
- A& h2 v5 b+ {3 q* ]4 c- T868981 SCM SETUP SCM responds slow when trying to browse signal integrity e7 y j$ z1 q; q+ s
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide/ f* G& z, [' }# N& M) _+ L
873917 CONCEPT_HDL CORE Markers dialog is not refreshed0 u- m0 L" g3 f& @) H- J
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License. X2 Z0 H b2 L& ^& n! @
888290 APD DIE_GENERATOR Die Generation Improvement
. W! p9 Q. P) \$ O0 w892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
4 d' }8 e) J. B0 r0 R) f( ^( a902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice9 H8 b' J) o( \2 i1 K/ R6 |: a" N
908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM
0 X. s0 T: r2 ?922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols
1 B- t( \8 Z# n% R. w8 ?923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences
+ w; E- h% {3 ]. C935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC
. p6 k0 _# e4 ]9 S1 I3 R% A7 w3 s5 Y945393 FSP OTHER group contigous pin support enhancement
: [+ A% }! |* K9 i ~/ ^969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database( Z( W% y+ D! H" F& \
1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes
2 o0 [9 U- g9 N L2 @/ }1005812 F2B BOM bomhdl fails on bigger SCM Projects
5 l0 N+ m8 `6 g" X: [1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture. r" C( s! M# G r4 F8 `
1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names& L+ R/ g+ o0 K2 a, e+ L- R' C4 X% |% @
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net
' O# P$ h' T& \7 J ?; b5 V1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical
2 H1 p8 l w7 B; a' @1032387 FSP OTHER Pointer to set Mapping file for project based library.( z; x& _' e/ Z! ?
1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with ї LL PLL_3 does not exist in device instanceї3 j$ A( V2 C( v# m$ x2 m- y
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart& C& I: B; |$ C) S% l3 L" Z T
1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding1 i$ d( h# b7 c$ e
1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages., x3 ^, l/ d# Y( f6 w+ G! f
1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type2 p a" j- Y7 R0 r& {
1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll
- Y5 |5 s, j1 _4 v* B- s1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation0 S( Z, c( x7 p6 b
1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects0 x; q; h8 E4 S- x8 ]4 k) r
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus
7 S; p3 x! I% {1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts& u- N7 K. l- I! S$ l, U- D( {
1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs3 i( }& a W; G2 y" e, \" ]/ h$ z' v
1065636 CONCEPT_HDL OTHER Text not visible in published pdf6 }/ |: R7 [6 _" ~6 C
1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings9 m3 ]4 E7 m. q$ K
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary
$ p3 }* K! u; x1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
b |! K2 f# r9 r& _, R1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic. O# N' |. H& ?) O7 g
1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down* X4 X7 Y" x7 u0 Y" }9 \/ j
1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45
/ C ]5 ]2 R! m+ O* K. H& s1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal
* r$ e; H2 \& w9 D; b- C# b' Y1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check6 K# L7 R5 p8 b6 s- F
1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.
; `; @4 C/ x* x! c- Z+ M1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3); P* J6 h0 ^4 I/ Y$ v A$ O
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die
; D( N" O6 q; O1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
( E2 p* E6 h4 a# d! y" c0 I; T1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut
0 E: U6 O; L+ |1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects; Z' b# Z+ @3 @) ^' Q* {
1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format
+ w, C4 g! I* l6 u+ G3 v1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net: g2 t: H2 S* R8 N5 D
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
/ V! J8 Q+ h' z1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
# `( b! {6 i/ u2 V! S( v1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.1 X$ D' v0 X V) n' g
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.( |* }, O0 L$ c; I6 `& D
1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors2 o* A& ~/ s+ b+ M8 Q1 O
1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.
B: h9 f+ W7 Z* T1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition# [: d8 W( r" o9 x3 i2 d, N/ Y
1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor
; e8 j- \/ }. z6 ]9 Z4 m1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options4 s3 B; ~8 o# T' c, W2 J
1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5* ?5 v% f3 y ~8 L! H( N
1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.+ ]$ s( A+ \4 v. ?" E0 c4 D. l
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate( Q+ c E' c) L; N
1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3
4 W s* C7 Y/ _0 P: \: O1078270 SCM UI Physical net is not unique or not valid
4 {* q+ Q) Z: K# j9 p' a4 |+ D1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted
. k- j1 D# a. Q1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle
3 u) j- i; x a, x1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs1 ?5 r; b7 o* s9 Y2 C9 t& e# I+ t
1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"
' j$ Q s: s6 O/ k+ Y1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters8 V' [9 k. i3 |$ n. {+ @- z w6 L
1080336 CONCEPT_HDL CORE Backannotation error message ehnancement; Y% u4 J% y }6 ^3 y
1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using orcad license
- g& a3 F, {" }, ~1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd, M6 W8 ^9 \0 z5 i, w: |$ q- d
1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error
) G$ i6 o2 D B9 M' \. a/ J1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.
5 {( c/ k9 ?6 `4 f# U1081760 FSP CONFIG_SETTINGS Content of їFPGA Input/Output Onchip terminationї columns resets after update csv command
" R! S! y" r+ X3 i7 c. \! G1082220 FLOWS OTHER Error SPCOCV-353+ U1 t- m/ V" T9 ~1 G8 C+ i
1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.
4 A" b) K9 ?% {3 M/ a D1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command8 Z2 k. P- d, Y: L. |! Q, J0 o
1082737 CAPTURE GENERAL The їArea selectї icon shows wrong icon in Capture canvas.
6 `* v: ^( \- t: M% H6 `/ [1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name" }8 ~0 u: r. S; }% ]' G
1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way) `# E, ]0 M' H2 F) J- ~
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher* N& E2 X6 `/ l
1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI
+ P/ d6 U2 ?% `3 Q% b$ R; x+ O2 I1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
& x: `2 e9 O5 i1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.3 w* S! q9 G* d( X x5 b5 \1 h& |# a
1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates
: F- p) S; @9 b2 x- O$ j1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters
: r8 U3 }. K& {; N+ O5 {# X1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.+ e* m* Y8 l* o
1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results3 Y' e0 M# {2 H* A+ T6 F
1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.
5 i2 |" A: n3 @" z, L1085891 ALLEGRO_EDITOR INTERACTIV about DRC update
7 @) W8 p% I, {. p& ~% ?1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO( W3 z" y0 G% r8 X9 n
1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working
- F. i+ Q0 P6 f: m; b* L! M5 Z1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.
W6 |/ y5 \3 D6 U8 D1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design
8 F! q5 f3 B1 @) T7 @& T% z1086749 ALLEGRO_EDITOR mentor mbs2brd: DEFAULT_NET_TYPE rule is not translated, y4 u% M8 ^ F1 t$ P
1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins1 i5 Q0 t+ j+ l, Q) q; E0 z" I4 ]/ J' ]* [
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity1 H" R5 g& |7 |% v4 l0 h: e
1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.
4 T; j% p/ w" S) `1087221 CONCEPT_HDL OTHER Part manager could not update any parts.2 H1 b& d% a0 O; [( b6 w
1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space' W( ^, Y( L9 `. k
1087295 SIP_LAYOUT EXPORT_DATA Enable "ackage Overlay File for IC" for concurrent co-design dies too
, i- n6 J" u8 ~! @1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice
6 F+ D; L0 ?, U6 Z1088231 F2B PACKAGERXL Design fails to package in 16.5
" r, R# J% P% h1 U1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.2 |( X/ x9 _* _& e; C2 u. X
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor) d5 o. }! A) q7 Z6 x
1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager0 p; e4 C% i' o, b
1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?
/ f! Z# x8 M2 J f$ e6 n s8 a" I1089259 SCM IMPORTS Cannot import block into ASA design
& u. K; a; o( p7 y& x2 m1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form
1 Q: C& p# r7 n3 E1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project
8 P+ f" I, K5 p1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory, ?4 i: W, D. w, _3 O! I
1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.' ]4 [! p+ P2 @$ z% D
1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165( ~3 Z# t) G7 U, o
1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.: z8 J1 T" v% z+ i6 V: C
1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-228 S0 B8 u2 R5 I2 g$ K
1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.$ W8 a9 y& r- {% ]& U! g. J) \1 n3 t
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.$ }. B7 ]- d% n* T) `: c! M
1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled* K1 o/ l* F/ F, } B j
1091359 CAPTURE GENERAL Toolbar Customization missing description; s7 G8 v' i' w9 Q$ _2 @
1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
- l! d, k! d4 H; Y1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time+ f/ \$ R7 f, U! |9 J
1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5
0 v; i s+ S- ]* w$ v+ p" H. j+ z4 `1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design
U, M& h7 x+ d' G% n8 E9 h1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled
8 X* [, v9 q* T0 U8 ^1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters3 M$ i' ]$ B( m6 v
1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error& q6 ?; } j# P. q) t
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder% V6 X8 s3 @+ r3 l5 q
1093327 CONCEPT_HDL OTHER Getting error SPCODD ї 369 Unable to load physical part in variant editor
4 j2 J+ N/ O9 L0 \1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.4 O3 d; b1 }8 b# x V$ K
1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time
! r( X' A+ `. U- E. R1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.
5 j4 G; F% @: L; j7 x1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
0 A, j( d: k: u; U' g1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic( R' M) V( s! C& g- m3 U
1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5
. o& I0 I) x2 _- F4 {9 l+ p I9 [1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet* b9 S2 a6 ]4 f
1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die9 q# H9 o# D) R2 x
1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block+ Z* N9 M4 G6 {( t$ W# r5 Y2 z
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3
. p, f1 ? I- I- y1095861 F2B BOM Using Upper-case Input produces incorrect BOM results& Y& a3 t0 G% G/ i. y
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import6 g. R; _) L H( ~
1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
! a$ T* D* C* _! F1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias
' I# @% H- X3 [7 O: ?! |1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate# n& A% R4 @/ R' @; f L. I+ ?; @
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors: o! V2 b! H5 w; D; D% Z/ @' ^3 U
1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL% o/ u, d/ Q0 h2 V
1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.
, e2 S; w2 I- ?/ B; p- h1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side; z9 n. m4 i# b d+ c1 j6 e. X
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command
4 r% @5 b c) x$ `+ f4 m9 F1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.9 l( X$ t" n ^( P
1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives
' |" ?; q( b' p5 W# _1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork
1 e1 v" h* H+ h1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts' ?) { N7 j5 t: M: q: T
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy
; j0 G% C* C' x8 w1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.9 @& E5 j" b/ a- ? f% N
1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties0 T! p% S0 c$ o; S% C; Q2 r
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6+ M& ?# ^9 Z# [+ b$ p7 h R, w9 [
1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad% u$ P1 [7 b, f+ O* t2 u
1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
4 m5 k/ e6 j$ ]' Z* \4 ?& \3 A& d# h& }1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad
1 m6 r1 ?4 d7 z4 ]( n, L1103703 F2B DESIGNSYNC Toolcrash with Design Differences/ o0 ~1 ~: c4 Q. J
1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view. u& s. s/ z3 `3 r5 c
1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.65 C+ z) u; ^( ~7 P
1104121 PSPICE AA_OPT їarameter Selectionї window not showing all the components : on WinXP
6 e* K7 U- Q% r+ `" P1 W. d1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly; d8 i! _/ H/ R3 N5 k( P3 Z
1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM& k* j" M9 a$ U# i0 r: F0 N; O3 B
1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule." R0 Y. w% z. c U8 R \
1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires." |5 @6 A1 h+ p# Q+ t% ^
1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form# ?% t- U; v% R4 T Y4 b
1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part
5 q/ m+ G1 {8 V9 m1 L% v4 n1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked5 l* V _4 K; T6 m; E4 k
1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
& _$ o' P/ D l8 R1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6; r1 l1 N& v: k$ q
1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only9 ~1 c- Z' h! V7 G3 D3 T9 l: {4 y
1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid3 ^6 _0 ]) E4 q: z, w( J9 A
1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.3 V. t+ V3 H2 N& t
1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param4 o% I6 |8 W; |8 J& l
1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish
% h! v0 X: _! d1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).5 |3 e, V, z7 z4 r8 c; q
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke" T8 f5 o9 i4 Z1 @& C. p" N
1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.
$ P8 h# i& p: [3 j5 U& |+ Q& c* S1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode; o7 y/ V# Z8 r' i
1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs
0 n- ?/ k* j" ~' R1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6
# D, o/ p {6 G% {1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins." t7 ?# E$ d( ?) j" Q" o: T
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON! x0 g( _7 y9 u3 n0 H
1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6' i) f' w; O- E- n, o
1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset
4 p1 n, j3 m* L! {/ v1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters4 I5 u: t# h. b% s$ }( v9 f
1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
0 A: V. W9 ^: E* w B2 l; ?0 s1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP
: N \3 B& a# m1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint
: f( Z, W7 @8 m8 j& a) d1112774 GRE CORE Allegro GRE not able to commit plan after topological plan9 `9 S& o, W0 V1 j8 _
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.
& Q' p# i) \$ J! Y- x9 ]1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file$ E: Z" G/ a& E" @
1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6
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发表于 2013-5-2 11:34
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