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本帖最后由 紫菁 于 2017-9-14 14:38 编辑 . X, }' I- H. y- b4 p
! Z9 v. m( B8 l2 S4 U9 y& u+ K& zDATE: 04-26-2013 HOTFIX VERSION: 008
0 E% [2 R; i5 }4 p" _7 U, Q===================================================================================================================================
- j' a6 W% G1 ~- MCCRID PRODUCT PRODUCTLEVEL2 TITLE
' h5 E0 c0 V) B$ V% H( C$ B===================================================================================================================================
: \! A# r D. {! g. b/ J876711 allegro_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit; ?/ O& p5 @* T" y
1080386 concept_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation
$ t" K- a% O" {4 [- J3 c1 r/ a1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device
. A) [" t5 i/ ]0 p9 m8 U3 q1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
* g- q* ^# c( S1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section# g* w9 F$ e( z8 y) [* {
1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running
- |8 ]1 o9 y! d( y$ W1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.
; V+ ]! \* y- T2 R1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence' }7 T! D7 s2 g3 C) `
1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.7 q- d4 X/ l: q, m
1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason
2 w/ N8 q* f! q* j- Z z; o3 f1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.
; B s8 g( o b( Z, T1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?
7 W+ _4 W- A; N: A1120414 ADW LRM TDO Cache design issue
0 H2 f( U$ @8 [0 W/ f. x; R$ V1121044 SIP_LAYOUT skill axlDBAssignNet returns t even when no net name is assigned to via
, ]6 |/ u; K; d# W5 g/ R1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups
: d2 x4 _( c6 _! c1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it
1 N. h6 [( J+ B5 k% `2 y3 q1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.
( b& E6 q4 I* f1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced
: V/ a4 i( P3 ~5 {, X/ x1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.
4 l$ w. _- e6 Z9 p1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable! ?, L, H/ L8 h: [; P5 |# y1 }* A
1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file0 ^/ _) {3 ~7 ?1 @
1123816 CAPTURE PART_EDITOR Movement of pin in part editor* t0 [- q4 ?# a9 Y. X( q
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50% s. c$ W; N8 ~2 |
DATE: 04-13-2013 HOTFIX VERSION: 007/ j$ v6 {- Z' ^, Z
===================================================================================================================================1 u, E8 R3 a1 z0 ]
CCRID PRODUCT PRODUCTLEVEL2 TITLE5 j" N; v) V3 p! F8 [; h
===================================================================================================================================2 P7 g- f: Q+ X
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die
6 W2 P: v2 Q+ Y$ m' R5 K' ]1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6
0 ?; u& q- y1 O: f1 x9 w1112295 APD DXF_IF padstacksї offset Y cannot be caught by DXF.
# d$ b* D' Y& t2 w" d6 m: `1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components
& v* K& C4 {% ^$ B' g$ k1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
7 r# u( _: u$ e Q7 h0 H1115491 ALLEGRO_EDITOR SKILL telskill freezes command window
. O* v0 A, E" ]3 i! ^" ?1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.+ \9 `) }) ?) n: o
1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.
' }8 f; x; x! @8 F* U# d1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear! O9 b7 M6 k* T( k5 y
1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks
' {0 `( _1 M) C, J: C" { r1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?
, P8 Q% [5 z' s' V0 C1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh: f, O. }7 G! R% ~0 h6 C* r
1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh
* b: e3 z0 F2 {0 S1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors1 P9 b# q& F4 g2 e7 }2 s# |1 u( m
1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6+ z2 B8 G) L3 }, c
1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently. e9 v; ^0 s9 F+ B
1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps9 t1 l. z6 d: B0 b6 j
1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks
1 o0 R2 F7 y5 p/ \( ^: c1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment./ F$ @2 M) V( M# c( ?
DATE: 03-29-2013 HOTFIX VERSION: 006! s- p: k9 [9 }7 g+ y* {
===================================================================================================================================4 ^9 K' M- S* Q' k% b
CCRID PRODUCT PRODUCTLEVEL2 TITLE
6 E1 V' y7 l+ f! q) L7 I===================================================================================================================================- f. U2 o3 c+ \7 h. m$ B
110139 FIRST_ENCOUNTE GUI Error in Save OA Design form
6 {+ l. w; {) i: F; J; F$ ~ m4 ?625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist./ e" v8 t3 ^! D+ o" o
642837 Pspice SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep
% ?7 E' j0 d* N9 j5 p650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".+ K. |, B3 }0 G8 _3 C
653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend
0 R- A7 \& i1 o3 F$ {687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect2 t A% b& }5 L
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
) I" L1 l& @, a; F: ?! p% _6 `825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other' m I3 ~* H/ _. ?0 Y, R6 B$ o
834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
1 S, D5 }0 j7 C9 x835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
0 V/ N, y1 t7 g( ^; b3 a# j l6 @868981 SCM SETUP SCM responds slow when trying to browse signal integrity
4 D" T/ S6 Z1 z/ q$ F871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
) O) f6 s$ L, W* B0 j* w873917 CONCEPT_HDL CORE Markers dialog is not refreshed c5 j2 I" Z% [! {- y1 `" \
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License$ @& _7 N% v6 z( L
888290 APD DIE_GENERATOR Die Generation Improvement6 n: k; i |- [8 M8 M- l
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
- B8 l( q2 m, c. l6 r902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice
% w$ U( x. n: h* Y0 k% ?908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM( h! j& Y/ G- C/ Q! A
922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols8 d" D8 y) ^; h
923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences
$ x, z5 R. W) f9 l7 L935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC: d6 l0 b9 L) R: h. v* X# ]
945393 FSP OTHER group contigous pin support enhancement
6 Y/ |9 S7 z% }969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database
3 ^) v1 P/ E+ S* n2 h5 s- [1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes
( S% n4 h6 U7 R; T+ |1005812 F2B BOM bomhdl fails on bigger SCM Projects; t: f/ _! l; Z/ v. h+ m/ I
1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture# Y/ n& w3 ^& S! W2 x- V
1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names# E% h0 P+ V5 ?0 }, f' }
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net4 n/ Q/ Y5 X9 `
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical
" \3 q3 A# B) Y7 t( V$ T+ \1032387 FSP OTHER Pointer to set Mapping file for project based library.2 Y& v( e" J9 _, {* t8 |2 D: I
1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with ї LL PLL_3 does not exist in device instanceї
' p7 C7 b0 l/ z% j+ w- j; f1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
) h2 n, c# u( ~( [; _2 l1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding2 y8 D R" E- m( F2 _! y7 U2 K9 z
1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.8 V1 h. p: f' I, h5 h
1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type; l: _1 A- G1 W* d& U' x% ^ @
1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll" t; v# B+ g. d& z, A g
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation
5 J2 Y) }/ Q+ `( ]) J! B* y1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects
/ ~* _' A9 J; L* R" j9 u, @' ~& M1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus! Z. h8 G- K0 D, A" H) U0 ^8 q0 [
1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts7 `1 n3 {! y# i) L. j
1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs$ K9 Z) U: Z4 b; A
1065636 CONCEPT_HDL OTHER Text not visible in published pdf# ]5 V9 _9 K) m; E
1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings, r5 ?) t( @) K: Y
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary
& d9 @! l I+ ^1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts! P- u: m" {" l8 l0 h1 h# J) D
1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic4 T# d2 }7 f1 x' @
1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down) d+ F' {7 D8 R& v, I
1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 456 s# ?9 V! I; V
1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal
" _) D& E, k) I, L# D! d1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check. k6 V% f$ e- A0 ]& `$ P" {
1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.. j' R7 B) g% l; k5 n2 x3 P# F
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3) M" Y7 }% i3 j7 g
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die
/ t" F, }1 m$ V2 m; v* B: m3 k# U1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
2 `* L/ f" v: O1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut; v/ M# Y5 i6 b5 N" \5 l
1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects
; Y& i8 S, e/ |! f3 z+ T8 b5 T1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format
- D5 q! o: R4 U' D/ c3 K2 h1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net# d/ i; A; }* T* L6 H4 J
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
3 b B" @7 p$ p) M2 Q1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
; S1 O8 M% k g8 b1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.) J t! s( L+ @# S4 B) d7 X# F
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.
+ t" h' s# @3 ]+ o( z+ Y1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors
4 K. n, S1 k. _1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.
8 I2 W a$ A1 B( _( _, S( Z1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition! G: R0 |/ a1 g# ^! u/ v- |% r
1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor B E) D1 T$ ~. v7 F; r* Z
1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
+ O) w. t' O9 z1 {" k- ^1 @5 r1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5' z7 Z5 n5 \# A4 n/ m( d# P2 c$ i8 S$ j
1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.$ _% |7 r, B$ i' o+ m
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate
0 I; g4 v Q# N1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3
7 Z4 N& [% F4 ]4 A1078270 SCM UI Physical net is not unique or not valid
% r7 |2 s* l4 x( B# C( y+ H: Z1 R1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted
) g8 ?% V" c! Z+ z* J% Y G+ b1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle
, a1 k+ D( { B8 S0 T$ v1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs/ f. C- t( ~; _+ c$ a4 T
1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"
; s& F+ y& }9 D! N1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters
) h" q3 K/ F- P/ w& i7 D% S( r1080336 CONCEPT_HDL CORE Backannotation error message ehnancement
9 @; c4 ~/ G+ z9 `7 r, ?1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using orcad license* s0 ]8 ]2 Z5 c [. s
1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd
0 s" l! G. M* u9 T6 r! r4 F1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error# ~1 y1 q* _1 @! L+ i
1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.% N4 R8 G! s2 n x* d/ t) ?9 I
1081760 FSP CONFIG_SETTINGS Content of їFPGA Input/Output Onchip terminationї columns resets after update csv command2 D7 i/ }! ~ s0 A
1082220 FLOWS OTHER Error SPCOCV-353
" N4 F$ N% s5 z1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.+ A4 W1 T- p& h) E2 I
1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command
, E, F6 A, N Y7 O1082737 CAPTURE GENERAL The їArea selectї icon shows wrong icon in Capture canvas.! y% j6 Z* V" v: L$ U
1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name/ J5 E7 r6 ^% q0 F+ h
1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way
& k* b; S1 z: X: @1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher) K: Q3 T* M% T" a- ]
1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI
, ^( W2 f* a" F% I1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file$ G' Q. V6 M. n X$ T
1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.' ^1 X6 {/ \( P5 z
1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates
* R2 y- y( X. ?% t! Q1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters% W* G* \5 q+ m3 A$ L. g
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.* g$ {2 M9 Y: d8 b% e
1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results
+ S8 E6 F5 `/ ]1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.6 u/ K: m+ ?2 b/ B* w
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update
7 F1 }% d: }3 L* C+ P1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO
6 _" D6 N% k6 {6 L3 Q& W7 G1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working
) {* V6 R3 Y' X* g& c9 Z1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules./ F. W6 Z% m, I2 `; k5 u5 r+ M
1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design
8 N* Z3 j3 w- D8 Q- R- {1086749 ALLEGRO_EDITOR mentor mbs2brd: DEFAULT_NET_TYPE rule is not translated
8 ]( b, V, X) D$ e! v1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins% d# F; K, R Q8 T6 Y
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity0 L2 w& Q6 W. o1 T* C
1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.( S9 \1 l; E, x9 [, a2 q8 p, ?
1087221 CONCEPT_HDL OTHER Part manager could not update any parts.
- [, e4 }3 @2 A3 r, U8 `/ W4 s1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space
& S T4 }* J! a9 Y/ e8 u1087295 SIP_LAYOUT EXPORT_DATA Enable "ackage Overlay File for IC" for concurrent co-design dies too5 ?! c" v5 A8 K t4 O
1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice
7 d/ A/ w" O: H6 ^6 p6 ~- t1088231 F2B PACKAGERXL Design fails to package in 16.5+ g7 C- b' d" h+ N( e/ ?
1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.
# x% e1 L, A1 ?8 I. F0 P# r1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor. B3 M1 _" L6 ^7 Z
1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager
8 g5 v' p3 b& [" Q1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?- V) ]. P; T) N& h! C
1089259 SCM IMPORTS Cannot import block into ASA design
4 \) K% I4 O/ n# V' n7 n1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form8 `* @& D w3 o
1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project- p5 s: P0 k) ?9 v$ C& P
1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory
' S8 c5 ]/ e7 V9 q; @4 j; A* r1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
! a7 J' P/ Y& Q) O1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165
, O+ Q" ^, f' u, ^$ u1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.2 n: ? X# F9 u, l4 P9 S
1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22 M+ U# P' p6 p0 U# e( x2 p
1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.( P" ^% i) n4 k& ~# F; W
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.& R! C6 T, H& M* m& i( j
1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled
/ k0 A, Z% W- J. g* _+ y1091359 CAPTURE GENERAL Toolbar Customization missing description5 |, M) T; _! ]/ n6 f
1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
6 e, m+ r7 J& m1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time
% F) W9 e0 i3 Q q1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5
( U/ M1 P0 A- ^1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design
' h- g+ O/ o, O% C1 a6 y# _7 l1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled, @1 w! _4 Y6 W5 _" Z# m! a( B1 _+ F
1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters
- o; g0 I; `- y8 N# C: a1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error# D& n2 i: R* P( V$ q, A6 e# O
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder! ~+ Y6 ] U9 R% {* w' ?- {! p/ J- }
1093327 CONCEPT_HDL OTHER Getting error SPCODD ї 369 Unable to load physical part in variant editor) r$ Q+ ]" _% k* J/ Y
1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
/ e' Z9 B1 J$ a* _6 A1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time
/ h0 i$ T+ W1 [* i1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.2 h0 g9 S7 O# S
1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?9 f! U v6 _+ k
1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic! D/ D- p, o. A/ B
1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5
4 q7 D( R: H5 V- ]7 k- [1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet
. }% b1 n, j( L3 |# T* G1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die+ H7 U' s! Z) ^% t% h- Y" W: {
1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block8 r7 T5 A- g% a! f1 E0 Y2 `
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.39 ?% e9 H& ?" S1 P$ F
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results( Z$ X0 }: x$ a. _5 U/ t7 t( ^# w/ g
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import) C5 X, r4 ?0 \9 V
1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically! Y' ~5 D* C8 I. d0 X
1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias7 l, N% b/ t/ b5 l9 n
1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate
" {. E# D) @6 y1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
$ K. c' p, p" ]& t8 w1 }! ~/ n1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL
7 F- x7 C, F. t, _/ S* |1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.% G8 E- t: K W2 H
1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side( M: n9 S" V/ h" z }$ v0 Z
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command
/ {$ M0 [% ~; h0 d2 D& m# {1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.9 B) Z a& ]& b. `7 k* d1 |) I
1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives. m9 _# w( e; z) @, U
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork5 l& w% Q" M$ e0 [: D, u* B
1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts
$ k9 |2 @. J/ I8 k3 p1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy
6 k* k! V( h3 L2 k/ v& x s% {1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.
& b, N5 u( |" ]/ V2 {1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties
. p5 q U. C: Y# q+ }1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6
* f& L6 q2 w8 O) z1 y9 N! ]1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad; Q! x+ V4 `1 P: X; i
1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
, Z6 g; A5 S2 l& i: B. M* W. J9 o1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad" Q/ J4 ^" e2 q) A
1103703 F2B DESIGNSYNC Toolcrash with Design Differences0 i9 v) p( g' ]. ^8 K' [
1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view
; H# u) W/ n2 m! R- m1 D x* P# ^1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.64 a' j5 {5 N C) V
1104121 PSPICE AA_OPT їarameter Selectionї window not showing all the components : on WinXP2 k4 F. K5 y; f+ |* ~
1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly
* O5 \7 C+ k) p+ W% c$ O5 k1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM
7 d" g& g+ h6 C+ E! N+ r, N# _+ o1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.
$ W- m- s" h* R9 g6 S% J( S$ h' }1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.
! ~5 s9 O, R; }; l1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form+ M/ Z3 U4 E+ [! _
1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part
8 d3 @7 f# V% y5 p) Y' ^2 u1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked3 c5 w4 ~3 q# `/ @! ? ]+ X
1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax* ~% I9 Y. r2 q7 Z, d
1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6 T' E3 l- x3 v) |) L: y* ^9 S" J
1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only5 H! e' x. @6 |
1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid* j7 ?2 G9 Y( W. X k; w
1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.
* m0 s1 b, L, {# m# \" N w1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param
( b* Q2 K- Y) F% C1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish [' |" U8 p- Y! o* V5 Z
1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning)./ [4 j* A- I, u- f+ ^" D
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke3 ]6 L. _+ v% H4 s! y4 l
1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.
# g- i4 J$ ?7 J( W7 E1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode
0 Q; S# @1 a/ g# o1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs
P* a8 e- U, O1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6$ m7 i5 G! I# \+ ?
1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.
) V" r' ?/ W6 s; z$ K8 r: \1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
( L, k0 f! M- ^4 M1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6
( K3 I: v: w* c! ?1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset
: @7 M- K, K# E V+ W1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters6 \! R- t# [/ o* x/ l: @
1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
8 e; r* Q" R3 Q# K1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP
! {4 O" c9 F4 c7 z% I1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint- T _3 q7 c- P; t" h$ B
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan: _0 H0 j9 y8 F( [* w
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.. R" Y9 ]1 o/ I/ @. s9 r
1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file
: Q% w, @2 D, ^- h( F4 ?, ^& B. Q' ^/ v1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6* T& h+ O7 d4 U4 w
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发表于 2013-5-2 11:34
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