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本帖最后由 紫菁 于 2017-9-14 14:38 编辑 # S3 I, B) \$ ?
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DATE: 04-26-2013 HOTFIX VERSION: 008
" W4 Q/ r! S. l, P8 X$ n4 z===================================================================================================================================0 J+ F4 O5 s+ u
CCRID PRODUCT PRODUCTLEVEL2 TITLE) ~; i0 T2 G4 v. C, N# p' f
===================================================================================================================================5 p. A& h; j; j& W7 ~4 O1 [
876711 allegro_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit$ T# X4 t; U5 _$ f3 d" |
1080386 concept_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation" }" P1 C9 A' c' c: w! p
1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device
, g- X0 |8 \4 X& b; h1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
4 ]. }/ Z" K2 ?& s# d# b1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section
' G0 r& }% ` E, E: D, Z1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running
3 j3 O b! Z6 |. X; }1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.' l- G9 q8 _# A5 |/ z" {
1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence
" f( s$ a, f7 u7 ^$ m, t% h5 l1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.) G9 U, G3 C9 a% {- Z8 i
1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason
# G6 ^9 i& d# {, s1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.2 w; ~ ^+ U" _6 {1 F
1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?8 _3 R% n6 {5 A' y# [
1120414 ADW LRM TDO Cache design issue
B5 e! ?9 t" `9 ~1121044 SIP_LAYOUT skill axlDBAssignNet returns t even when no net name is assigned to via/ s% O* V( P" z2 C7 ?2 U3 `
1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups
: d1 g |: q, P0 A- @' ?1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it# y3 R$ `5 P2 ` k: L" T2 P& Y
1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.
4 |% n0 I8 }0 x1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced. Q% H6 I9 }$ \
1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.8 ~( M+ K0 U+ I
1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable8 _6 {. Z' O& H/ g: d% z
1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file* h0 h' { x# L
1123816 CAPTURE PART_EDITOR Movement of pin in part editor3 D. P3 }4 g% F6 U
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50( O; M* H6 [, Z. J$ z
DATE: 04-13-2013 HOTFIX VERSION: 007
7 }4 X( d1 K1 N" A$ J===================================================================================================================================
Z8 S! X9 X2 c! GCCRID PRODUCT PRODUCTLEVEL2 TITLE: r2 t s) n) I$ S
===================================================================================================================================
) `4 d( A4 G# O1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die
: l- q T1 b+ c3 J5 u+ P% {1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6
' o9 X- m6 n ?& J) |5 O) h+ B1112295 APD DXF_IF padstacksї offset Y cannot be caught by DXF.
u1 }. w; E5 J6 A3 x- Z$ X# y! S1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components
! ?* Y7 g9 B) z- M1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
# ]0 c& D4 j# a& E v1115491 ALLEGRO_EDITOR SKILL telskill freezes command window4 t+ M+ @- u1 O7 [
1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.) m$ R' M, C' z+ u2 m2 T! E% S
1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.: c6 ?, b% }1 j* q8 W3 ~/ \
1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear! T! Q/ l. ~% G5 H" |* v6 X0 u
1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks
1 v5 L9 Q/ `: ` _; M: O1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?
. D% ?# Z. o- D$ C1 V1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh
3 ?; r- [3 R# L" t/ K: j3 Y1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh
( {( v# @/ g8 J: Z2 L+ |1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors" o! _' G: [( V f _1 z
1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6
) \. p( v) a1 k8 f3 k2 E+ j/ o8 n1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently
3 o& t, |# T+ f1 K0 t" ~1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps
, u8 F, {, v( ?1 E1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks$ @; q+ g5 ~" Q: y
1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.
$ r2 g& M& W( }7 E: W$ s& zDATE: 03-29-2013 HOTFIX VERSION: 006
f. s' u* |% y# Z===================================================================================================================================
: S4 m" E {, h( sCCRID PRODUCT PRODUCTLEVEL2 TITLE% K V* e. w0 h) e
===================================================================================================================================
8 k7 I& M% v ?2 M0 ^110139 FIRST_ENCOUNTE GUI Error in Save OA Design form
2 Y% A* A* \' X625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.
7 i j; k n+ m q642837 Pspice SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep. N0 u+ E1 Z0 [; y9 Q
650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".
; T- P& i. w; x, T c. J653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend# \- ]1 g& ^- T% J0 a
687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect
0 {6 N1 r4 h6 e: I, }) W787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics' ?9 R9 d8 J" b r1 W
825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
3 O' t, x5 k8 z834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
" s) P! u+ p: Q& R; [' F835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.0 V- h+ o/ C5 \; m7 j9 S
868981 SCM SETUP SCM responds slow when trying to browse signal integrity
" a" z4 k" [5 b871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
! I) Z' ^8 ~0 M3 G, i; J873917 CONCEPT_HDL CORE Markers dialog is not refreshed' K2 s H, \, y9 y6 g
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
6 d; N- w6 I; V% Y$ a888290 APD DIE_GENERATOR Die Generation Improvement
0 x( Y( ^. N: K3 e892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
: n* d6 i+ v$ Q1 [% d902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice5 i: N1 {4 I, B6 k O
908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM
6 m6 c% D) P! h922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols0 A- Q) C( Y7 J& d* g& [
923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences( C4 T' Y; g8 I# \
935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC+ U4 D8 n1 N9 I5 H1 }
945393 FSP OTHER group contigous pin support enhancement$ u5 g0 m. L- r. P$ k' ^! b
969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database
7 S- E) l. U1 V. A1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes
- V6 j8 g" j, A, n1005812 F2B BOM bomhdl fails on bigger SCM Projects& k6 O, F5 R4 N, m0 S" C- N# t
1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture, y4 a2 H; M3 K% t" x x. w
1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names, k" j1 m* K7 g3 \: r% @
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net
Y B* c( N7 K o* G! V0 m4 y( h) m1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical+ y, Z3 t- K; d! J6 b" a! ~0 u% q4 C
1032387 FSP OTHER Pointer to set Mapping file for project based library.2 T5 m l( p4 i1 u0 X$ j- I
1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with ї LL PLL_3 does not exist in device instanceї
0 k, D0 T2 a$ B4 e: i+ b: d. N1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
, n9 j# z, q- t( M$ K8 u1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding% V3 ?3 Q4 f$ a- u6 _% Q: c' D, E
1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.
/ k8 k7 r- ~3 T6 ?1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type+ z+ U/ v: M4 H, ~
1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll: m* u% P, g! Q; x2 G- U& f
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation
' c* `) i* {8 G; \$ O5 b+ E1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects
3 ~% S' j& ?7 C/ ^. l1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus( E9 `& }0 S0 P- H1 K7 v s
1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts$ e6 x. s$ t. t! ~6 G7 c0 q' p: _
1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs. m! r% O/ m z+ Q3 ? Z2 p
1065636 CONCEPT_HDL OTHER Text not visible in published pdf
0 Z3 n( i m e1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings% n, Y+ I& ~% F; c* l
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary+ K3 X5 q9 E: z0 e
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
2 `) R* J8 `7 Y2 O! V1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic! o& q1 e& V/ V& V' M# a! ~
1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down$ s- Z& s5 d2 {+ G6 @0 J5 q/ D
1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45# C, ]. ?! U3 f/ G3 ^6 }* s
1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal
1 P2 i4 P; d: A( H l* T. q j1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
& C( |) p6 B; }$ v) w1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.
! A; X8 G2 |0 k1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3); N: W8 G- l1 K# Z# M' B% C0 X( K/ }
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die
/ ~; a( i( K! [$ v; R) A/ y1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
m* r; f( h& P7 k1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut1 G+ _! E9 x5 j: F. _' q
1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects
! _$ j8 \) Z4 X" z t- P1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format/ {0 W/ z: q( y5 i1 L! D4 J b
1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net: e' q& d8 @- y3 {+ w
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic3 K$ T3 [7 k) k
1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible4 f" P3 g% U9 f/ g4 V7 T$ ?, v
1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.
$ P) m* d8 v2 ?+ b m5 F5 c4 I+ m1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.
# Y- Z1 E6 s$ F5 }1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors. b) ?$ E: b3 d/ E
1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.
! w% `. c- N( D* ^' K" Q1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition
+ O; ~. [7 h6 g8 f; Z! u. Z1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor9 \2 I' ?1 e" f7 L) E3 i% |6 t
1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
% R( c, d/ k2 K- F1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5
6 u X, s! O2 c; u- e8 k0 }+ j. {" I1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.
+ Y `" S# R! g8 [$ R1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate9 j' {2 [& y2 t9 z9 m0 }5 o& W
1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3
; ?1 Z Y) K" @. W6 ?1078270 SCM UI Physical net is not unique or not valid) x9 A, F, H/ z. ]
1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted9 i9 q f9 K2 e; g
1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle; b; ^: C w1 ?! \! W
1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs' c, W1 Y9 X/ a% o9 v# Y* H
1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage": v! J& N+ [* \$ v, f
1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters
( c& \5 W5 }! [2 Y1 J0 T6 @. X1080336 CONCEPT_HDL CORE Backannotation error message ehnancement0 S& K2 o! D/ y. v9 d
1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using orcad license
3 ^1 Y7 o2 O# E, T1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd1 U+ L* C8 x6 D. Q4 R) n# o5 D) {3 Z) |
1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error
. c2 J4 q% g+ V0 ~! P. {1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.% }8 |6 \1 P9 t4 v0 S5 S
1081760 FSP CONFIG_SETTINGS Content of їFPGA Input/Output Onchip terminationї columns resets after update csv command9 c' }# z- W3 E+ E: I8 r9 a, j; B
1082220 FLOWS OTHER Error SPCOCV-353
% f8 H* ]$ G; u+ N h) Y1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.
6 v" e/ Y! Q4 Y$ Y I1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command) F( D% Q$ J6 v" c% y, V
1082737 CAPTURE GENERAL The їArea selectї icon shows wrong icon in Capture canvas.
9 \: T0 D% V+ \/ p: X/ |, T7 f1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name
4 i z- ~3 {( ]8 y2 {; k1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way
# d' Z0 Y' ?# G, D1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher1 {, E1 } t/ y, x$ d4 p1 {
1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI
5 T1 |; k- ^. d9 |( R7 Q3 l! y1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
! g! @1 w2 q4 s5 [; F* {% N, b1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.
* O H1 f3 Y( f: d- P8 J1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates
+ x0 R" N. G" @ w2 M1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters3 t2 I4 D+ a: b) O4 I2 z6 ]* Z* W2 O7 w
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.3 F4 X/ ~8 C5 B% p( @( E% d" e4 e
1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results
& [' [: U. p: s L& A1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.
( ~5 ?0 \- p& i$ r' j1085891 ALLEGRO_EDITOR INTERACTIV about DRC update; [- o# V4 @! z1 y* t
1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO; B) z: B$ r/ f0 g6 o
1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working9 n! h {6 U. T
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.' M2 u0 w6 q- S0 m& X; u; u
1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design
5 E) C$ L" |/ D4 j1 }& A1086749 ALLEGRO_EDITOR mentor mbs2brd: DEFAULT_NET_TYPE rule is not translated
5 {$ \1 R, @& I j( G1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins
: H6 v4 C+ U* ?2 f+ S* B# ]1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity! G" Z/ t* A- V
1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.
& [5 O3 m/ @+ L5 T: W1 m1087221 CONCEPT_HDL OTHER Part manager could not update any parts.1 E9 G* H0 ]2 C0 a$ r( f6 G4 `
1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space
$ X/ T7 g; o' a# m# G- J+ a w+ }: t1087295 SIP_LAYOUT EXPORT_DATA Enable "ackage Overlay File for IC" for concurrent co-design dies too
, j4 \! {& e8 l! g2 }1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice8 ?( |' I+ Q5 T: b
1088231 F2B PACKAGERXL Design fails to package in 16.5
( m1 E/ l/ a x7 r8 K( j; s1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.9 N& ?% k7 A. _
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor$ t, e, `# G1 s: B
1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager' h8 B: M2 e/ n$ r) j
1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?
+ p2 w" {% L8 ~& d A1089259 SCM IMPORTS Cannot import block into ASA design4 Q4 [0 Q' N! a$ G% b
1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form9 j/ a& D$ I( s y+ i0 i) h
1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project
5 ^4 B: h, I! E A6 u( N3 e; C1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory
8 Y8 H2 v! U& l1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.7 [5 a) |/ `1 p- ], m) L9 D
1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165# N+ z2 M0 D% d( s; s8 ?5 ~
1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.! \6 v; P& V) u! S$ Q
1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22
/ S# m' G3 u; ]% q# M5 y6 v1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.
5 g6 w& M9 ?" L, B) @4 q1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
, s# y- t9 h4 H/ K$ m1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled0 }- d0 d6 R" F9 O( j5 k+ C3 o
1091359 CAPTURE GENERAL Toolbar Customization missing description% y: Q# d/ N% Z7 }; [% }
1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
( c, X r$ w* ^; i5 l1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time
) J1 Q2 n7 U, c' |" C& w1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.52 v9 r& Y, g% {3 S' X
1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design
) ?7 h7 d {0 g: Q1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled
B, ~! E" R; U+ _1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters
, W# G) M6 f* V$ G2 D+ [6 b% _1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error' k& w1 f& Y; ?- C* T3 ]
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder
2 }" _" m% G- y/ @1093327 CONCEPT_HDL OTHER Getting error SPCODD ї 369 Unable to load physical part in variant editor6 |- `! d+ }" \
1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.( p( B4 w8 q8 ]. T7 v
1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time8 L$ D% I& ?# m7 A* E
1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.
) L8 D3 n: _+ p v3 R! |1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
- Y. @# \. r0 y" {1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic7 q% Y9 o5 V8 F
1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.51 E/ ]( ~1 \5 b9 [. x3 V5 `
1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet
$ H* b" u: g% Z- N1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die( G% S6 O( L# J. i/ \
1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block
; C+ p3 L1 V: i6 H8 x1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3
! \. a Q5 p/ {, Q, R' J1095861 F2B BOM Using Upper-case Input produces incorrect BOM results' u7 p- X9 s' t" I3 m
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import
+ U8 ]9 W' N( p, V: J8 u8 x1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
* `% J* _. u: n1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias" j0 d7 D% L: E+ L5 \
1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate: F2 m: K: V. f4 L& B0 u _1 Z0 C
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
# i$ o1 n. h/ ]. `1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL
7 ~" w8 ~5 E' g( z7 N+ T' i B K( R1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.
# Q/ O6 j' y( X t) G. T3 P1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side4 H0 h; {, o2 } s$ |' D0 J- o
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command
# O; D' Y) u6 n$ F- E* M$ x1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
: t! U+ z- ^6 w' h$ _8 f1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives0 e7 x7 n8 H+ e6 ~7 z. `
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork# f' I/ N( H6 {
1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts
' V. y$ T- |# O: ]" ^8 b1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy
4 t. M) P5 N9 C6 p3 e1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.9 t# @2 \: G) ]/ A& h% n
1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties" w% e! D3 q+ B
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.65 y2 B P# E* ]4 ^* G
1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad
6 f0 P. V* \. \) j4 m4 H; D% c4 X1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
6 T& K( I4 k+ {) U1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad
. h3 O; r( _0 I/ u9 [1103703 F2B DESIGNSYNC Toolcrash with Design Differences
) h0 \3 ^: @: M0 T: l: O1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view# v, e9 ?; ^! }9 L: Q6 W
1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6
2 W, E1 [# P$ w& ~5 S1104121 PSPICE AA_OPT їarameter Selectionї window not showing all the components : on WinXP
3 z8 x- z8 t* m& `1 H9 j( p1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly
/ L) B- V4 m" L0 k+ n1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM
4 _% N. N" [6 q! j1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.
- K, [; U" ? Q1 |. R1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.
. e7 G( |( D/ {1 p3 a6 E1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form- o( X! t: r* [0 c. c
1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part
" O. G3 R- R8 W7 a! S7 P1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked
0 J. v( A& Z% r% _1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
0 A. Y- [& H5 A5 v' K1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6
; d8 Z3 ^+ r1 E) |* @9 N4 k1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only5 ^- s4 z- c0 w/ F: N# @
1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid6 D% s- x0 u0 a! F+ W
1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.! u' h9 V7 w+ m8 y. Q" q3 c* S
1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param2 z% c: y) o, c8 u
1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish5 v1 {& J0 J9 t8 l ]
1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning). P1 d7 p- a1 d0 X! J5 T
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke1 J9 ?3 w# M" Z5 P# }: |5 T
1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.
* X- U; ]9 P. `: N, @. e1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode O. j' X9 b% S& R
1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs
" l6 }' A9 m& H4 H1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.67 @: d* F4 S3 i) F- R9 o
1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.$ `1 x5 ^" J0 k8 Q! _0 [3 t0 w
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
' s+ u2 ~' f/ ^1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6
& \4 o9 u. C9 J3 c6 o1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset; p S7 f- M! u$ i6 ?2 m
1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters
6 f! }: D& W# W V0 ^% D/ s$ x9 l1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend$ x. ?8 g% r: S4 }1 K
1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP
5 k* r4 k* L% U# J$ D; Z1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint/ \* ]$ n& M9 d( C7 o- S d5 B, b
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan
. b; m& T v& y4 T: V1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.- m5 V& O' q% G/ Z9 Z7 ?7 N: M- Q
1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file4 j3 r2 p+ }% Q; o$ A$ N
1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6
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发表于 2013-5-2 11:34
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