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本帖最后由 紫菁 于 2017-9-14 11:21 编辑 6 [# e9 E/ ` z3 l3 K2 Z- f
* Q9 R2 C3 T& \' s/ g- V0 I下面链接是cadence SPB16.3及最新Hotfix下载地址,需要的可以下载!
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Hotfix057更新的内容如下所示:
. ?4 \' e$ {6 \; w& p/ R; ~DATE: 12-19-2012 HOTFIX VERSION: 0571 Y: X/ k5 p. r$ ~) I
===================================================================================================================================
3 n0 g2 D4 D5 C3 t( K# [7 P9 H! vCCRID PRODUCT PRODUCTLEVEL2 TITLE
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1 ]6 S5 S2 u& g3 }' J& w1080193 SIG_INTEGRITY ASSIGN_TOPOLOGY View Topology freeze during the extraction of the net connected to resistor network.$ S: H% ~0 g6 ^1 ~1 ?
1082509 allegro_EDITOR INTERFACES Export DXF in the 16.3 S056 roatate some pins.4 F) o9 y) P6 _
! g# ?) Q- \( ^! g( QDATE: 12-7-2012 HOTFIX VERSION: 056
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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825813 concept_HDL CORE HDL crashes when copying a property from one H block to other! Q" V& I' Q, ^* Y
871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash& o& u3 ?7 k6 ?& b5 \
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide7 H: `3 ?& M) A% p6 S6 {
873917 CONCEPT_HDL CORE Markers dialog is not refreshed" o5 _4 [' L- n: z5 P
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License: `. K9 @2 ^" i, V+ M5 N
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
- K) h' \& U2 f9 O2 R" z @1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
; x; Q% k- v- @$ z1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide |
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