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本帖最后由 紫菁 于 2017-9-14 11:21 编辑 1 Q0 x' n# G% b e
1 {- e: F$ Q8 A下面链接是cadence SPB16.3及最新Hotfix下载地址,需要的可以下载!
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Hotfix057更新的内容如下所示:
7 G6 W* q* t$ w' z* X' i8 ]$ f6 ]DATE: 12-19-2012 HOTFIX VERSION: 0570 f/ I+ {6 o$ Z
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1 @5 g& @* |( j. H/ f1080193 SIG_INTEGRITY ASSIGN_TOPOLOGY View Topology freeze during the extraction of the net connected to resistor network.
% ?, p5 S6 L1 K# Z4 x1082509 allegro_EDITOR INTERFACES Export DXF in the 16.3 S056 roatate some pins.4 x |) y% }; n0 H5 J( q& \
; x9 b( J6 l: c7 ~1 }$ PDATE: 12-7-2012 HOTFIX VERSION: 0561 B7 y- t" x' }8 c. g
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CCRID PRODUCT PRODUCTLEVEL2 TITLE5 q) R2 r6 P, `$ d# [- {; U! f
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4 x+ \6 X2 n! |2 N- g: O9 E5 E825813 concept_HDL CORE HDL crashes when copying a property from one H block to other
$ v0 r/ r9 |4 U871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash# C6 M# s) \, l
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide6 }, _' i$ E' g6 ~
873917 CONCEPT_HDL CORE Markers dialog is not refreshed
$ _4 H! R/ \( z1 z2 F4 j887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
7 B4 \5 i# [" `5 ^; ?892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
0 R, @# N* c$ q9 l) V1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic8 ]( o, i# G$ R7 ]; y
1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide |
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