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本帖最后由 紫菁 于 2017-9-14 11:21 编辑 * k0 w5 P. p& |
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下面链接是cadence SPB16.3及最新Hotfix下载地址，需要的可以下载！
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Hotfix057更新的内容如下所示：
, ] Z% T- ^; b' g( r% uDATE: 12-19-2012 HOTFIX VERSION: 057- P V0 }/ P- s2 x
===================================================================================================================================$ \+ F- [! r7 P' B" J- N
CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1080193 SIG_INTEGRITY ASSIGN_TOPOLOGY View Topology freeze during the extraction of the net connected to resistor network.. M; ?' J8 W( K) U
1082509 allegro_EDITOR INTERFACES Export DXF in the 16.3 S056 roatate some pins.1 ?: y5 E. D) \
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DATE: 12-7-2012 HOTFIX VERSION: 0564 x+ j9 c- i) c, k: D' F6 D
===================================================================================================================================
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% P6 e+ E6 F. A3 B; h) q825813 concept_HDL CORE HDL crashes when copying a property from one H block to other
! S- q4 j+ B0 a! w; ?9 W871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash
. B$ x, f( y/ K4 X- O3 B; W871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide: b7 l4 T7 ]0 o( e
873917 CONCEPT_HDL CORE Markers dialog is not refreshed
( ^0 F- _9 F- O8 f+ e. W887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License4 @9 g3 u: Q& J. v( r6 ~1 }/ a
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator/ F1 {, l$ X# r$ H. t
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
2 [- u7 d4 F9 _$ l# Q8 k, J1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide |
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发表于 2013-1-14 11:49
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