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现有DDR2的地址总线，在sigxplorer设置后T点之后更新到pcb中发现有一根地址总线add15没有加上T点，报警为红色，以下为更新工程的结果：请教高手原因？/ _2 q$ v' N! S, J$ F( s, R! u
Processing Net XM1ADDR15 in design S5PC100==V1_0" x$ {, h: N8 m. \- H; Q
Date/Time: Wed Oct 24 18:54:42 2012
$ F3 ?3 L1 }& Q2 I8 X. O% N$ d' K q& y7 P o/ _
Mapping Pins of Cset: DDR2_ADD_BUS
% N, w$ \: k3 B, J0 z7 c" [7 \Mapping Mode: Pinuse and Refdes
9 p2 `& I8 Y T; G/ l7 h/ O- N*ERROR: There is no net in the Cset that has pins matching those in net# 0 in the Xnet.3 B; X) j- [% [. X
1 O3 r/ ]# x0 J) ]$ Y( @: [Cset end point Group Buffer model Value net#! p, B6 g9 ~2 e3 {9 ^
--------------------- ----- ----------------------------------- ----- ----+ C" t- v: R* y2 X U: W. E7 p! U
S5PC100==V1_0 U12.D18 IO S5PC100X8A_081223_pvhbsudtartg_t_00 NONE 0. @ {7 R# A R3 J& H* I
S5PC100==V1_0 U4.L3 IO CDSDefaultIO_2p5v NONE 0% {; k' ~5 a# j1 r: u) ?! o @
S5PC100==V1_0 U5.L3 IO CDSDefaultIO_2p5v NONE 0
7 P3 r! x( ?; ~$ k2 h! aS5PC100==V1_0 NET.T.1 rat-T NONE NONE 0
6 D! n4 p7 B. Q
" e8 T" @0 J2 R/ L+ qXnet end point Group Buffer model Value net#% f( R T: Q* c. a4 [/ l4 O; `& e
--------------------- ----- ----------------------------------- ----- ----
& A% K; X8 _* g0 g& |S5PC100==V1_0 U12.D18 IO S5PC100X8A_081223_pvhbsudtartg_t_00 NONE 0
\* N! U ~' ~: N*WARNING: Due to mapping error, Min Tree scheduling will be used for Net S5PC100==V1_0 XM1ADDR15.$ q( S" `; `/ H% u& S
: f r" B: A! t9 |3 e$ m
Net S5PC100==V1_0 XM1ADDR15 Schedule: Default( ?2 X; ^! \# `/ K! }- e8 n' U% N
Verify Schedule: VERIFY( |; \; u' q* z9 x+ g# T, V
% l5 Z8 o7 g/ }: s5 H0 u( F1 @**************************************************************************
$ r$ G5 I* {& A! p& ]( w6 F+ i+ u1 v7 s# k
Processing Net XM1ADDR14 in design S5PC100==V1_0+ \+ i! D. X; I9 _. Y; N1 w
Date/Time: Wed Oct 24 18:54:42 20128 t8 g% o& n) _ ^
; [: A( x" H5 O% P' t a/ C: D `, J6 S2 yMapping Pins of Cset: DDR2_ADD_BUS- t; |2 X3 o- q( Z
Mapping Mode: Pinuse and Refdes) ?8 J s, O4 o, R9 e( z* ^
9 a4 d/ P3 m! M! ]
Cset end point Xnet end point mapping mode
# [/ M( F$ X; `1 L5 f8 ^3 U# F--------------------- --------------------------- ------------------: }' A" m2 j M9 t. c" j
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G13 Refdes " b) j8 a# v: d
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.L2 Approximate Refdes
, u. q9 Z' s4 W; X' m1 @ JS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.L2 Approximate Refdes" p9 o2 A+ A# U- o: }; O9 o0 r
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR14.T.1 Floating T-Point
: u { d6 ]% V: J( S, L( d* J& I" Z8 ], G
Net Schedule: Template Defined
$ u7 Z2 k. |5 H& Z( d, c7 L S5PC100==V1_0 XM1ADDR14.T.1->S5PC100==V1_0 U4.L2" r# n9 B* w4 T# L* B+ q$ @" J
S5PC100==V1_0 XM1ADDR14.T.1->S5PC100==V1_0 U5.L2& E4 w2 U$ i8 m9 D2 w7 }5 K+ W
S5PC100==V1_0 U12.G13->S5PC100==V1_0 XM1ADDR14.T.1
* H: d- h# d- i. N5 L: l1 ?8 N
& Y y4 V; @0 K% m5 s0 m$ m9 t- O7 TVerify Schedule: VERIFY
: ?+ I4 b; K$ c2 A" s, V3 }) G7 k9 ~# s; j4 E+ A
**************************************************************************
- }5 ^' l! n" P5 J5 T g6 n5 a; [3 p0 D
: j; Z/ {. d! _6 I. N3 Q" GProcessing Net XM1ADDR12 in design S5PC100==V1_0
) G( s9 [2 |3 h0 J0 l" dDate/Time: Wed Oct 24 18:54:42 2012
. S6 `, ]3 K, R) f3 D9 w5 W- f1 s+ L# ^$ a% S$ z
Mapping Pins of Cset: DDR2_ADD_BUS
1 y" S b; Y7 t. u' UMapping Mode: Pinuse and Refdes3 _0 }0 p' k' F! J$ e ^8 C
+ V' A/ n3 S$ J- `3 |) p6 GCset end point Xnet end point mapping mode 8 A0 Y( h2 l9 L8 N4 z" u
--------------------- --------------------------- ----------------, K9 u+ }8 D9 }# ~6 r( N; G
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G12 Refdes
: z4 y% f2 {$ o `6 y5 a K* q4 ^S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.R2 Refdes
" X. }7 p: ?7 b4 a( s# nS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.R2 Refdes
- k( T' E* B8 \( v3 MS5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR12.T.1 Floating T-Point; _3 ]' B4 y) O' s+ g6 R
7 _- N# j( Y# v
Net Schedule: Template Defined
; i; {2 L4 H$ n S5PC100==V1_0 XM1ADDR12.T.1->S5PC100==V1_0 U4.R2
" U$ ~: j* a" M& h# N/ u$ G$ ` S5PC100==V1_0 XM1ADDR12.T.1->S5PC100==V1_0 U5.R2
4 b% Y b/ @# b+ { S5PC100==V1_0 U12.G12->S5PC100==V1_0 XM1ADDR12.T.1
2 H3 j3 D- @' |& {" E1 @3 X& e' @. V9 j* n* ^; B' J
Verify Schedule: VERIFY2 ~; C. q! S& U* E* v/ c4 g
. [" p- i' Y0 Y$ [# `$ B4 i: h# `) M**************************************************************************$ x1 t9 K; S& v- U% E0 w
. _$ h% Z4 N( u( v [Processing Net XM1ADDR11 in design S5PC100==V1_0
" t" y# p5 C* v; k* r0 YDate/Time: Wed Oct 24 18:54:42 2012
, E/ R& o" F. A' g
7 o$ P; f; z# F rMapping Pins of Cset: DDR2_ADD_BUS; e+ C- m7 s& _0 R( o
Mapping Mode: Pinuse and Refdes
) I; l( ~2 e" v/ R. d/ q) z- K+ z% ~( k3 }% }+ D9 d. p: T2 h$ o8 E
Cset end point Xnet end point mapping mode
5 c8 i7 @. U% ~+ H3 J, K--------------------- --------------------------- ----------------( @9 A+ S. j3 P9 Y6 `! h j
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.H11 Refdes ! q- T+ m) h/ m% `+ d
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P7 Refdes
+ l$ V. R* Y) PS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P7 Refdes
2 d7 y3 X0 y/ w2 c8 B4 v4 rS5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR11.T.1 Floating T-Point
8 M1 k b- Q1 U% X1 _( N9 z" r
1 N+ |. A9 R) WNet Schedule: Template Defined
, K1 f1 `( K* d2 n$ c0 r S5PC100==V1_0 XM1ADDR11.T.1->S5PC100==V1_0 U4.P72 Y3 n- B5 e* a0 G! A0 C( P$ h
S5PC100==V1_0 XM1ADDR11.T.1->S5PC100==V1_0 U5.P7
- a6 `8 J4 _' G- g S5PC100==V1_0 U12.H11->S5PC100==V1_0 XM1ADDR11.T.1
$ x. o) A" r2 X1 e6 w2 I9 K' }2 T1 Q1 n9 d# f1 i( Z
Verify Schedule: VERIFY
* Z. J6 ?/ S( j: D# }8 v' E' ?% ^- Q7 _% w4 D/ f) t' _
**************************************************************************
. Z* Z! Y& e9 H0 F3 R; F; M3 d w( l
Processing Net XM1ADDR10 in design S5PC100==V1_0
; _) X; `& H' ^4 Y8 {1 E$ uDate/Time: Wed Oct 24 18:54:42 2012+ G$ [# F. W7 q
( X. y' G$ }9 \) G: M
Mapping Pins of Cset: DDR2_ADD_BUS; o$ M# B) _6 K! f4 R7 j+ `
Mapping Mode: Pinuse and Refdes. ?- E3 f, |! k( J! {0 L
/ S: X: j t. Y$ R! n5 u# KCset end point Xnet end point mapping mode # r) A: x( a+ k/ Z; ~* d0 d" B2 [0 V
--------------------- --------------------------- ----------------9 c d( u, c/ u! ~" ~
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G16 Refdes
- V1 c; @9 R) nS5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M2 Refdes
4 P$ u. I2 k6 r5 Q% US5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M2 Refdes 3 {" f# a+ B; f, W6 [& E8 ]2 X
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR10.T.1 Floating T-Point0 P I3 ]/ d" G/ `3 g+ m6 r) b
% A4 Q$ L# R8 [3 T0 S7 e+ [* KNet Schedule: Template Defined( }+ }: i* s( R
S5PC100==V1_0 XM1ADDR10.T.1->S5PC100==V1_0 U4.M2
/ G' F+ M" Q. w" b S5PC100==V1_0 XM1ADDR10.T.1->S5PC100==V1_0 U5.M2
" l& r: \$ f. Y- G) ] S5PC100==V1_0 U12.G16->S5PC100==V1_0 XM1ADDR10.T.1
4 C' q" O. G) F" t
% P3 Y: t7 G E4 ZVerify Schedule: VERIFY7 L. i1 n \- R9 h& o5 T
2 q1 |! b% Z! k: j7 L
**************************************************************************
' Q) V1 P2 x' I4 Y8 `/ p
. m# k9 B. n" n8 s& T6 u4 MProcessing Net XM1ADDR9 in design S5PC100==V1_0/ U7 l2 J4 \6 Z9 c: i$ t9 z9 I
Date/Time: Wed Oct 24 18:54:42 2012
# @$ l+ m/ z! u. W( w2 W$ l- J, m' x: C+ g: P- r" p6 b% t6 i1 G
Mapping Pins of Cset: DDR2_ADD_BUS# F# v8 C4 n! S. d: x! L
Mapping Mode: Pinuse and Refdes# v, x9 b7 r1 X+ H# r
$ U4 z" V0 D) Y6 P& t- F3 I
Cset end point Xnet end point mapping mode 2 n2 G1 I) j" o/ ~1 s
--------------------- -------------------------- ----------------+ ?0 [2 }: y! ^, w. G5 O/ x
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B16 Refdes
3 T5 {# l# [9 T. wS5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P3 Refdes 5 S/ h0 |) g9 j' ]# Y
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P3 Refdes
( d3 r0 I8 l) h2 S* RS5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR9.T.1 Floating T-Point# P( j5 m! L# m% d0 s
5 N* J, _5 @' i) C! S
Net Schedule: Template Defined
! O# }; U8 m1 I" S S5PC100==V1_0 XM1ADDR9.T.1->S5PC100==V1_0 U4.P3
. P( w/ ~6 J" J5 ?; u4 ^ S5PC100==V1_0 XM1ADDR9.T.1->S5PC100==V1_0 U5.P3
, M( Z8 E% o' ^, L! r, E1 z S5PC100==V1_0 U12.B16->S5PC100==V1_0 XM1ADDR9.T.1
2 d' i5 a3 l) r5 g, x; O- e$ A6 e) z5 f9 u) Y8 G, D' u7 c
Verify Schedule: VERIFY
a4 M3 N7 T5 n# ?7 @% `; M) x2 M
**************************************************************************; |+ V* i/ j, c% g
: J$ }4 @; O- GProcessing Net XM1ADDR8 in design S5PC100==V1_0
) J) H, D/ {0 D; X8 fDate/Time: Wed Oct 24 18:54:42 20122 V2 z6 l) Z+ z& |) _
M, \6 I% o- x w* }7 q! E
Mapping Pins of Cset: DDR2_ADD_BUS
8 r9 a1 f4 ?% l* W5 ?3 _$ hMapping Mode: Pinuse and Refdes+ F4 V1 |9 A# u; c
& y2 x* c( I4 a
Cset end point Xnet end point mapping mode & p$ b; I. X8 n' H
--------------------- -------------------------- ----------------
; H1 V: v% F9 n% nS5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.A19 Refdes
8 Z b. J6 s; J. NS5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P8 Refdes
4 X2 J( w) u/ M* q, kS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P8 Refdes
6 U1 @3 a+ L& M/ a" y8 H- a4 fS5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR8.T.1 Floating T-Point
4 B' d0 u6 k! ~/ s: `1 [8 H
5 _ e: h' @$ \' C* ANet Schedule: Template Defined4 [5 Y) A4 p$ W9 s5 I% ?
S5PC100==V1_0 XM1ADDR8.T.1->S5PC100==V1_0 U4.P8
1 ?4 W8 x7 [3 L! _$ d S5PC100==V1_0 XM1ADDR8.T.1->S5PC100==V1_0 U5.P8
. H+ @& W. N0 R S5PC100==V1_0 U12.A19->S5PC100==V1_0 XM1ADDR8.T.1
0 Q. e, w) x9 H' Q7 E1 k: }
& q Z% m- m& A- x) hVerify Schedule: VERIFY- Q8 C9 {8 a& k N, @+ k; ?2 y' p
0 y/ J* G8 H$ U7 v' |/ X3 r
**************************************************************************; g1 V0 z7 D3 |# U" J9 l, \
& o" a) V4 J8 |5 z f4 |( P& gProcessing Net XM1ADDR7 in design S5PC100==V1_0& K) n# V2 | c& v' R, N
Date/Time: Wed Oct 24 18:54:42 2012
+ X7 n0 X" N' B7 }
9 d* ]5 ^8 L4 A' g: L. ?$ eMapping Pins of Cset: DDR2_ADD_BUS
5 a& {8 v R5 S1 B$ [5 G; c. aMapping Mode: Pinuse and Refdes
( y9 }. F6 Z, Z' x: U+ c
d; H. d4 D2 [6 @$ a6 [5 ^Cset end point Xnet end point mapping mode , T1 S+ x- L( C k" B1 ^
--------------------- -------------------------- ----------------
- W4 s: Q* b7 q9 G* Z! h6 k# qS5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B17 Refdes ' H2 W0 v9 c3 k0 c" W) s+ j' M
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P2 Refdes
* ]/ p+ W3 j/ [+ wS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P2 Refdes & M# U; r1 E% U1 i1 u/ i, [! A( \
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR7.T.1 Floating T-Point
. Z. ?7 x1 i9 f9 L' u6 k8 b' i; c
; v. Z1 _# G' h/ ?* xNet Schedule: Template Defined
$ @& E/ U3 @) O6 e( l S5PC100==V1_0 XM1ADDR7.T.1->S5PC100==V1_0 U4.P2$ S* w) \3 a% C9 ~3 H0 h- v" K
S5PC100==V1_0 XM1ADDR7.T.1->S5PC100==V1_0 U5.P2
3 }* L# m! ~' q' Y S5PC100==V1_0 U12.B17->S5PC100==V1_0 XM1ADDR7.T.1
0 ? @; P4 ^5 Q+ E8 l4 ~0 Y z# `9 Y' l9 R& O2 K5 D# S9 d! h
Verify Schedule: VERIFY
4 a2 e9 F; X' }- Q3 k4 K* p& e: x5 `; V3 }0 w
**************************************************************************6 h: e4 W0 c6 S. V. a+ I% E5 k
/ \7 ^. w/ ?6 O: h/ jProcessing Net XM1ADDR6 in design S5PC100==V1_00 K2 r2 J5 b; ?
Date/Time: Wed Oct 24 18:54:42 2012
c* I2 X, H8 v( W/ i2 q* i, F$ ], Y. d! ?/ S9 i" k
Mapping Pins of Cset: DDR2_ADD_BUS2 K3 j: P$ G) Z5 X) M* N9 V
Mapping Mode: Pinuse and Refdes- L$ Q7 v* d+ u6 \- }' u
; z5 d7 g% w: I0 m; B
Cset end point Xnet end point mapping mode
. }+ X- ]* P( {& |, {% H--------------------- -------------------------- ----------------
$ k9 \$ k8 U/ L5 m# CS5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G11 Refdes
$ d' x6 x; h& M F! I) a! O& a# kS5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N7 Refdes
2 K( Z0 x) O7 T- q( g! S/ a vS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N7 Refdes
: R5 A; Y' X9 j+ u9 w8 ^6 rS5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR6.T.1 Floating T-Point/ c' Y4 y- E: Q! N# B
& q3 n4 W D( t! |5 O$ m
Net Schedule: Template Defined
& }- I @4 c K S5PC100==V1_0 XM1ADDR6.T.1->S5PC100==V1_0 U4.N7" F0 M" `. t& [* U8 x% T! I8 O. J
S5PC100==V1_0 XM1ADDR6.T.1->S5PC100==V1_0 U5.N7- ?$ D6 p% K! }- C* R9 W
S5PC100==V1_0 U12.G11->S5PC100==V1_0 XM1ADDR6.T.1& ?4 Y' o6 |9 A7 P% S
& B1 L G9 q0 k1 uVerify Schedule: VERIFY; ]0 E+ t+ G# E# e
' g4 E8 _" Y' B/ |+ e**************************************************************************+ I9 K: i7 C) R3 P; k9 ]2 K
" L, n9 H3 m4 s' f! o+ T# F* QProcessing Net XM1ADDR5 in design S5PC100==V1_04 f u0 W' y+ }) ^$ W& B1 K! e
Date/Time: Wed Oct 24 18:54:43 2012
! w' |0 h; R4 o5 R- K2 V1 x% e. A* T& ~
Mapping Pins of Cset: DDR2_ADD_BUS9 l0 |0 r" g! W! i1 x B
Mapping Mode: Pinuse and Refdes
" g4 }% g4 i4 ?6 K6 }+ b# q
" N( R7 X* I* b' OCset end point Xnet end point mapping mode 0 @' I6 ^4 X2 a
--------------------- -------------------------- ----------------
/ v+ q1 I7 X, L' p: AS5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B15 Refdes + h+ y7 X2 Y: h0 u- B9 ?
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N3 Refdes
" ^) @/ j+ p$ ]6 y* V' MS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N3 Refdes
Z: M) s) Y- ~6 B! i3 v. `8 G9 @S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR5.T.1 Floating T-Point
% J# _# p0 S! u) L& K5 ?+ F8 O- c S9 C; L4 W) _
Net Schedule: Template Defined0 C3 ?5 w8 O! N- a- {3 o
S5PC100==V1_0 XM1ADDR5.T.1->S5PC100==V1_0 U4.N3/ f( @8 t7 ]: |: z: M6 U9 @
S5PC100==V1_0 XM1ADDR5.T.1->S5PC100==V1_0 U5.N32 Y3 P1 E/ B4 _! \" E9 q1 i
S5PC100==V1_0 U12.B15->S5PC100==V1_0 XM1ADDR5.T.18 z/ d6 u% Z O' M
0 Y* g6 w4 H9 k$ V w2 [8 @Verify Schedule: VERIFY" @0 ?8 {$ v" R3 a
7 X* K0 o# u, Q) T$ f6 l**************************************************************************
2 f/ b7 ~' I9 T, ]1 A; B5 H% b4 j+ Q, v% n1 I
Processing Net XM1ADDR4 in design S5PC100==V1_03 m# q" ^/ K% r( Q1 f
Date/Time: Wed Oct 24 18:54:43 2012
* L( d9 ^: h" Y, p' o, M
9 S7 ~* `8 j0 R* C! \3 V/ v. cMapping Pins of Cset: DDR2_ADD_BUS4 s1 ^! N* i& X# Q3 y# x' @
Mapping Mode: Pinuse and Refdes& h c" R- k6 L
8 k1 N8 }' i$ k. x
Cset end point Xnet end point mapping mode
1 P- O) C! h/ b8 j9 X; [$ g5 H--------------------- -------------------------- ----------------- A: w. ?( p& E' }, g/ A
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.A17 Refdes % w$ A, M6 D/ s% m1 B
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N8 Refdes 6 H. {' ]$ Y7 o% _6 I
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N8 Refdes . H& n# S6 b3 S
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR4.T.1 Floating T-Point ?" t+ D/ h( ^
' _4 V+ {1 P5 n" ?1 {+ s
Net Schedule: Template Defined- V' Q0 `9 D) o8 X: [6 Q* y. f
S5PC100==V1_0 XM1ADDR4.T.1->S5PC100==V1_0 U4.N85 E% D+ R; A2 n! Q, H
S5PC100==V1_0 XM1ADDR4.T.1->S5PC100==V1_0 U5.N8) N% s4 k9 q; N" r q
S5PC100==V1_0 U12.A17->S5PC100==V1_0 XM1ADDR4.T.1, r. [6 G, O F$ v* b7 y" z# y
3 t6 o s K% m) {- E
Verify Schedule: VERIFY/ p1 b. h$ [$ O9 D2 [
, K' ~% J' a- _% v) l/ R
**************************************************************************
' r8 d. \( B1 n! @8 [
8 ?. i/ x8 O, w7 r% mProcessing Net XM1ADDR3 in design S5PC100==V1_0. h, h2 @8 \0 f. r- g. m5 V+ u
Date/Time: Wed Oct 24 18:54:43 2012/ V2 o3 q7 L9 d. n8 I5 Y
! B7 Q% u2 s: L ^ @0 W1 x5 G
Mapping Pins of Cset: DDR2_ADD_BUS
' C/ R5 [! h$ k7 V# g, wMapping Mode: Pinuse and Refdes
8 [% D' p5 v! `$ E# m% u5 d8 v! S/ U$ U6 j8 B
Cset end point Xnet end point mapping mode
4 Z2 K0 F/ z& N1 x( e--------------------- -------------------------- ----------------% p7 H" O3 M, o) C: v5 D
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B20 Refdes ; j7 N) L! W; X
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N2 Refdes
1 {. W! |# l/ Y, b4 ^S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N2 Refdes ; h1 t$ f; K$ m& n
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR3.T.1 Floating T-Point
/ B' M# @$ w4 o$ Q$ v% ?
! W& ]/ N# a) O1 z5 N3 m+ R/ R& ^Net Schedule: Template Defined% L) E! g z; ]* s
S5PC100==V1_0 XM1ADDR3.T.1->S5PC100==V1_0 U4.N21 R# M+ e# @5 e, _2 {" c9 X
S5PC100==V1_0 XM1ADDR3.T.1->S5PC100==V1_0 U5.N2
6 G+ ^% M+ x# X* v1 D S5PC100==V1_0 U12.B20->S5PC100==V1_0 XM1ADDR3.T.1
0 o+ P/ s$ A1 x8 }
+ l, F$ B# A9 a4 _9 s8 z( v' B0 mVerify Schedule: VERIFY
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**************************************************************************( G! [ `" x: p, }! y
# {, O ~2 U$ M x0 _( Y8 B( IProcessing Net XM1ADDR2 in design S5PC100==V1_00 y7 [9 t+ Y: r ?
Date/Time: Wed Oct 24 18:54:43 2012
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Mapping Pins of Cset: DDR2_ADD_BUS
# i; M) W% P% a9 p* t; R3 B1 G: W+ aMapping Mode: Pinuse and Refdes
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Cset end point Xnet end point mapping mode
# Y! r2 |6 F$ N) C* `, K3 c5 @--------------------- -------------------------- ----------------
! K$ L1 W0 [, J' s" [. GS5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.C23 Refdes
) H2 W, }( T) P6 uS5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M7 Refdes * f* {3 A8 R1 S) c6 \$ W
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M7 Refdes . |! k6 D9 [# Z: K; t/ u
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR2.T.1 Floating T-Point6 m: U+ q" k' M+ x4 C! l0 n
) D4 m* R1 C; C# W/ F% yNet Schedule: Template Defined0 B8 x- V3 ?/ z+ s" J' |7 R
S5PC100==V1_0 XM1ADDR2.T.1->S5PC100==V1_0 U4.M7
6 [2 r7 b- h) Z% i8 y S5PC100==V1_0 XM1ADDR2.T.1->S5PC100==V1_0 U5.M7
3 r9 F# H0 Z' J! h S5PC100==V1_0 U12.C23->S5PC100==V1_0 XM1ADDR2.T.1% H3 U. Y5 z5 H8 V2 j
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Verify Schedule: VERIFY- Z7 F1 z' Q+ D6 G# G& C
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**************************************************************************5 p3 D3 a2 d) p$ y, |
! Y, @8 i. U, Z* O6 b. ]$ \Processing Net XM1ADDR1 in design S5PC100==V1_0% o1 y* Q, z* U( P F) D
Date/Time: Wed Oct 24 18:54:43 2012' o$ v/ \0 c4 b l' D6 U
* P- v' j6 ]9 _3 A. I3 j
Mapping Pins of Cset: DDR2_ADD_BUS
! i: E7 \7 {6 K1 XMapping Mode: Pinuse and Refdes
1 X3 w0 Z7 z5 z, D5 \0 ~4 r- z1 @/ S) p: r5 _
Cset end point Xnet end point mapping mode , G) T0 h) J! f: H( s
--------------------- -------------------------- ----------------
2 N9 X3 n7 h M# O& r# C3 t# D6 [S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.C19 Refdes
" N0 S; D4 k* \1 ^: p8 GS5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M3 Refdes
/ e* S# J. A8 L6 K" c8 U& VS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M3 Refdes 1 j/ Q2 b, R2 [, `1 G7 A' |
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR1.T.1 Floating T-Point8 c2 E! d4 `: f/ K# L; K/ j! {9 X
+ S7 K+ f# h; _8 L
Net Schedule: Template Defined
# \% ? f7 B# J+ E4 r" W" p7 S S5PC100==V1_0 XM1ADDR1.T.1->S5PC100==V1_0 U4.M3
7 o0 {7 n1 P6 o% P5 R8 n* U6 L, \ S5PC100==V1_0 XM1ADDR1.T.1->S5PC100==V1_0 U5.M3
( V, @0 ~4 u2 C& O# Y: V. E S5PC100==V1_0 U12.C19->S5PC100==V1_0 XM1ADDR1.T.15 K8 T) W! J" b. r
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Verify Schedule: VERIFY4 O* b( A# x L& r, x
8 m7 c6 M' i4 r2 e; P$ F**************************************************************************
$ S% o! h6 D$ q8 l! t3 s
2 T( K/ n9 ^ ]( h RProcessing Net XM1ADDR0 in design S5PC100==V1_0: Y4 E Q, H/ J6 h
Date/Time: Wed Oct 24 18:54:43 2012) p- U2 @! L; u7 g% N
, p! \2 Q3 J& x4 b" w$ Q& M
Mapping Pins of Cset: DDR2_ADD_BUS
0 p& A, K# ]- M6 RMapping Mode: Pinuse and Refdes3 o; V- ~. _- W% T8 e# P, \5 g
& }) S9 z) j' F
Cset end point Xnet end point mapping mode
- o( A" U" q. r) j" R6 C--------------------- -------------------------- ----------------3 x9 @* r; k; M7 `
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G14 Refdes
6 Q7 @! p: e1 m) ^' T! @% g+ ~S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M8 Refdes
6 T9 m* D3 j2 F; WS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M8 Refdes
3 P* L3 N I- u# H. N; {" HS5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR0.T.1 Floating T-Point' ^: m" d6 I- f! n, \$ o1 P
R* ]/ h1 z, \) P iNet Schedule: Template Defined
' w/ S0 G! v- r, N( J# j9 S S5PC100==V1_0 XM1ADDR0.T.1->S5PC100==V1_0 U4.M8& f& q0 f) S: x* ]
S5PC100==V1_0 XM1ADDR0.T.1->S5PC100==V1_0 U5.M8- w9 r1 z) C4 t, K7 f* ]
S5PC100==V1_0 U12.G14->S5PC100==V1_0 XM1ADDR0.T.10 A' ~* u! ]& P- v: Y: s2 Q3 a
9 h+ e8 v$ n6 ~, W; Z' N
Verify Schedule: VERIFY
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发表于 2012-10-24 18:56
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