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各位大侠,在给DDR2做Relative propagation delay时,发现Constraint information中除了ETCH LENTH还有一个ZALL,请问ZALL是什么?是Via等的等效长度吗?谢谢……附对DDR2 NET的Show Element:9 w/ s9 }4 f Z2 E1 V9 A* M
" l5 U4 A) K8 KLISTING: 1 element(s)
6 R' Z7 {* W7 I8 r$ R- n1 r, ^
% F$ b) v+ ~$ `8 Y& ]) O: d# Y- Y < NET > % t/ n! I. d3 i' O8 d5 {
1 V" c5 T& B$ J7 t. i( x Net Name: MFPGA1_DDRD23+ ^$ U7 I) R- ^0 r4 B9 d3 G
Member of Bus: MFPGA1_DDR_DATA2. ~# q& x) t8 t' y; `; S! X
. W/ ?/ b& k0 T0 w/ o Pin count: 2
: r+ W. o$ t9 j6 P: j* a' N1 z Via count: 29 @% N- a& O! x" r5 l6 V. y
Total etch length: 1964.069 MIL
( j: y# H+ i2 J. l9 y- }( a Total manhattan length: 1135.851 MIL
; r* c' ^3 f% k; N3 p Percent manhattan: 172.92%0 ~/ w$ v" s* i& B0 n' v
& w* z9 c- F. _9 ~, P, e8 U
Pin Type SigNoise Model Location1 `! _' m( ]5 n' H# {; P
--- ---- -------------- --------
* Y0 m$ x( y( @. q1 o U801.F9 UNSPEC (-1984.000 6603.717)
3 {5 d$ q4 }' Q |; C+ L. v3 | U796.C18 UNSPEC (-2351.016 5834.882)
3 M4 H! p( f* \1 u( b7 W' g
. r' n0 ^/ `. Y& G' V# v No connections remaining5 s' j& o+ K7 j% M
6 a+ @, p9 W+ ~: Q* E0 V
Properties attached to net
: W6 {3 f e/ Q5 G! K% p FIXED
8 ?, o- _1 N) F8 i) @" u LOGICAL_PATH = @dw5vlx_all_20120504_1800.schematic1(sch_1):mf
: p# h5 Q1 ]! n pga1_ddrd23
& {/ y8 ]4 f; u) y( C. j BUS_NAME = MFPGA1_DDR_DATA2
" b+ d& r8 n0 G6 V
7 E7 L" {8 |4 t3 S$ ^# v/ J Electrical Constraints assigned to net
3 w+ r6 @. { } relative prop delay: global group MFPGA1DDR_GROUP_DQ from AD to AR delta=0.000 MIL tol=10.000 MIL
1 d4 t' F; a h) A, u3 J% c: J, M1 E! u/ z2 u1 M2 ^5 b
Constraint information:. B' e% u8 ?2 B2 o+ i. {* W# e- t/ Z
(RDly) U796.C18 to U801.F9 min= 1966.14 MIL max= 1986.14 MIL actual= 1980.741 MIL
I5 W; Y. Q; m target= (MFPGA1_DDRDQS3P) U796.G20 to U801.B7
; e, @0 I% A# ^6 h: d' O1 f9 H: S (-2351.016,5834.882) pin U796.C18,UNSPEC,TOP/TOP
6 b# X, {* a! ^. k 24.812 MIL cline TOP) h* h8 |( H. B/ M$ m% z+ |
(-2333.471,5852.427) via TOP/BOTTOM
0 i3 F/ M3 ]6 d+ K$ I2 g3 ~ 1917.397 MIL cline 03IS01
$ }; @8 p6 ?: T- P; ` (-1999.457,6588.260) via TOP/BOTTOM
' y# ?7 s# _9 k 21.859 MIL cline TOP8 O3 v4 e* X9 B- [- x4 O- S
(-1984.000,6603.717) pin U801.F9,UNSPEC,TOP/TOP,Zall=16.672 MIL3 v4 h1 }/ l$ y
+ X( e' B" o: n& Y' o Member of Groups:, [" M" w6 t, x% @# K
MATCH_GROUP : MFPGA1DDR_GROUP_DQ% g2 M% V0 e( S1 l! ^8 q! W
BUS : MFPGA1_DDR_DATA2% |$ E0 N( K5 M S
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