|
EDA365欢迎您登录!
您需要 登录 才可以下载或查看,没有帐号?注册
x
各位大侠,在给DDR2做Relative propagation delay时,发现Constraint information中除了ETCH LENTH还有一个ZALL,请问ZALL是什么?是Via等的等效长度吗?谢谢……附对DDR2 NET的Show Element:
# G3 |: \" i6 V( m
. T5 |, B" F" ?0 Z8 e7 F1 kLISTING: 1 element(s)$ ^8 ], J& D& D0 k" }: U
( ]( K$ p( @) Q. d, n < NET > " D, A9 t1 g0 S Y
. v( j) p9 W8 X% M3 E6 r) O$ U
Net Name: MFPGA1_DDRD23- L) S. \4 I- ~
Member of Bus: MFPGA1_DDR_DATA21 c5 {3 Z+ C3 R2 ?
8 d- M5 C6 T( o5 h; Z/ P! v
Pin count: 2
+ t% I. H* a* i6 s Via count: 2
# I3 V8 i& a) n9 a+ J1 u0 d- Z8 E Total etch length: 1964.069 MIL( H4 K4 t% X2 _7 ?8 Z7 m$ w/ {
Total manhattan length: 1135.851 MIL# b$ V; A6 z7 n3 e5 v8 Z
Percent manhattan: 172.92%$ [$ h1 M3 _3 G
7 h! M5 O% S! h( j k. F$ I$ G$ D6 p/ w
Pin Type SigNoise Model Location7 Z6 H; R3 N+ V% P
--- ---- -------------- --------- J- p! {) N# D
U801.F9 UNSPEC (-1984.000 6603.717)2 l9 L/ F, I9 W3 A# ^
U796.C18 UNSPEC (-2351.016 5834.882)
& [. ^8 H6 U7 J) E% p2 m2 N. B: p; [. }) k9 B# T0 c
No connections remaining
5 l4 Z: C1 c9 G! s, n5 o/ r6 O6 I6 e/ N0 |
Properties attached to net1 K/ S, W, l4 Q- `( L
FIXED
! H! |, ~( O( u( E0 d/ Y) V LOGICAL_PATH = @dw5vlx_all_20120504_1800.schematic1(sch_1):mf6 S, w, N: S# Z+ k; x# N4 @; F7 h
pga1_ddrd23: j, G" c! W5 L8 x5 `0 y+ M# S, @+ _
BUS_NAME = MFPGA1_DDR_DATA2
! Z9 I# S" B# f) t! n. n, w6 ~7 W( t6 c0 U
Electrical Constraints assigned to net" p. u( m4 ?& ]1 t: S2 A
relative prop delay: global group MFPGA1DDR_GROUP_DQ from AD to AR delta=0.000 MIL tol=10.000 MIL* h% ]0 W8 z% e5 g5 c: `9 v" G3 g
' n5 o" E3 j$ F# N2 ~ Constraint information:
: r, e9 f) |* I, x1 ^: h+ m7 H (RDly) U796.C18 to U801.F9 min= 1966.14 MIL max= 1986.14 MIL actual= 1980.741 MIL
5 H" C& I+ J6 X6 S+ |" \$ M target= (MFPGA1_DDRDQS3P) U796.G20 to U801.B73 S$ s. V l: {6 Z% I( M$ w
(-2351.016,5834.882) pin U796.C18,UNSPEC,TOP/TOP5 D3 K" {! N+ R* v
24.812 MIL cline TOP
9 F1 L% O4 o# g3 ^ (-2333.471,5852.427) via TOP/BOTTOM
2 w0 ] m# ~- e' I- D8 Z 1917.397 MIL cline 03IS01
# a: e' X7 H# U8 G8 P+ `. ~ (-1999.457,6588.260) via TOP/BOTTOM0 `# ~( p, }# T7 Z0 @
21.859 MIL cline TOP5 _/ Q# L- X4 B
(-1984.000,6603.717) pin U801.F9,UNSPEC,TOP/TOP,Zall=16.672 MIL5 y$ u2 x* e! j
! w3 \! b8 d4 X, m; \ Member of Groups:
$ W+ p8 U4 n: x8 b# h3 G MATCH_GROUP : MFPGA1DDR_GROUP_DQ
" j% b% ~' D0 B8 n BUS : MFPGA1_DDR_DATA2& B8 m$ O9 O6 f. A% m) H U$ ]4 |' B0 E* m
|
|