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各位大侠,在给DDR2做Relative propagation delay时,发现Constraint information中除了ETCH LENTH还有一个ZALL,请问ZALL是什么?是Via等的等效长度吗?谢谢……附对DDR2 NET的Show Element:
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LISTING: 1 element(s)
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< NET >
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* C7 Y' N3 l2 X! o/ @ Net Name: MFPGA1_DDRD23# P( L$ g- i; K) H2 J: J" x" Z
Member of Bus: MFPGA1_DDR_DATA27 y1 r5 m: Q/ C# Q
3 r% U* X$ }, t, G' Q5 i$ c: d Pin count: 2 ~) o5 t5 Z, g5 a
Via count: 2: e3 e8 s/ @, K3 U- b/ v
Total etch length: 1964.069 MIL
! o& _+ K5 P w Total manhattan length: 1135.851 MIL! N0 c. c W1 y, U6 L
Percent manhattan: 172.92%
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( b8 i) E" M. [% X Pin Type SigNoise Model Location
- h: V4 k& o$ \; y* \7 I' V4 I --- ---- -------------- --------
" Y# X/ B/ [8 U8 R7 Q9 H U801.F9 UNSPEC (-1984.000 6603.717)
! d4 @' N& q/ U5 T9 A- r U796.C18 UNSPEC (-2351.016 5834.882)
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No connections remaining
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; C% l- { H9 W' P0 Y7 i4 b Properties attached to net% ]+ |$ A/ B7 y6 }: B
FIXED
( K. M2 R# |4 X0 ], f. f) J, E LOGICAL_PATH = @dw5vlx_all_20120504_1800.schematic1(sch_1):mf
& y0 O2 j" k4 e1 u9 Z pga1_ddrd236 g4 O+ k. o3 w3 d' e; S% E
BUS_NAME = MFPGA1_DDR_DATA2
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! e+ `& I2 Z: ?8 j- g Electrical Constraints assigned to net- y" b/ A% i% [- ^2 P: E
relative prop delay: global group MFPGA1DDR_GROUP_DQ from AD to AR delta=0.000 MIL tol=10.000 MIL
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Constraint information:3 [- }+ h, }+ h9 |# V
(RDly) U796.C18 to U801.F9 min= 1966.14 MIL max= 1986.14 MIL actual= 1980.741 MIL% w4 q$ |5 n: G* Z$ M
target= (MFPGA1_DDRDQS3P) U796.G20 to U801.B70 T, G, Q4 d( u; G+ ?1 r' P
(-2351.016,5834.882) pin U796.C18,UNSPEC,TOP/TOP
- a1 x6 r1 \ U; G b) r% G 24.812 MIL cline TOP
/ v, C" N* y& m B. | (-2333.471,5852.427) via TOP/BOTTOM0 s5 L" \* f$ i
1917.397 MIL cline 03IS01, |" `' T7 ?: b9 ?. S$ L
(-1999.457,6588.260) via TOP/BOTTOM( N. H- n# w- O% H9 j6 z. E
21.859 MIL cline TOP
0 t! C0 Y/ x+ o: A (-1984.000,6603.717) pin U801.F9,UNSPEC,TOP/TOP,Zall=16.672 MIL) h' N, e, j2 J3 J) r- X2 f$ `) k
) X& l: [7 x$ G- ^ Member of Groups:+ `* v; ]6 W5 _, V6 C
MATCH_GROUP : MFPGA1DDR_GROUP_DQ. J( s0 \$ W2 k3 c# D9 y" T
BUS : MFPGA1_DDR_DATA2# J9 h7 Y2 G! o5 j: Z% h0 b
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