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各位大侠,在给DDR2做Relative propagation delay时,发现Constraint information中除了ETCH LENTH还有一个ZALL,请问ZALL是什么?是Via等的等效长度吗?谢谢……附对DDR2 NET的Show Element:8 r' M+ X1 e& h; f2 P5 y2 h
5 Z4 k r4 m' Z& D2 U" U- u
LISTING: 1 element(s)4 }, F i) x$ z. n' z! f r
* j: E% l6 ]1 T- e/ @ m < NET >
1 w1 w" W8 v. D& N+ K
% U: ]8 c( m) Z: _4 w) C Net Name: MFPGA1_DDRD23
4 [4 t; i2 w* P' `* O Member of Bus: MFPGA1_DDR_DATA2
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8 y( r5 t# O) o- r2 J. y: d% G8 q Pin count: 2 j1 z' c+ j2 {5 G% ^9 J5 l* d
Via count: 2& s. w( G( U* Y0 q# w, ?
Total etch length: 1964.069 MIL
; q( j# r) S- z9 o( c' Z+ c Total manhattan length: 1135.851 MIL
( \9 f3 ^3 l7 p% e7 l+ c% o$ X Percent manhattan: 172.92%& X$ }! \7 M0 q+ Y$ i3 N' G
- ]2 v( a+ b3 Z* l/ x
Pin Type SigNoise Model Location0 a6 o7 E( b! L/ }; D# s6 E9 C
--- ---- -------------- --------
! Z! _* }# l: i: ] U801.F9 UNSPEC (-1984.000 6603.717)
' ~& `! _# d! h ^# Z+ K: _. x U796.C18 UNSPEC (-2351.016 5834.882)5 \/ T: N% o$ @1 N) q
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No connections remaining# F" v; m" ~2 n8 x" _5 j0 R2 _0 M
W# Y7 w9 A7 v, G3 v
Properties attached to net3 H% Q; k6 }' l7 p" J3 L* x
FIXED
' t# U: v' y& B$ {' H+ b3 y LOGICAL_PATH = @dw5vlx_all_20120504_1800.schematic1(sch_1):mf
! f1 t$ N8 p* c4 U: G pga1_ddrd23
% f9 s2 U. T* f+ Z BUS_NAME = MFPGA1_DDR_DATA2
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Electrical Constraints assigned to net4 `2 p0 Q+ l" a% G1 B( z
relative prop delay: global group MFPGA1DDR_GROUP_DQ from AD to AR delta=0.000 MIL tol=10.000 MIL+ t$ Z0 r# j: n8 U( Y q
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Constraint information:% k/ [; k) \: U1 y1 t3 P
(RDly) U796.C18 to U801.F9 min= 1966.14 MIL max= 1986.14 MIL actual= 1980.741 MIL8 o4 |/ i& n M( E
target= (MFPGA1_DDRDQS3P) U796.G20 to U801.B73 ]8 x, u2 I% {- U3 f4 s
(-2351.016,5834.882) pin U796.C18,UNSPEC,TOP/TOP
4 j5 A! f$ ^9 ]1 S, `$ a, x6 r, ^9 D 24.812 MIL cline TOP
! l7 }- v a) y2 h (-2333.471,5852.427) via TOP/BOTTOM. ~- g, d$ P4 _) `/ b$ d0 Y3 R
1917.397 MIL cline 03IS01
0 h3 i2 r# _! t$ U* B# [2 { (-1999.457,6588.260) via TOP/BOTTOM& i8 @. l9 R/ T4 D: ?/ g
21.859 MIL cline TOP6 H5 Q; b( H% |8 q& A( W1 T8 Z) M
(-1984.000,6603.717) pin U801.F9,UNSPEC,TOP/TOP,Zall=16.672 MIL) j. X4 B1 J, ^% g$ G
9 @. K% h5 H- H9 G B# R& f Member of Groups:
4 {1 w4 Q- r7 E- G6 M0 a& q MATCH_GROUP : MFPGA1DDR_GROUP_DQ! c1 i6 |, X, g1 ^" N# T, o0 i
BUS : MFPGA1_DDR_DATA27 p& w7 u, {" F+ w+ O8 h
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