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偶也跟一贴！
) H* A( e' f8 _8 X! W' b以下内容来自《high speed digital system design》。
A; ]5 e: x& K( E, X/ Q4 a* e, W" v# S
A via is a small hole drilled through a PCB that is used to make connections between various
* N( A. |4 y# k2 A" i/ Hlayers of the PCB or to connect components to traces. It consists of the barrel, the pad, and5 ]- V4 B, ?: G+ K3 a
the antipad. The barrel is a conductive material that fills the hole to allow an electrical% B' B1 u+ v2 A$ \' W+ Z2 y' I7 X
connection between layers, the pad is used to connect the barrel to the component or trace,
: J# G4 D4 [" q" \and the antipad is a clearance hole between the pad and the metal on a layer to which no4 J* V) a# [9 _ J6 s
connection is required. The most common type of via is called a through-hole via because it
- D% p- Z3 ~$ Ois made by drilling a hole through the board, filling it with solder, and making connections on
0 \. x0 {" p- \2 q3 happropriate layers via the pad. Other, less common types of vias, used primarily in multichip
( }7 z" t+ x% x" ?0 d1 amodules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts
0 l, Q, k- T6 I2 Ia typical through-hole via and its equivalent circuit. Notice that the pads used to connect the
5 i: Y) D. E) R4 o% [traces on layers 1 and 2 make contact with the barrel and that there is no connection on1 i4 u; ?) y; S2 [% E
layer 3. Blind and buried vias have a slightly different construction. Since through-hole vias
' j/ M' N9 S' `3 m" bare by far the most common used in industry, they are the focus of this discussion.. w& R4 v2 w; u- j
5 |$ O$ k4 |& K$ qNotice that the via model is simply a pi network. The capacitors represent the via pad5 v5 j8 `; l# I- O
capacitance on layers 1 and 2. The series inductance represents the barrel. Since the via h3 m# r$ g8 i# @
structures are so small, they can be modeled as lumped elements. This assumption, of
. d4 a; [: z- j% s1 ]course, will break down when the delay of the via is larger than one-tenth of the edge rate.
- B, i- m4 ]; S P8 F/ y7 pThe main effect that via capacitance has on a signal is that it will slow down the signal edge5 Q5 g( q) b, i! B' \" a
rate, especially after several transitions. The amount that the signal edge rate will be slowed
0 ]2 b' z, I& W( X) mcan be estimated by examining the degradation of a signal transmitted through a capacitive0 q" O- P9 }: F6 o: _5 ~9 ?% r, E
load, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive, R8 J2 _+ C& ~. H: s
vias are placed in close proximity to one another, it will lower the effective characteristic
8 D$ ~7 `8 G% N* Oimpedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is5 [, V" B5 r! u; j1 b
[Johnson and Graham, 1993]
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/ f' d. t* n$ H' }" C. F[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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支持！
反对！
发表于 2008-1-17 21:53
发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!