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偶也跟一贴！
3 e5 a2 [! N8 |4 l. G, l以下内容来自《high speed digital system design》。
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7 `2 s1 B8 B. oA via is a small hole drilled through a PCB that is used to make connections between various( R1 l7 G0 h$ i. w" \( ~
layers of the PCB or to connect components to traces. It consists of the barrel, the pad, and
9 w! H. c, j+ k" r7 ?# tthe antipad. The barrel is a conductive material that fills the hole to allow an electrical
( R. s b& O. t) I4 E8 M' Jconnection between layers, the pad is used to connect the barrel to the component or trace,
* n: T0 S* B- ]3 s' H1 band the antipad is a clearance hole between the pad and the metal on a layer to which no& d9 [, F5 H2 X, D& O0 @ u9 X
connection is required. The most common type of via is called a through-hole via because it
, B7 u- V- y* Fis made by drilling a hole through the board, filling it with solder, and making connections on% m p. \: l9 S/ W" z
appropriate layers via the pad. Other, less common types of vias, used primarily in multichip4 s4 n5 c# P+ u& G: w: I/ b
modules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts
8 P1 t2 B: c% m6 u, @. ga typical through-hole via and its equivalent circuit. Notice that the pads used to connect the* ] i$ y+ C1 n9 b& F+ o3 h [
traces on layers 1 and 2 make contact with the barrel and that there is no connection on& u& [/ b: R- t. p# x
layer 3. Blind and buried vias have a slightly different construction. Since through-hole vias
5 e9 ]% [! g6 gare by far the most common used in industry, they are the focus of this discussion.' n0 M; ]3 C* L- `3 R
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Notice that the via model is simply a pi network. The capacitors represent the via pad
7 S" Y% k; h5 x% H$ ecapacitance on layers 1 and 2. The series inductance represents the barrel. Since the via
1 P1 U2 K1 ^* Z7 o' J6 l) qstructures are so small, they can be modeled as lumped elements. This assumption, of
7 d) l# t! h( p+ Z x6 vcourse, will break down when the delay of the via is larger than one-tenth of the edge rate.1 }3 p6 k0 _9 J {
The main effect that via capacitance has on a signal is that it will slow down the signal edge9 i# v2 r2 d9 |0 ~5 @( S
rate, especially after several transitions. The amount that the signal edge rate will be slowed( ? f4 Z4 _7 G, Y# Q; G1 S3 N
can be estimated by examining the degradation of a signal transmitted through a capacitive
; N8 b5 q2 F3 L) } I1 g0 j4 oload, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive
- O4 z9 V% o7 K8 C- k, `. Avias are placed in close proximity to one another, it will lower the effective characteristic
7 A6 Y: u2 h# g% E6 w4 `impedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is
; J2 ]# A. r# H) H4 l9 b[Johnson and Graham, 1993]
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; r* n% W. g) E) {+ t9 ?) b[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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支持！
反对！
发表于 2008-1-17 21:53
发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!