Stratix5_DDR.ibs模型读取报错

hesonggs@126.co

[ERROR]D:\Hyperlynx\9.4.1HL\SDD_HOME\hyperlynx64\LIBS\Stratix5_DDR.ibs:
        Error :  at line 1267 in file D:/Hyperlynx/9.4.1HL/SDD_HOME/hyperlynx64/LIBS/Stratix5_DDR.ibs : Declared differential pins AD17 and AD18 not previously defined for this component [StratixV]
        Error :  at line 1268 in file D:/Hyperlynx/9.4.1HL/SDD_HOME/hyperlynx64/LIBS/Stratix5_DDR.ibs : Declared differential pins AE15 and AD15 not previously defined for this component [StratixV]
        Error :  at line 1269 in file D:/Hyperlynx/9.4.1HL/SDD_HOME/hyperlynx64/LIBS/Stratix5_DDR.ibs : Declared differential pins AP15 and AN15 not previously defined for this component [StratixV]
        Error :  at line 1270 in file D:/Hyperlynx/9.4.1HL/SDD_HOME/hyperlynx64/LIBS/Stratix5_DDR.ibs : Declared differential pins AF14 and AE14 not previously defined for this component [StratixV]
        Error :  at line 1271 in file D:/Hyperlynx/9.4.1HL/SDD_HOME/hyperlynx64/LIBS/Stratix5_DDR.ibs : Declared differential pins AU14 and AT14 not previously defined for this component [StratixV]
        Error :  at line 1272 in file D:/Hyperlynx/9.4.1HL/SDD_HOME/hyperlynx64/LIBS/Stratix5_DDR.ibs : Declared differential pins AJ12 and AH12 not previously defined for this component [StratixV]
        Error :  at line 1273 in file D:/Hyperlynx/9.4.1HL/SDD_HOME/hyperlynx64/LIBS/Stratix5_DDR.ibs : Declared differential pins AU12 and AT12 not previously defined for this component [StratixV]
        Error :  at line 1274 in file D:/Hyperlynx/9.4.1HL/SDD_HOME/hyperlynx64/LIBS/Stratix5_DDR.ibs : Declared differential pins AG10 and AF10 not previously defined for this component [StratixV]
        Error :  at line 1275 in file D:/Hyperlynx/9.4.1HL/SDD_HOME/hyperlynx64/LIBS/Stratix5_DDR.ibs : Declared differential pins AW10 and AV10 not previously defined for this component [StratixV]
        Error : Parse failed on file D:/Hyperlynx/9.4.1HL/SDD_HOME/hyperlynx64/LIBS/Stratix5_DDR.ibs.

ephemeral

读取的方式问题吧