linux学习之路_or1200下linux的i2c(一)

mutougeda · 发表于 2021-8-5 10:09

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本帖最后由 mutougeda 于 2021-8-5 10:14 编辑

这篇 blog 介绍 I2C 的学习了，首先要在我们的 or1200_soc 上添加进来 I2C Controller ，到 opencores 社区上面找到 i2c_latest.tar.gz 这个工程包。
解压得到如下文件目录：

注意啦，这里的i2c_top.v的顶层文件需要自己编写，因为需要在工程的更顶层将i2c_master_top.v里的输入输出信号组织成三态信号。

module i2c_top(
//wishbone inteRFaces
wb_clk_i, wb_rst_i, arst_i,
wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
i2c_scl, i2c_sda
);
// wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input arst_i; // asynchronous reset
input [2:0] wb_adr_i; // lower address bits
input [7:0] wb_dat_i; // databus input
output [7:0] wb_dat_o; // databus output
input wb_we_i; // write enable input
input wb_stb_i; // stobe/core select signal
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_inta_o; // interrupt request signal output
// i2c signals
inout i2c_scl; //i2c clock signal
inout i2c_sda; //i2c data signal
i2c_master_top i2c_master_top(
//wishbone interfaces
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.arst_i(arst_i),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i),
.wb_stb_i(wb_stb_i),
.wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o),
.wb_inta_o(wb_inta_o),
.scl_pad_i(scl_pad_i),
.scl_pad_o(scl_pad_o),
.scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda_pad_i),
.sda_pad_o(sda_pad_o),
.sda_padoen_o(sda_padoen_o)
);
assign i2c_scl = scl_padoen_o ? 1'bz : scl_pad_o;
assign i2c_sda = sda_padoen_o ? 1'bz : sda_pad_o;
assign scl_pad_i = i2c_scl;
assign sda_pad_i = i2c_sda;
endmodule
) |% i& R0 `( H

      详细可以看看在改工程目录下的/doc说明文档，当中有改ipcore的使用说明。

      接着在or1200_soc中例化改ipcore，然后添加到wishbone总线上，再定义好使用的中断号。

      例化代码：

`ifdef I2C
wire [2:0] wb_i2c_adr_i;
wire [7:0] wb_i2c_dat_i;
wire [7:0] wb_i2c_dat_o;
wire [31:0] wb_i2c_dat32_i;
wire [31:0] wb_i2c_dat32_o;
wire [3:0] wb_i2c_sel_i;
wire wb_i2c_stb_i;
wire wb_i2c_we_i;
wire wb_i2c_ack_o;
wire wb_i2c_cyc_i;
wire wb_i2c_inta_o;
i2c_master_top i2c_master_top(
//wishbone interfaces
.wb_clk_i(clk_cpu_40),
.wb_rst_i(wb_rst_pad_i),
.arst_i(1'b1),
.wb_adr_i(wb_i2c_adr_i),
.wb_dat_i(wb_i2c_dat_i),
.wb_dat_o(wb_i2c_dat_o),
.wb_we_i(wb_i2c_we_i),
.wb_stb_i(wb_i2c_stb_i),
.wb_cyc_i(wb_i2c_cyc_i),
.wb_ack_o(wb_i2c_ack_o),
.wb_inta_o(pic_ints[`APP_INT_I2C]),
//i2c interface
.scl_pad_i(scl_pad_i),
.scl_pad_o(scl_pad_o),
.scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda_pad_i),
.sda_pad_o(sda_pad_o),
.sda_padoen_o(sda_padoen_o)
);
assign i2c_scl = scl_padoen_o ? 1'bz : scl_pad_o;
assign i2c_sda = sda_padoen_o ? 1'bz : sda_pad_o;
assign scl_pad_i = i2c_scl;
assign sda_pad_i = i2c_sda;
assign wb_i2c_dat32_o[7:0] = (wb_i2c_sel_i[0] == 1'b1) ? wb_i2c_dat_o : 8'h0;
assign wb_i2c_dat32_o[15:8] = (wb_i2c_sel_i[1] == 1'b1) ? wb_i2c_dat_o : 8'h0;
assign wb_i2c_dat32_o[23:16] = (wb_i2c_sel_i[2] == 1'b1) ? wb_i2c_dat_o : 8'h0;
assign wb_i2c_dat32_o[31:24] = (wb_i2c_sel_i[3] == 1'b1) ? wb_i2c_dat_o : 8'h0;
assign wb_i2c_dat_i = wb_i2c_dat32_i[7:0];
`else
assign pic_ints[`APP_INT_I2C] = 'b0;
`endif/*endif I2C*/
/* the comment section below just instance for wb_conbus module */
/*
`ifdef I2C
.s5_dat_i (wb_i2c_dat32_o),
.s5_dat_o (wb_i2c_dat32_i),
.s5_adr_o (wb_i2c_adr_i),
.s5_sel_o (wb_i2c_sel_i),
.s5_we_o (wb_i2c_we_i),
.s5_cyc_o (wb_i2c_cyc_i),
.s5_stb_o (wb_i2c_stb_i),
.s5_ack_i (wb_i2c_ack_o),
.s5_err_i (1'b0),
.s5_rty_i (1'b0),
// .s5_cab_i (),
for switch cross bus :
// .slave5_sel_addr ( `I2C_BASE_ADDR ),
.wbs5_adr_i( wb_i2c_adr_i ),
.wbs5_bte_i( ),
.wbs5_cti_i( ),
.wbs5_cyc_i( wb_i2c_cyc_i ),
.wbs5_dat_i( wb_i2c_dat32_i ),
.wbs5_sel_i( wb_i2c_sel_i ),
.wbs5_stb_i( wb_i2c_stb_i ),
.wbs5_we_i( wb_i2c_we_i ),
.wbs5_ack_o( wb_i2c_ack_o ),
.wbs5_err_o( 'b0 ),
.wbs5_rty_o( 'b0 ),
.wbs5_dat_o( wb_i2c_dat32_o ),
*/" S2 O$ N6 z+ `7 j6 q& f$ z

中断号和地址：

/* Interrupts */
`define APP_INT_RES1 1:0
`define APP_INT_UART 2
`define APP_INT_KEY 3
`define APP_INT_ETH 4
`define APP_INT_I2C 5
`define APP_INT_VGA_LCD 6
`define APP_INT_RES 19:7
/* Peripheral Addr ,modify by manual */
`define FLASH_BASE_ADDR 4'hf //slave X address ,connect to FLASH
`define SDRAM_BASE_ADDR 4'h0 //slave X address ,connect to DDR_SDRAM
`define UART_BASE_ADDR 8'h90 //slave X address ,connect to UART
`define GPIO_BASE_ADDR 8'h91 //slave X address
`define ETH_BASE_ADDR 8'h92 //slave X address ,connect to ETH
`define VGA_BASE_ADDR 8'h95 //slave X address, connect to VGA/LCD
`define DMA_BASE_ADDR 8'hxx //slave X address,
`define SRAM_BASE_ADDR 8'hxx //slave X address ,connect to SRAM
`define SD_CARD_BASE_ADDR 8'h94 //slave X address ,connect to sd_card
`define I2C_BASE_ADDR 8'h93 //slave X address ,connect to i2c device/ Z, d: g8 g" c8 K F