PCB Designer’s si guide

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PCB Designer's SI GUIDETable of Content
Basics of SI___________________________________________________________________5
4 {4 r! i; V; G0 w4 n1.1 When Speed is important? _____________________________________________5
- E3 e$ s+ o4 }8 L9 {1.1.1 Acceptable Voltage and timing values ________________________________5
1.2 Signal Integrity ______________________________________________________5
, [; c3 V' w+ O. }2 [! m1.2.1 Waveform Voltage Accuracy _______________________________________5
1.2.2 Timing_________________________________________________________5
$ i/ q7 [: Z2 l3 A  L% i1.3 Speed of currently used logic families ____________________________________5
- K2 a" \$ j/ R0 b1.3.1 Transition Electrical Length (TEL) __________________________________6
1.3.2 Critical length ___________________________________________________6
& {0 g) \, @7 @, F2 [" f6 f; p1.3.3 What is Transmission Line? ________________________________________6
& U" c  q: P- a4 c- D1.3.4 What is moving in a Transmission line?_______________________________6
1.3.5 Power Plane Definition____________________________________________6
1.3.6 The concept of Ground ____________________________________________7
1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
1.5 RLC Transmission Line Model _________________________________________8
8 w3 ^3 g/ X0 l3 X9 R) ~: d3 Y0 H1.5.1 What is Impedance? ______________________________________________8
1.5.2 A Practical impedance equation for microstrip _________________________8
1.5.3 What is relative dielectric constant Er? _______________________________9


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2 Interconnections for High Speed Digital Circuits _______________________________10

2.1.1 Summary______________________________________________________10
- \5 E7 t5 u8 D, ~- ?2.2 Examples of dynamic inteRFacing problems _______________________________10
, e0 d8 F1 `" F9 Y" Y2.3 IC Technology and Signal Integrity _____________________________________12
2.4 Speed and distance __________________________________________________14
2.5 Digital signals: Static interfacing _______________________________________15
2.6 Digital signals: Dynamic interfacing ____________________________________16
$ w- L# i9 @! L# q6 r2.7 Review questions ___________________________________________________18
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3 Interconnection Models____________________________________________________20

) O# {3 h# F2 E7 Z3.1 Summary__________________________________________________________20
) [/ K; ~3 L- K4 r, ]6 h: q) \' z" ^3.2 Reference model for interconnection analysis _____________________________20
5 ^: v( B" [( H- a- E  T* V" _3.3 Receiver model_____________________________________________________21
3 F0 r0 v  o1 z6 @4 K2 n9 {3.4 RC interconnection model ____________________________________________23
9 b1 I! d: A- ?3 K& |2 ]' V! g3.5 Parameters of the interconnection ______________________________________25
( H+ S& v  r+ S4 ]2 x9 p$ ]  @" {3.6 Refined models _____________________________________________________26
( X" B8 U  L9 }) V! l3.7 Review question ____________________________________________________28

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4 Transmission Line Models _________________________________________________31

) U- s/ G* W% S" j. Z( I) d9 B0 R7 {4.1 Summary__________________________________________________________31
4.2 Transmission line models _____________________________________________31
4.3 Loss-less transmission lines ___________________________________________32
# ]( Y0 V" Y# u9 [4.4 Critical Length _____________________________________________________34
4.5 Reference transmission line model______________________________________35
1 f  \) @4 ?0 {! q4 _- H6 n6 l, i4.6 Line driving _______________________________________________________36
4.7 Propagation and reflected waves _______________________________________37
4.8 A sample system____________________________________________________39
' L+ [' d$ d: E9 R, D% {) {5 R4.9 Review questions ___________________________________________________42
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PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45

5.1 Summary__________________________________________________________45
! g7 H% l) s& p; n5.2 Transmission time and skew___________________________________________45
% t7 ?. _# e, L* L4 p! Z5.3 Effects of termination resistance _______________________________________46
- Q8 c' _  c3 f9 p. i5.4 Lattice diagram _____________________________________________________48
, Q9 P, H  X8 P  n: c( ?! S; s5.5 Examples of Real Lines ______________________________________________49
5.6 Simulation code ____________________________________________________51
+ R, v( J$ J2 M' T) F9 [- M5.7 Examples of results__________________________________________________54
( ^/ ]3 M6 ?" F+ S" r0 e! j, L1 R5.8 Review questions ___________________________________________________55



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6 Design guide for interconnection ____________________________________________57

6.1 Summary__________________________________________________________57
0 C. ~8 d4 o4 g+ l9 L6.2 Incident wave switching ______________________________________________57
( G8 m9 i2 L2 S0 M" V6.3 Effects of capacitive loading __________________________________________58
$ o# N" y, [5 `6.4 Termination circuits _________________________________________________59
6.4.1 Passive termination______________________________________________60
0 i( h& m1 A; O" v6.4.2 Low power termination___________________________________________61
- {. Z5 V3 V9 K/ ~% N( b6.4.3 Active low power termination circuit. _______________________________61
8 d/ {" s" l6 k6.5 Driving point-to-point lines ___________________________________________62
6.6 Driving bused lines __________________________________________________64
6.7 Design guidelines ___________________________________________________67
6.8 Review questions ___________________________________________________67

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Signal Integrity in Digital Circuits ___________________________________________70
. ?2 S8 ^0 p* v2 p! X& S7.1 Crosstalk __________________________________________________________70
6 p, p( \0 o0 s3 x& l( [7.1.1 Summary______________________________________________________70
7.2 Examples of signal integrity problems ___________________________________70
! C. g) ]. Y  ~+ b% n7.3 Simplified Model for Crosstalk Analysis _________________________________71
7.4 Forward and backward crosstalk _______________________________________74
  ~6 O& V4 c$ d9 q9 [; l7.5 Examples__________________________________________________________76
9 |1 K- B1 y7 `- Q2 B2 M  m7.6 Near-end and Far-end crosstalk ________________________________________80
7.7 Review questions ___________________________________________________81


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8 Design Guide to Handle Crosstalk ___________________________________________85

8.1 Summary__________________________________________________________85
8.2 Effects of Crosstalk __________________________________________________85
8.3 Passive countermeasures _____________________________________________86
8.4 Active Control of Crosstalk ___________________________________________92
8.5 Review questions ___________________________________________________94
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9 Ground Bounce and Switching Noise_________________________________________97

9.1 Summary__________________________________________________________97
4 j1 ?! ]* R" d, h9.2 The totem pole Current Spike__________________________________________97
9.3 Current flow in the output capacitance __________________________________100
9.4 Total Ground Bounce _______________________________________________100
- h6 U4 c2 o3 S) n/ a# Q3 u9.5 Review questions __________________________________________________105
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10 Design Guide for Ground & Power Distribution _____________________________107

10.1 Summary_________________________________________________________107

PCB Designer’s SI Guide Page 3 Venkata

10.2 Decoupling Capacitors ______________________________________________107
10.3 Placement of bypass Capacitors _______________________________________113
10.4 Ground and power distribution________________________________________114
10.5 Clock distribution __________________________________________________115
10.6 Review Questions __________________________________________________118
. Y9 }. B% ?" b3 \) p11 Laboratory Experience _________________________________________________120
; Q$ r) e6 V4 e6 R; a! f, B11.1 Summary_________________________________________________________120
3 J$ k- \% }- f) N! h11.2 Aim of the experience_______________________________________________120
11.3 Generator Parameters _______________________________________________122
11.4 Cable Parameters __________________________________________________123
11.5 Mismatch at driver and at termination __________________________________124
! n# t. {  i" R9 m5 b( O11.6 Capacitive Load ___________________________________________________125
11.7 7. Time-domain reflectometer ________________________________________127
11.8 Driving the line with logic devices _____________________________________128
12 SI Analysis Strategy____________________________________________________133
0 e' f! H( B! ~+ J12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
2 R, Y# |  ^6 {12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
8 i- `- A. E* F9 n12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
12.3 SOLUTION SPACE ANALYSIS _____________________________________135
$ ?5 s8 I9 ?* ]6 c12.3.1
$ Y. A$ g6 z+ Q. i, ?5 x' {3 bSTEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
* g$ n/ A/ X  Y1 R& ?12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
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/ x' o4 ]3 B+ F6 QSTEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
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STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
  I7 Y: K: x- U: N$ p12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
. h: |" L# H1 E8 a6 I12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
, j+ K. a! y* c+ K4 `12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
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STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
+ j- N' A1 Y& W5 M# F/ g12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
/ i7 W& k" g0 d; l- @1 M0 _12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
, p  `) V! ~# ?8 X1 `0 i4 F12.4 CONCLUSION____________________________________________________139
13 Glossary _____________________________________________________________141
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PCB Designer’s SI Guide Page 4Venkata

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