PCB Designer’s si guide

snowwolfe

PCB Designer's SI GUIDETable of Content
Basics of SI___________________________________________________________________5
0 m4 L  v# v4 k. @3 E1.1 When Speed is important? _____________________________________________5
1.1.1 Acceptable Voltage and timing values ________________________________5
1.2 Signal Integrity ______________________________________________________5
& W* U3 w0 V+ P0 @* |1.2.1 Waveform Voltage Accuracy _______________________________________5
1.2.2 Timing_________________________________________________________5
1.3 Speed of currently used logic families ____________________________________5
1.3.1 Transition Electrical Length (TEL) __________________________________6
1.3.2 Critical length ___________________________________________________6
1.3.3 What is Transmission Line? ________________________________________6
9 k0 P( R4 H, M1.3.4 What is moving in a Transmission line?_______________________________6
3 B* C8 o8 @9 f! h& F) [  u1.3.5 Power Plane Definition____________________________________________6
! O4 I7 Q0 H# d) v, i1.3.6 The concept of Ground ____________________________________________7
1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
1.5 RLC Transmission Line Model _________________________________________8
1.5.1 What is Impedance? ______________________________________________8
1.5.2 A Practical impedance equation for microstrip _________________________8
1.5.3 What is relative dielectric constant Er? _______________________________9
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2 Interconnections for High Speed Digital Circuits _______________________________10

2.1.1 Summary______________________________________________________10
2.2 Examples of dynamic inteRFacing problems _______________________________10
( ^4 D- X( x. Q% G  }; {9 E/ _2.3 IC Technology and Signal Integrity _____________________________________12
2.4 Speed and distance __________________________________________________14
4 _+ C8 t0 T: w. t0 ^2.5 Digital signals: Static interfacing _______________________________________15
2.6 Digital signals: Dynamic interfacing ____________________________________16
+ e! x/ C4 T0 z9 y0 ~1 _2.7 Review questions ___________________________________________________18



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3 Interconnection Models____________________________________________________20

. N" ^# _2 H: J6 K* i3.1 Summary__________________________________________________________20
3.2 Reference model for interconnection analysis _____________________________20
3.3 Receiver model_____________________________________________________21
3.4 RC interconnection model ____________________________________________23
3.5 Parameters of the interconnection ______________________________________25
3.6 Refined models _____________________________________________________26
3.7 Review question ____________________________________________________28
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4 Transmission Line Models _________________________________________________31

4.1 Summary__________________________________________________________31
4.2 Transmission line models _____________________________________________31
4.3 Loss-less transmission lines ___________________________________________32
+ |- i8 U2 c; O: N, M: ^1 p4.4 Critical Length _____________________________________________________34
9 e' t" }" Y: s; F1 z1 l% ]4.5 Reference transmission line model______________________________________35
2 k* j6 u* i' M5 X* F4.6 Line driving _______________________________________________________36
4.7 Propagation and reflected waves _______________________________________37
4.8 A sample system____________________________________________________39
4.9 Review questions ___________________________________________________42

PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45

5.1 Summary__________________________________________________________45
' C. |0 }$ c7 Q0 J5.2 Transmission time and skew___________________________________________45
0 g0 ?2 s& [9 O0 Y$ `0 V5.3 Effects of termination resistance _______________________________________46
! s7 S, U. I/ g0 I5 T5.4 Lattice diagram _____________________________________________________48
5.5 Examples of Real Lines ______________________________________________49
5.6 Simulation code ____________________________________________________51
) I2 F& h/ [# E7 I5.7 Examples of results__________________________________________________54
) l" z7 d, g; X3 B* I( r' O  V5.8 Review questions ___________________________________________________55

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6 Design guide for interconnection ____________________________________________57

( j; N  i; v' p% t- n1 s6 Y6 s6.1 Summary__________________________________________________________57
6.2 Incident wave switching ______________________________________________57
6.3 Effects of capacitive loading __________________________________________58
6.4 Termination circuits _________________________________________________59
6.4.1 Passive termination______________________________________________60
0 |* v4 {* c% Y( X6.4.2 Low power termination___________________________________________61
6.4.3 Active low power termination circuit. _______________________________61
6.5 Driving point-to-point lines ___________________________________________62
- H$ `' ~3 ^7 h  e1 U# l, k4 |9 W. G6.6 Driving bused lines __________________________________________________64
& J+ }/ H* h( m! N* D' l6.7 Design guidelines ___________________________________________________67
6.8 Review questions ___________________________________________________67

snowwolfe

Signal Integrity in Digital Circuits ___________________________________________70
" k4 z! D8 B- z; {2 a+ g  @: Z7.1 Crosstalk __________________________________________________________70
2 s5 Z: ]# b) C( l7.1.1 Summary______________________________________________________70
7.2 Examples of signal integrity problems ___________________________________70
4 ]% G8 N! _! c4 y2 X; R9 g9 J& n7.3 Simplified Model for Crosstalk Analysis _________________________________71
7.4 Forward and backward crosstalk _______________________________________74
& b1 I7 [! o/ N0 I: R8 Q7.5 Examples__________________________________________________________76
. P$ m1 [5 X+ u  W/ R. W# v& R7.6 Near-end and Far-end crosstalk ________________________________________80
- W/ L2 w8 r8 N/ i! S4 [' K  J7.7 Review questions ___________________________________________________81
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8 Design Guide to Handle Crosstalk ___________________________________________85

8.1 Summary__________________________________________________________85
* C/ L4 Q3 b4 G/ N6 z- {8.2 Effects of Crosstalk __________________________________________________85
! C1 D! D3 J' `9 l0 c% U7 _8.3 Passive countermeasures _____________________________________________86
8.4 Active Control of Crosstalk ___________________________________________92
. k) ?1 d. k6 n2 C3 \  a8.5 Review questions ___________________________________________________94
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9 Ground Bounce and Switching Noise_________________________________________97

+ W# x. |4 s" t2 u2 h1 M2 `" ?! b$ c9.1 Summary__________________________________________________________97
& v! F: _- V6 f/ k  {! }9 e9.2 The totem pole Current Spike__________________________________________97
9.3 Current flow in the output capacitance __________________________________100
9.4 Total Ground Bounce _______________________________________________100
9.5 Review questions __________________________________________________105

10 Design Guide for Ground & Power Distribution _____________________________107

8 d6 u4 W9 Q  v; E5 F10.1 Summary_________________________________________________________107

PCB Designer’s SI Guide Page 3 Venkata

10.2 Decoupling Capacitors ______________________________________________107
10.3 Placement of bypass Capacitors _______________________________________113
, Z" m) M$ P" h' p& F8 a10.4 Ground and power distribution________________________________________114
10.5 Clock distribution __________________________________________________115
+ Y0 h* `2 ^/ C- U5 M10.6 Review Questions __________________________________________________118
11 Laboratory Experience _________________________________________________120
11.1 Summary_________________________________________________________120
11.2 Aim of the experience_______________________________________________120
1 k$ S, f' v. K9 h* F: e! @4 Y11.3 Generator Parameters _______________________________________________122
11.4 Cable Parameters __________________________________________________123
7 D, j" r5 h0 P) j' I. H11.5 Mismatch at driver and at termination __________________________________124
- F7 l* E1 [; h! A0 T) k9 ^11.6 Capacitive Load ___________________________________________________125
11.7 7. Time-domain reflectometer ________________________________________127
11.8 Driving the line with logic devices _____________________________________128
0 e, |' c3 @" S% G, |$ d12 SI Analysis Strategy____________________________________________________133
% d) \$ t  N% N4 d; |* ]0 }12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
) R3 a% l) o6 {: [! X3 V- t2 }12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
) I" D9 {9 c' c, v. p8 L6 M12.3 SOLUTION SPACE ANALYSIS _____________________________________135
) G/ B, J9 ]; E- h12.3.1
STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
12.3.3
STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
12.3.4
STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
- m' H& q! \4 \2 f$ z& p3 Y12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
; V1 t9 M( n# g% H& D$ }12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
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. }3 A! P$ h* T# K" `" SSTEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
+ d( Y) P7 |. w  z0 M3 I- A12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
8 k4 w& ]# a" F0 j! S6 u5 V12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
12.4 CONCLUSION____________________________________________________139
13 Glossary _____________________________________________________________141
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PCB Designer’s SI Guide Page 4Venkata

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