PCB Designer’s si guide

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PCB Designer's SI GUIDETable of Content
Basics of SI___________________________________________________________________5
1.1 When Speed is important? _____________________________________________5
% V8 s; _, W2 e0 ]8 X! M. \1.1.1 Acceptable Voltage and timing values ________________________________5
1.2 Signal Integrity ______________________________________________________5
# J' R4 R' ~! W, q" i/ p$ a1.2.1 Waveform Voltage Accuracy _______________________________________5
0 @- |& b1 k+ H8 T3 X! m4 o* }1.2.2 Timing_________________________________________________________5
! {- d% g) e$ v/ ~7 V1.3 Speed of currently used logic families ____________________________________5
+ V$ L, ^- A1 U1.3.1 Transition Electrical Length (TEL) __________________________________6
1.3.2 Critical length ___________________________________________________6
1.3.3 What is Transmission Line? ________________________________________6
1.3.4 What is moving in a Transmission line?_______________________________6
" D! s3 `7 `; b$ L2 o1.3.5 Power Plane Definition____________________________________________6
9 p0 ~9 [( j/ G' v1.3.6 The concept of Ground ____________________________________________7
3 M8 `/ @, T5 P8 \, u4 t1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
4 m0 k' p' \& O1 L) @6 m$ I7 ]1.5 RLC Transmission Line Model _________________________________________8
/ o9 g3 z/ Q5 I9 y/ {1.5.1 What is Impedance? ______________________________________________8
$ Y- w7 v( D2 V0 _' z1.5.2 A Practical impedance equation for microstrip _________________________8
1.5.3 What is relative dielectric constant Er? _______________________________9
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2 Interconnections for High Speed Digital Circuits _______________________________10

2.1.1 Summary______________________________________________________10
2.2 Examples of dynamic inteRFacing problems _______________________________10
2.3 IC Technology and Signal Integrity _____________________________________12
8 e, v) X( k, O. P2.4 Speed and distance __________________________________________________14
& N, b5 x, d/ g8 u4 \& n2.5 Digital signals: Static interfacing _______________________________________15
& v9 d7 d1 R5 D) i, }2.6 Digital signals: Dynamic interfacing ____________________________________16
2.7 Review questions ___________________________________________________18


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3 Interconnection Models____________________________________________________20

3 P# J7 i) @$ D, p- _3.1 Summary__________________________________________________________20
2 H$ V1 \8 `% _4 R& X( S- ]3.2 Reference model for interconnection analysis _____________________________20
& u! M, A- A% b6 P3.3 Receiver model_____________________________________________________21
3.4 RC interconnection model ____________________________________________23
  o: {& b) o5 I: b6 c3.5 Parameters of the interconnection ______________________________________25
1 X3 ?! r- I! `2 }/ J# i* i! P3.6 Refined models _____________________________________________________26
1 m9 A* W( G! K! t7 `3.7 Review question ____________________________________________________28
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4 Transmission Line Models _________________________________________________31

4.1 Summary__________________________________________________________31
$ [' E4 U  h" _% {# w( m& z4.2 Transmission line models _____________________________________________31
4.3 Loss-less transmission lines ___________________________________________32
+ y5 X6 ]7 D) c: I7 u$ Q4.4 Critical Length _____________________________________________________34
$ T+ f3 k8 F7 O0 C4 e; @. _4.5 Reference transmission line model______________________________________35
7 Y7 S, \* ~; x3 H4.6 Line driving _______________________________________________________36
8 ?  [+ r( {7 c" Q9 _0 f4.7 Propagation and reflected waves _______________________________________37
- ^7 }' ^% K) |+ |4.8 A sample system____________________________________________________39
$ E6 @! T: Y- H- |/ I8 [- U4.9 Review questions ___________________________________________________42
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PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45

& t2 k* r1 d' V3 v5.1 Summary__________________________________________________________45
5.2 Transmission time and skew___________________________________________45
5.3 Effects of termination resistance _______________________________________46
' T6 }& K( }0 s: y- a5 O! s$ |5.4 Lattice diagram _____________________________________________________48
+ o; D" z! j$ y9 s5.5 Examples of Real Lines ______________________________________________49
5.6 Simulation code ____________________________________________________51
0 u8 N" ]; u- n* i5.7 Examples of results__________________________________________________54
5.8 Review questions ___________________________________________________55

6 Design guide for interconnection ____________________________________________57

6.1 Summary__________________________________________________________57
( h5 k9 J# I' N! k0 P1 c6.2 Incident wave switching ______________________________________________57
6.3 Effects of capacitive loading __________________________________________58
5 M3 X3 h1 n1 `% g6.4 Termination circuits _________________________________________________59
, o% \( f( M' L( T2 r" l6.4.1 Passive termination______________________________________________60
6.4.2 Low power termination___________________________________________61
6.4.3 Active low power termination circuit. _______________________________61
* X7 ^- M+ m& {" B# I" r" r6.5 Driving point-to-point lines ___________________________________________62
6.6 Driving bused lines __________________________________________________64
6.7 Design guidelines ___________________________________________________67
! i& d: K( S: {  T' L3 z6.8 Review questions ___________________________________________________67

snowwolfe

Signal Integrity in Digital Circuits ___________________________________________70
3 j! r$ W: c5 |" d7.1 Crosstalk __________________________________________________________70
7.1.1 Summary______________________________________________________70
7.2 Examples of signal integrity problems ___________________________________70
) _4 ^. Y8 }" g1 |7.3 Simplified Model for Crosstalk Analysis _________________________________71
7.4 Forward and backward crosstalk _______________________________________74
% L1 g% o3 o. q- b7.5 Examples__________________________________________________________76
7.6 Near-end and Far-end crosstalk ________________________________________80
7.7 Review questions ___________________________________________________81

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8 Design Guide to Handle Crosstalk ___________________________________________85

8.1 Summary__________________________________________________________85
& ]* P; O' L4 x2 Y/ y8 R8.2 Effects of Crosstalk __________________________________________________85
& \& G! H2 g3 z3 A5 E8.3 Passive countermeasures _____________________________________________86
, @6 o+ U3 l  P+ l* J9 J8.4 Active Control of Crosstalk ___________________________________________92
, ]4 A+ `# L% A# `( {* Y- k8.5 Review questions ___________________________________________________94
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9 Ground Bounce and Switching Noise_________________________________________97

+ i' {, D" h- W2 r1 h- a7 T4 W3 z9.1 Summary__________________________________________________________97
4 l* [5 j& L; Z9 L9.2 The totem pole Current Spike__________________________________________97
3 R" D$ M$ L4 L. ], M4 C! N9.3 Current flow in the output capacitance __________________________________100
3 D* ?' d! l: E: ^# \* x9.4 Total Ground Bounce _______________________________________________100
9.5 Review questions __________________________________________________105
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10 Design Guide for Ground & Power Distribution _____________________________107

+ T8 Y6 A; f% `5 t6 a' |10.1 Summary_________________________________________________________107

PCB Designer’s SI Guide Page 3 Venkata

10.2 Decoupling Capacitors ______________________________________________107
: ?  o, ~& u* v" L( V10.3 Placement of bypass Capacitors _______________________________________113
10.4 Ground and power distribution________________________________________114
9 n7 K$ |$ f- {/ W! O5 x4 _10.5 Clock distribution __________________________________________________115
10.6 Review Questions __________________________________________________118
9 J  t, B1 I/ q+ o( S; |11 Laboratory Experience _________________________________________________120
11.1 Summary_________________________________________________________120
11.2 Aim of the experience_______________________________________________120
! ]' N4 L$ k2 ]5 g11.3 Generator Parameters _______________________________________________122
# E/ |2 W; @1 n. D- C11.4 Cable Parameters __________________________________________________123
11.5 Mismatch at driver and at termination __________________________________124
11.6 Capacitive Load ___________________________________________________125
11.7 7. Time-domain reflectometer ________________________________________127
/ b2 _" W# @$ [/ o6 y3 x" X. ^11.8 Driving the line with logic devices _____________________________________128
12 SI Analysis Strategy____________________________________________________133
12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
& ?% z2 |( ]$ O% o! c12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
12.3 SOLUTION SPACE ANALYSIS _____________________________________135
12.3.1
STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
0 b" b. w; `3 h9 @/ f12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
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STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
12.3.4
1 R, M$ x. O  H' G. A6 Z1 LSTEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
" c0 g5 p3 _0 n, p0 x12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
9 Z$ f' r6 D$ G9 `4 A/ E6 @  M12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
& {4 `2 o! r+ y4 I, I: M3 c4 N12.3.8
- T2 R& ]! ^2 B- y* ySTEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
6 ]1 ^2 R' z) h2 g12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
12.4 CONCLUSION____________________________________________________139
2 p0 V# ~4 ^$ D0 _1 }9 k) F- O6 j13 Glossary _____________________________________________________________141

PCB Designer’s SI Guide Page 4Venkata

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