楼上正解。根据FPGA的memory设计经验,等长建议如下:! m. M/ p; a: V+ T
* i8 T2 D# C/ x D" b
1.DQ match DQS in one group within 50mil; ! J3 Y: E: \* Q' j& U) b2.DQS match associated clock within 100mil; ! c* N1 a' L. k/ o$ y) S3.Address/Command match associated clock within 150mil.