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Cadence OrCAD and Allegro 17.4-2019 QIR1

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发表于 2020-6-8 02:00 | 只看该作者 |只看大图 回帖奖励 |倒序浏览 |阅读模式

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本帖最后由 金志峰 于 2020-6-8 03:33 编辑 / p+ T( [3 d  H

1 o5 K" ~) O! `  Z. D4 \4 j' j cadence orcad and allegro 17.4-2019 QIR1新特性 $ J# X8 L3 u" N2 F+ j* w
·焕然一新的图标及UI
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; B0 R9 {0 b1 I% X  }QIR1中全新启动界面 (点击图片放大)
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8 U; S) t! C) o# U, y. JQIR1中全新启动界面(点击图片放大)5 M, w, P; D6 [2 N8 j" s

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% V* a+ U! ~: H7 J; W- }. s# e9 tQIR1中capture官方Dark主题(点击图片放大)(QIR1中UI界面中所有图标也全部更换全新并统一了)
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QIR1中capture官方Light主题(点击图片放大)
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QIR1中PCB Editor新增官方Dark主题(点击图片放大)
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QIR1中PCB Editor官方Light主题(点击图片放大)
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Fixed CCRs: SPB 17.4 HF007
5 F3 t( _) N2 l/ L7 X05-21-2020+ f0 M) _5 C) s9 l$ R+ A5 d" V
========================================================================================================================================================) J/ }5 x# g5 _# `& `
CCRID   Product            ProductLevel2 Title3 W. u( n6 a: A) u' S% q* t7 ^: ?
========================================================================================================================================================8 g6 P* c5 q3 p! d
2247686 ADW                CORE          Allegro EDM: Unable to create a project using a newly created flow
4 z2 m$ N- o0 z4 H0 J& _' V8 r2137594 ADW                DBADMIN       EDM is not allowing changes to STEP models
$ J/ p9 W+ C" J5 S) \' v" _/ \. P2135452 ADW                DBEDITOR      DBEditor poor peRFormance in high-latency networks
+ D2 K1 b  n" G4 x% e2113265 ADW                LIBDISTRIBUTI Various database operations take a long time; rebooting server seems to fix the problem
! j7 z3 q, j. T& ]/ O) s2122941 ADW                LIBDISTRIBUTI Lib_dist execution taking a long time to run; Capture CIS DBC file appears to be taking the most time. V6 o5 Z; X9 t6 O
2127319 ADW                LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250)
; Y: b; L# |, X% d- y1975317 ADW                PART_BROWSER  Space at the end of the line in CDS.LIB results in zero libraries being shown in System Capture library search
) V) e1 h* T: M, k9 K+ G- \2078057 ADW                PART_BROWSER  Symbol Graphics preview is not available in Designer Servers
& p9 U) {" d/ d: V4 L/ M2092863 ADW                PART_BROWSER  System Capture library search is not displaying the symbol and footprint preview
! Q4 e0 h+ l* Q$ C/ i7 w2086463 ADW                PART_MANAGER  System Capture cannot add components when accessing remote machine via Citrix
4 ]' i9 I8 p2 z2092868 ADW                PART_MANAGER  Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not flow from pstchip9 Q3 `& ~% @5 n. c4 ^) W
2092872 ADW                PART_MANAGER  System Capture stops responding when importing from DE-HDL
! p: z+ x- n( x/ K4 j7 D2113226 ADW                PART_MANAGER  System Capture stops responding while importing DE-HDL sheets
8 \! t8 E( R% Q. U$ M" q2212406 ADW                PART_MANAGER  Allegro System Capture: Part Manager is deleting properties from all instances upon Update
# g' }* o6 _- q2025147 ADW                TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
0 o; f8 z- P( K2 `+ O2025201 ADW                TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to Team Design- Y) l- E4 Z# V
2056694 ADW                TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object0 O8 V5 J2 D0 N/ n$ R; I. m" G( g
2048086 ALLEGRO_EDITOR     3D_CANVAS     Wire bonds are not linked to die pad when component is embedded body down
$ }& W- ?1 y4 L" ]  ~, i! ~% V4 w! y2051277 ALLEGRO_EDITOR     3D_CANVAS     Vias are offset from board in Z direction in 3D Canvas/ ]9 W1 U' ^  i/ H4 |. K
2054243 ALLEGRO_EDITOR     3D_CANVAS     Plating is not shown on stacked vias in 3D canvas& q9 c+ D7 i9 v
2054327 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
" O- ~( M; S' L2079732 ALLEGRO_EDITOR     3D_CANVAS     Enhance 3D Canvas to merge the lines segment and overlapping lines and shapes
1 D$ F' b8 ~6 L" K5 ~5 f2206045 ALLEGRO_EDITOR     ARTWORK       Artwork Control Form fails to create film if Film record has a period (.) in the title
  a8 e. K/ n( w1 k4 |2209200 ALLEGRO_EDITOR     ARTWORK       PCB Editor stops responding on rebuilding apertures without rotation6 r6 e$ ^, T7 q4 S) N/ v, ~  u8 [1 n; E
2244407 ALLEGRO_EDITOR     ARTWORK       Automatic editing apertures with rotation takes time in the General Parameters tab of Artwork Control Form0 `  m; m- u! b% k. B& G
2267942 ALLEGRO_EDITOR     ARTWORK       Allegro PCB Editor stops responding when generating apertures in HotFix 006
8 A4 I( Q3 R+ L% w0 S- x567342  ALLEGRO_EDITOR     COLOR         Add option under View menu for 'load color view'
1 I0 K7 B4 J  ^8 I- T7 ?8 C637828  ALLEGRO_EDITOR     COLOR         Line highlights in 'shape select' command  P0 E/ y) r+ [
720274  ALLEGRO_EDITOR     COLOR         Add menu option for the 'colorview load' command0 }# l  Q3 ]1 _: u' w* U; s( r8 `
1602652 ALLEGRO_EDITOR     COLOR         Color/Visibility behavior variation using "Enable Layer Select Mode", I4 U2 ?2 \' ^) V+ v
2072695 ALLEGRO_EDITOR     COLOR         Clines of colored nets not colored when 'display_nohighlight_priority' is set+ I( m3 S  g! R7 |
2207580 ALLEGRO_EDITOR     COLOR         Component color is inconsistent when display_nocolor_dynamics is set.$ B. ^2 L/ i& K$ Q" f/ z
2056497 ALLEGRO_EDITOR     DATABASE      Place manual is slow
9 h& Q) t+ h& p0 j! L& @2250988 ALLEGRO_EDITOR     DATABASE      Inner Layer keep out as illegal subclasses: Shape object may not exist on layer ROUTE KEEPOUT/INNER_SIGNAL_LAYERS) t# Q, }" m) @0 V- ?
2096958 ALLEGRO_EDITOR     DFA           Cannot launch Constraint Manager after assigning CSet and closing
* U, j# ]" W$ r: {) {2049681 ALLEGRO_EDITOR     DFM           DFF check for plating in via should not flag DRC for surface mount testpoint Via
) ]" ]$ W0 r7 j8 ^& s. r$ [2155060 ALLEGRO_EDITOR     DFM           Inconsistent behavior in displaying DRCs for Via to Via spacing8 i" V# n0 _! ]" c
2166431 ALLEGRO_EDITOR     DFM           DesignTrue annular ring thru pin pad to mask checks compared to smd pin to mask checks are inconsistent in behavior
) s, o# Y3 ]) |" ^! Q+ a0 m2221975 ALLEGRO_EDITOR     DFM           DFM missing mask check reporting mask is missing when pins have a mask geometry overlaying them.
  \) t9 [7 [' E' H2249498 ALLEGRO_EDITOR     DRAFTING      When a Symbol with a Dimension is placed on the board, an extra Dimension is added to the Symbol origin.5 r; S2 m. L; s8 H- f- w3 e; k
2250631 ALLEGRO_EDITOR     DRC_CONSTR    Cannot import netlist into design due to illegal DRC element: no DBDoctor error# _) n; X2 ]* v( q& Z4 X
1794593 ALLEGRO_EDITOR     EDIT_ETCH     Unable to deselect return path vias selected when creating High-speed via structures1 ^: N- K/ f& A. o
2099538 ALLEGRO_EDITOR     EDIT_ETCH     Gloss - Via Eliminate shifts traces to another layer
, x0 C/ H9 b! A" p) t: z8 n2204339 ALLEGRO_EDITOR     EDIT_ETCH     Differential pair line lost during slide operation
9 c* X, m* q6 l1 }2 {2208938 ALLEGRO_EDITOR     EDIT_ETCH     Slide operation makes one of the differential pair cline invisible
% C" O& B1 Z) a. R; z2222047 ALLEGRO_EDITOR     EDIT_ETCH     One of the traces disappear when sliding a differential pair in single trace mode
! E$ e" Y4 m; ~2 c0 l4 Q2233991 ALLEGRO_EDITOR     EDIT_ETCH     One cline of a differential pair disappears temporarily upon sliding the Differential Pair in Single Trace Mode
# a; G0 s% i. \( ^* e8 u! [* L* \. o2240827 ALLEGRO_EDITOR     EDIT_ETCH     Cline of a Differential pair net disappears after sliding the other net of the Differential pair
4 L# M' B2 V) X2 q& d2245775 ALLEGRO_EDITOR     EDIT_ETCH     Differential pair slide in single trace mode removes other trace/ h( _9 Z) y0 ^7 D$ G
1813358 ALLEGRO_EDITOR     GRAPHICS      Allegro PCB Editor enables shape boundary when disabling etch layer in Visibility pane/ j7 c" @- j% r1 {0 t
1911613 ALLEGRO_EDITOR     GRAPHICS      The subclass for boundary class stays on, even if Subclass for Etch Class is turned off from Visibility tab3 V3 W! M& W- `* B' e! ?
1966343 ALLEGRO_EDITOR     GRAPHICS      Shape boundary remains enabled even after turning off the etch layer visibility
  Z  k9 |. Q5 d0 ^4 @5 T! `2195276 ALLEGRO_EDITOR     GRAPHICS      Selecting File view is slow
! c7 \7 y7 B1 g7 t; g' s5 ]4 E& L2031883 ALLEGRO_EDITOR     INTERACTIV    Sub-Drawing: Clipboard origin point is not set correctly  [* `3 J; }3 W
2050177 ALLEGRO_EDITOR     INTERACTIV    Letters need to remain aligned and uniform after performing Shape ANDNOT operation# K2 I3 t. Z7 O# q2 m6 b$ C, [" g
2069247 ALLEGRO_EDITOR     INTERACTIV    DFA bubble on wrong layer after mirroring the part
0 e  x3 r3 P7 X$ |  d2103711 ALLEGRO_EDITOR     INTERACTIV    Placement edit mode popup 'Rotate' leaves ghost image in the background" K/ ?2 L# {( a1 z9 y8 x& ~
2136859 ALLEGRO_EDITOR     INTERACTIV    DFA Problem if we mirror component while placing
# O; D0 F: J+ S7 F0 r3 ?2165027 ALLEGRO_EDITOR     INTERACTIV    Different behavior in OrCAD Capture when using crossprobe to select Power nets
2 g# X. b, h$ Y$ V2240235 ALLEGRO_EDITOR     INTERACTIV    The design file name changes automatically to board template name while creating new board (wizard).
& p  k: V1 l- ?4 ~7 S3 G; y2244765 ALLEGRO_EDITOR     INTERACTIV    License 4150+226 does not have AiDT/AiPT in release 17.2-2016
8 d. n7 _+ q% F$ l# \6 R2259800 ALLEGRO_EDITOR     INTERACTIV    DFA DRC circle not shown on the layer of placement in Placement App Mode
$ `3 y0 ?1 k9 e" B2120420 ALLEGRO_EDITOR     INTERFACES    Drill figures missing in the exported PDF if drill legend deleted& S) x; ^( T# ^# A0 i; D; b  b
2136454 ALLEGRO_EDITOR     INTERFACES    Export - PDF output is not correct
2 c7 P: u3 l) F& d( M6 Q" ^) r2116748 ALLEGRO_EDITOR     IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets
) M) Y( P! @2 P3 x2138977 ALLEGRO_EDITOR     IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to 17.2-2016, HotFix 057: j% w# z! V( |- Q0 C: g
2247167 ALLEGRO_EDITOR     IN_DESIGN_ANA IDA Impedance Analysis: Add an option to export CSV automatically" y9 @* g- O" _
2222638 ALLEGRO_EDITOR     IPC           Documentation Editor crashes with error: Failed to complete the job because of unspecified error8 l! H. @5 F" Q1 R& g# q+ n
2106425 ALLEGRO_EDITOR     NC            Disable undersize regular pad and oversize soldermask pad for start layers in Backdrill Setup and Analysis
! K( S/ u' _* F" [+ u7 l/ y1 \& [2091932 ALLEGRO_EDITOR     OTHER         Unsupported Prototypes command missing for the OrCAD licenses
# j$ k- ~; l, p2221345 ALLEGRO_EDITOR     OTHER         Speed up Allegro PCB Editor startup by removing check for defunct PCB/Package co-design capability (NG_450)
* \  U" M6 E# A1 U8 f2257934 ALLEGRO_EDITOR     PLACEMENT     Error (SPMHGE-626) on place component: Symbol not valid on any layer" N* I6 T+ O6 v4 W- c
1001000 ALLEGRO_EDITOR     PLOTTING      File - Plot in PCB Editor does not plot more than one copy
0 U. k1 v- f$ K) b8 w* X2234538 ALLEGRO_EDITOR     REPORTS       Allow Unused Blind/Buried Via report to run as Batch Process through the reports batch command0 h# n$ D2 e/ D! N; K$ V7 }
2222738 ALLEGRO_EDITOR     SCHEM_FTB     Netrev not completing, showing error for electrical constraints data (pstcmdb.dat) import
/ h4 H0 [4 W( v' x) T  ]& y" q2255426 ALLEGRO_EDITOR     SCHEM_FTB     Netrev is running for hours without closing6 |* _# t3 Q" i/ {# D1 e, T
1702190 ALLEGRO_EDITOR     SCRIPTS       Allegro PCB Editor script file: Some sub-classes not created and error for form field label
: \5 Z1 \8 T5 f0 g$ Z# K1791099 ALLEGRO_EDITOR     SCRIPTS       Allegro PCB Editor does not terminate when the script is run with '-nographic'
" B! J* j( O2 D% ^0 d/ J- P* }' Q4 r1791267 ALLEGRO_EDITOR     SCRIPTS       Allegro PCB Editor script does not run with '-nograph' in release 17.2-2016
+ q* v# s. D$ Q# a! `+ `1892520 ALLEGRO_EDITOR     SCRIPTS       Allegro PCB Editor stops responding for script when run with '-nographic'  I" b; I: f' z' K& x0 n9 V, I! q7 \1 L
1962010 ALLEGRO_EDITOR     SCRIPTS       Allegro PCB Editor stops responding for script when run with -nongraph option
4 T. y' l9 W: A# m$ _! S. P2056857 ALLEGRO_EDITOR     SHAPE         Shape boundary error by shape parameter
& w5 l. ~7 {" }1 u2081946 ALLEGRO_EDITOR     SHAPE         Shape Update takes twice the time in release 17.2-2016, HotFix 053 as compared to HotFix 047, g5 a/ }( o; Y
2104559 ALLEGRO_EDITOR     SHAPE         PCB Editor crashes while performing shape operation 'andnot'
' R0 q' p9 Q0 S2108207 ALLEGRO_EDITOR     SHAPE         No Void Overlap option is not working in  Auto Metal Balancing (AMB)  `6 H" |* e3 G9 \5 t
2240996 ALLEGRO_EDITOR     SHAPE         Detecting Shape Island: Ignored for copied or moved shape2 G; P2 T& X1 {* ^. p, r
2258758 ALLEGRO_EDITOR     SHAPE         Allegro PCB Editor crashes when routing two signals together
$ t$ y: C% A% w, \- e  p/ m717389  ALLEGRO_EDITOR     skill         Ability to set and return the application mode using SKILL
" Q. n. B/ q7 B& y853160  ALLEGRO_EDITOR     SKILL         Need ability to get and set application modes using SKILL
$ }3 t4 k" j  u; ]+ \; P9 ]3 ^; I981446  ALLEGRO_EDITOR     SKILL         Request the ability to get and set application modes using SKILL
& k+ f5 x, }6 n1235409 ALLEGRO_EDITOR     SKILL         SKILL option to get application mode
4 L' ]5 ?  {* [: n% n1316962 ALLEGRO_EDITOR     SKILL         SKILL option to switch between application modes
/ r  v; r& F8 m1553621 ALLEGRO_EDITOR     SKILL         Ability to change application modes using SKILL function0 G' K' z* z0 t" p6 d
1885442 ALLEGRO_EDITOR     SKILL         Ability to change application modes using SKILL function., N1 l+ r0 ~9 [9 }
2080351 ALLEGRO_EDITOR     SKILL         SKILL to determine current application mode" v# d! m  Q+ T8 U, o1 o0 |# @
2195645 ALLEGRO_EDITOR     THIEVING      Thieving pad cannot be added on some areas in the board in latest hotfix but could be added earlier9 H8 A& Y5 c' P5 A' I/ z7 U
1721594 ALLEGRO_EDITOR     UI_FORMS      STEP name Filter for STEP Package mapping form should be case insensitive
6 Z, Y; A; r8 h" g2090604 ALLEGRO_EDITOR     UI_FORMS      Undo/Redo UI grayed out when invoking Color192( h& R3 i1 D. t2 F4 m
2203278 ALLEGRO_EDITOR     UI_FORMS      'Width' keyword in Place Rectangle field is grayed out when Place Rectangle is selected( Y' r) ~8 h% Y1 t3 B
2209172 ALLEGRO_EDITOR     UI_FORMS      Labels truncated by drop-down lists in Options ('Manufacture' - 'Drafting' - 'Relative Copy')6 D. Z3 q" ]- l# Y0 ]: j
2239426 ALLEGRO_EDITOR     UI_FORMS      Cannot start text size with decimal in 'Design Parameter Editor' - 'Text' for English (Denmark) regional settings4 c& @1 {4 }2 M9 n! _; ]% H
2245035 ALLEGRO_EDITOR     UI_FORMS      The right edge of the default Define Grid form looks cut off in 17.4.0 K" S& ]$ z: K( y3 A! r% B
2245955 ALLEGRO_EDITOR     UI_FORMS      Resizing of 'Reject Item Selection' window not possible in release 17.4-2019, HotFix 004! D# K5 |; f) O6 I8 u
2249202 ALLEGRO_EDITOR     UI_FORMS      Extra click required to activate Pass field in Autorouter form
, D( {- h; P- K) Q! H3 E2259605 ALLEGRO_EDITOR     UI_FORMS      Add ability to resize Reject pop-up' n, [# U( N- H) N2 i$ |+ m
2090517 ALLEGRO_EDITOR     UI_GENERAL    Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane
( h4 m0 b- H) m* y, W3 n6 ]2092436 ALLEGRO_EDITOR     UI_GENERAL    RefDes length of input string for Modify Design padstack is limited to 20 characters
/ z" e! y% q; E8 K* }' Z2134781 ALLEGRO_EDITOR     UI_GENERAL    The Pin Class is missing in Options tab when creating or opening a Mechanical Symbol  J0 [* x0 b; Z
2168026 ALLEGRO_EDITOR     UI_GENERAL    Edit Properties UI slow to launch for boards with many drawing properties' [- S5 U/ ^: X: ^
2191267 ALLEGRO_EDITOR     UI_GENERAL    Changing Visibility of any object type disables links in Layer Select Mode in the Visibility pane
* V/ L/ \) k7 W! e1 z) B8 A" a2208018 ALLEGRO_EDITOR     UI_GENERAL    Text on BGA pins not visible in release 17.4-2019 if not zoomed to maximum" Q! U. {3 p& W. L
2225753 ALLEGRO_EDITOR     UI_GENERAL    dark theme does not respect TRBICON size for 4K monitors
6 l/ f4 n2 e; O  [! [& t2256841 ALLEGRO_EDITOR     UI_GENERAL    Enlarge the Shape Copy to Layers form as the window is quite small and not resizable
" S' @! [- v1 J# S9 u* l/ D2258019 ALLEGRO_EDITOR     UI_GENERAL    Canvas turns white after closing STEP Package Mapping window6 Y; L' ]8 J$ L5 [! E
2258167 ALLEGRO_EDITOR     UI_GENERAL    Enhance 'Shape copy to layers' window in release 17.4-2019 to expand or resize0 M; `% L) a. f' j. ]
2262305 ALLEGRO_EDITOR     UI_GENERAL    Assign Differential Pair form list box size too small to add signals
  M# [' V  c' U1 ^2 M2086574 APD                OTHER         APD is showing duplicate layer text on the vias, U( B  h+ ?4 ~: w7 U3 G
1723825 APD                SCRIPTS       Allegro Package Designer in release 17.2 is not writing out to either jrl files or script files in real time.( h* ~8 _" W$ J. m
2186363 APD                UI_GENERAL    Text on the Pin is not visible until zoomed in to certain extent6 S9 J& ^8 D. C9 y* W7 L
2253484 APD                WIREBOND      APD stops responding when running 'wirebond soldermask create' with 'Measure from soldermask pad'
" [9 B) s7 G) }5 r) G7 ~+ D) q. |( [2241725 CAPTURE            DRC           Waive DRC option not working from batch DRC window$ M3 c- r' }0 p1 e
2243645 CAPTURE            DRC           Online DRC bug in release 17.4-2019, hotfix 004 - offpage connector does not have wire; C2 T8 X7 A/ P* O
2250867 CAPTURE            DRC           Hanging wire custom DRC not working when selected standalone5 c$ U. T, `8 J
2252912 CAPTURE            DRC           Unable to create new DRC file using Browse button in DRC window
4 S# ?, b. \1 x8 t% h2047391 CAPTURE            PART_EDITOR   Pin type cannot be changed in release 17.2-2016, hotfix 051- i- L2 n- [2 n
2183187 CAPTURE            SCHEMATIC_EDI OrCAD Capture: Ctrl + N seems to call a legacy dialog that allows projects to be created with no name
$ g, u: R$ i% p- L' ~8 `2190602 CAPTURE            SCHEMATIC_EDI Cascading options of Window menu not working in OrCAD Capture in release 17.4-2019
( K3 _6 C8 a3 d3 @$ U2194374 CAPTURE            UX            Design Sync issues: Session log does not report information about errors
# e0 g* R& }* J% c+ y2183037 CIS                LINK_DATABASE CTRL-L shortcut for Link DB-Parts for Query in CIS-Explorer not working
" G! Q7 j0 k, h' ]6 F5 v2201323 CIS                PLACE_DATABAS Capture CIS displays empty dialog on placing part from database in release 17.4-20196 n6 i, N: D# K6 G
2216963 CIS                PLACE_DATABAS Light Theme: Warning text not visible in Capture CIS dialog
6 X( Z% ~  H9 E% J6 i: ?8 u2246354 CIS                PLACE_DATABAS Warning (ORCIS-6159) pop-up window is blank.8 N& t3 s; q1 K3 R4 i$ g
2230651 concept_HDL        CHECKPLUS     Discrepancy in the 'checkplus' marker files
, o2 A; m2 F! d7 I2237145 CONCEPT_HDL        CONSTRAINT_MG T-Points match groups get deleted after saving a design
. g) e# G; A5 H9 S' X1 o/ h- H# z2246452 CONCEPT_HDL        CORE          Page information gets removed from 'master.tag' of the top-level design when subdesigns are read-only9 T  e! x  I/ {2 Z
2057490 CONSTRAINT_MGR     CONCEPT_HDL   Constraint Manager Worksheet flips after running hier_write when CM is open
. |* W8 a' Q0 o9 G: r9 n2 |+ o9 }2236329 CONSTRAINT_MGR     CONCEPT_HDL   Pin Pairs not added to Match Group
& u/ v( f9 U! A, @" y* B2214367 CONSTRAINT_MGR     INTERACTIV    CSet assignment matrix sorting in Net Class-class random in Capture to Constraint Manager flow
* z1 H  F! o  T% x# @% l. o* L. c2243574 CONSTRAINT_MGR     OTHER         CM SKILL cmxlPutAttribute() cannot set constraint value) {0 o' A& ?) I' C8 b
2259598 CONSTRAINT_MGR     OTHER         Importing netlist: Error for electrical constraint data (pstcmdb.dat) import
. U  H: ^9 M$ i* [. F4 o1 B2207862 CONSTRAINT_MGR     SYSCAP        Save icon and 'File' - 'Save' menu in Constraint Manager is inactive
& `* H# z( w8 X8 i( B2200316 CONSTRAINT_MGR     UI_FORMS      Expanding 'Analysis Mode' form resets column width
" X+ y- O+ e4 V& D! O" U2097479 PCB_LIBRARIAN      CORE          Symbol import in Part Developer does not show the correct pin shape.) n* L3 r- ?. V* |6 P# G
2145385 PCB_LIBRARIAN      CORE          Error-SPLBPD-972 reports missing parentheses in the ALT_SYMBOLS property of a part6 C0 V9 @+ }0 C
2202622 PCB_LIBRARIAN      CORE          When adding a new pin to a symbol in Symbol Editor, the space between pins changes
; w; y! _, }" C/ B1955570 PCB_LIBRARIAN      FLOW          Using the PACK_SHORT property with more than 256 characters does not work or report an error on packaging: e# s0 }2 G+ \8 S0 `+ n$ M$ @
2072190 PCB_LIBRARIAN      FLOW          Allow PACK_SHORT property value longer than 255 characters* [# A6 |3 M, t' A; P
1720395 PCB_LIBRARIAN      IMPORT_OTHER  Converting OrCAD Capture OLB to Design Entry HDL library adds braces to pin number+ k2 Y2 q  O/ K
2141340 PCB_LIBRARIAN      SETUP         SPLBPD-216 Error logged in PDV even when MAX_SIZE Sheet is defined
0 s; @$ g. ]  }( Z1 J2214973 PCB_LIBRARIAN      SETUP         Unable to apply symbol property templates when PDV lock directives are set' n% [7 L3 Y2 u( [' @6 P( C, G4 t2 G
2257527 PCB_LIBRARIAN      SETUP         Locking PDV directives prevents applying symbol property templates
' K8 W# i; g! v2 l" m- ^2033898 PCB_LIBRARIAN      SYMBOL_EDITOR Running Symbol Editor with no arguments results in a background process, not an error.. i. |5 v0 O, {$ W
2093849 PCB_LIBRARIAN      SYMBOL_EDITOR Symbols and font sizes appear different when placed in designs
+ F7 s, a) T) Z! _1 e% o2200399 PCB_LIBRARIAN      SYMBOL_EDITOR Multiple issues observed when editing parts in the New Symbol Editor
7 |( [# v9 ^5 v) b* H7 \2218940 PCB_LIBRARIAN      SYMBOL_EDITOR Duplicate pins cannot be removed" P5 {% k4 j2 [3 x: P
2230542 PCB_LIBRARIAN      SYMBOL_EDITOR Bus pin location changes after expanding or collapsing pins in Symbol Editor
% x( r& |. S. @; T. C2239303 PCB_LIBRARIAN      SYMBOL_EDITOR Expanding and collapsing a bus is changing the msb and lsb for the pin name
9 ]. Z& |+ }5 x, r) {2243431 PCB_LIBRARIAN      SYMBOL_EDITOR Group of pins that are not adjacent cannot be moved together
5 D9 R  [# i( |8 G7 Z6 o0 [7 j$ z2029056 PCB_LIBRARIAN      SYMBOL_EDITOR Unable to change Grid Settings in Part Developer
' ^) j; D( t8 ]6 P  f6 _% Y+ @4 M2149948 PCB_LIBRARIAN      SYMBOL_EDITOR New Symbol Editor and System Capture moved pins from 0.01 grid to 0.05 grid.; r; ?4 ^7 ]+ l
2206975 Pspice             MODELEDITOR   PSpice Model Import Wizard symbol preview readability improvement requested* ^" S! z; `" m/ B8 N9 l' n+ C
2211187 PSPICE             MODELEDITOR   Model Editor color scheme not readable$ i2 Q4 x! D6 q+ T
2214415 PSPICE             MODELEDITOR   Symbol view in Model Import Wizard has a visibility problem1 {" B) B& H8 x+ k$ @7 x) m
2199570 PSPICE             PROBE         Unable to 'select sections' after Monte Carlo runs with Temperature3 H/ G& p/ C+ d! O, B
2244140 PSPICE             PROBE         Not able to select multiple sections to plot in probe! F1 {5 |( w# I' i' t
2249565 PSPICE             PROBE         Selecting multiple traces for PSpice A/D Monte Carlo run not working9 t- }: k) {9 y1 P
2171626 PULSE              CORE          Pulse crashed with error related to third-party development kit platform issue
# _) J4 q: I' s2221523 PULSE              UNIFIED_SEARC Cannot log in to third-party search providers but can log in to Cadence Online Support( K7 v3 c" Z% J0 x" z- N: @
2019229 RF_PCB             OTHER         Layer conversion file data does not update GDSII layer mapping using Package Symbol Wizard# W4 t9 p, M* u% B+ W
820288  SIP_LAYOUT         COLOR         Layer Priority command does not seem to be functioning
. z# Z7 I& [7 X  g& ^( h820305  SIP_LAYOUT         COLOR         Layer Priority menus do not match the Color dialog in the package substrate tools
. ?0 C% j  t1 ]& m+ g# k2256044 SIP_LAYOUT         DATABASE      Fix teardrop does not work for some situation: Deleting fixed fillets  y1 E/ l' J5 p  A' }6 S2 f3 C
2254932 SIP_LAYOUT         DEGASSING     APD Plus generating assertion failures when running degassing mode with script1 T+ w' A/ w2 T* V4 a0 Q3 e0 x3 ]3 G
2106314 SIP_LAYOUT         INTERACTIVE   Large design causing severe lag in Windows Server machine' \" s  J: Z; D! l1 ~. i
2096239 SIP_LAYOUT         STREAM_IF     Database fails to create stream out file7 n/ n6 N3 m) `% e+ w9 T
2079071 SIP_LAYOUT         SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die3 m" V3 ~! X, {2 x  i1 _7 i1 f
2251630 SIP_LAYOUT         WIREBOND      'Change Profile' does not change the diameter of the wire bond& w+ @- p" ]) Y4 U0 v/ u! R
2253633 SIP_LAYOUT         WLP           Advanced degassing passing illegal arguments to dba routine
' D+ m* C; x% W; ^6 |6 S2259630 SIP_LAYOUT         WLP           Advanced WLP: Import PVS DRC results in error0 N  s3 z% L1 p' f# F* H
1968437 SYSTEM_CAPTURE     ASSIGN_SIGNAL Net name pasted in lower-case though uppercase input is enabled
( h- q5 f1 S3 O2 H6 j* H  O2131976 SYSTEM_CAPTURE     AUTOMATION    syscap exits when run with the -tclfile argument and an invalid Tcl file
! ]4 |7 P! ~$ z: l$ b1983063 SYSTEM_CAPTURE     BLKDIAGRAM_AU Auto Shapes are being shown as part of components
8 h8 O$ V; p2 Q0 a1977673 SYSTEM_CAPTURE     COMPONENT_BRO adding reference blocks through add component error when cell name matches design name: D2 @+ r& j9 }$ j- y! E
2247567 SYSTEM_CAPTURE     COMPONENT_BRO Symbol property placeholder changes not updated on the canvas; e" z- W% p: W. W6 ~
2027100 SYSTEM_CAPTURE     COMPOSITE_FIL pstdedb.cdsz and netlist preview in System Capture is not being updated when individual netlist files are written
/ ?/ _, e5 P8 ]0 ]' x, k1863460 SYSTEM_CAPTURE     DARK_THEME    thumbnail preview of pages is in light them but dragging the page the previes is dark7 @( L- T( E- G" f; {
2168622 SYSTEM_CAPTURE     EDIT_SEARCHRE Reports from Find Results are dumped even when the operation is canceled
' U2 c9 N; [6 i- u" Q$ ^4 h3 k2168625 SYSTEM_CAPTURE     EDIT_SEARCHRE Sort icons for columns in 'Find Results' are incorrectly placed: appear to be in adjacent column0 {$ T, j8 U' x
1895142 SYSTEM_CAPTURE     EXPORT_PCB    System Capture incorrectly reports unsaved changes when closing after running export physical
6 N0 ~$ g: R, v( h. r/ H. _1931660 SYSTEM_CAPTURE     EXPORT_PCB    SDA is non-responsive while Allegro launches and opens a board when launched from SDA. _5 {4 t9 \# R& D( x; ?
2087387 SYSTEM_CAPTURE     EXPORT_PCB    System Capture: After Export PCB completes, busy cursor shown for a while4 [, m& \3 m/ T( N, U
2202179 SYSTEM_CAPTURE     FIND_REPLACE  Replacing a net name with the same name by using Find and Replace results in a crash
/ y# V. h0 C: x1 I4 Q3 j6 G1843885 SYSTEM_CAPTURE     FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
1 |( d2 O+ o0 j8 F* m* r1993208 SYSTEM_CAPTURE     FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
" Z: A- E" m! ?* M7 p2231399 SYSTEM_CAPTURE     IMPORT_BLOCK  'importBlock' Tcl command not working when using a script
7 s3 \) q: U8 Z% y3 M9 v+ J* F1907729 SYSTEM_CAPTURE     IMPORT_DEHDL_ Import DE-HDL sheets -  differential pair properties on nets are lost
& L* h/ a- R; }/ M2025949 SYSTEM_CAPTURE     IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not  translate in System Capture
4 Z$ p: Z) B9 W7 q8 p1942542 SYSTEM_CAPTURE     IMPORT_PCB    System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks0 V0 M% M8 i' z5 k
1982320 SYSTEM_CAPTURE     IMPORT_PCB    View files are not created in the schematic-to-board flow
0 R6 h$ [( o) F1 m' ?7 c2117532 SYSTEM_CAPTURE     MENUS_AND_TOO Ability to customize menus for a site: s8 Z9 p; x  T8 R9 @+ C6 P* Y3 u+ o
2213478 SYSTEM_CAPTURE     MENUS_AND_TOO Help - About menu item appears twice% X( R! \8 x" J
1910941 SYSTEM_CAPTURE     MISCELLANEOUS Parts that are not in any schematic page appear in netlist and BOM
8 k8 n% s2 I8 K1967614 SYSTEM_CAPTURE     MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
: z* ?& a& d) ^  r* u2189846 SYSTEM_CAPTURE     MISCELLANEOUS Inconsistent display of same font
7 O5 G( _5 X+ c) a4 h6 ]2178961 SYSTEM_CAPTURE     NOTES         Cannot add Japanese text in notes in release 17.4-2019 on Windows 101 U8 ~- b' i' b7 K
1973437 SYSTEM_CAPTURE     OPEN_CLOSE_PR Opening a design crashes System Capture! V  N7 U( G+ ?8 V3 X, s5 s5 M
2079857 SYSTEM_CAPTURE     OPEN_CLOSE_PR System Capture: Unable to select design to open if license selection box is canceled the first time& [$ O8 L' s' J3 ~4 ]
2065025 SYSTEM_CAPTURE     PACKAGER      Export to PCB Layout reports wrong path but exports correctly0 V  S- d1 x1 I5 ~) b; E. \. r
2229611 SYSTEM_CAPTURE     PACKAGER      Path for the 'packaged' folder shown in the 'Export Physical' is incorrect' H7 z" n" p0 i& T) A+ A
1993146 SYSTEM_CAPTURE     PROJECT_EXPLO Cannot move page up by only one position
6 R0 e1 }  _0 d" p, y) |" G1892120 SYSTEM_CAPTURE     PROPERTY_EDIT Some parts are missing reference designators and some have two properties - RefDes and REFDES0 `) ]6 g) Z' A; v" a8 E
2201060 SYSTEM_CAPTURE     PROPERTY_EDIT Some of the icons in the Properties window do not have tooltips
" R3 b/ E8 o) s, t7 s$ @2246667 SYSTEM_CAPTURE     SCRIPTING     Running the 'replay.tcl' script gives an invalid command name error
0 d- z% L0 q9 _2010032 SYSTEM_CAPTURE     SHORTCUTS     Cannot enter Page-Up/Page-Down as shortcuts
8 n* A) `" ^( ~0 Y3 ]7 f2017985 SYSTEM_CAPTURE     TDO           Allegro System Capture ability for multiple users to open a design
) j0 v) \- N* K$ g+ n2 i9 T+ l2106743 SYSTEM_CAPTURE     TDO           Ability for multi-user access to the same schematic
( R4 {4 ^( O1 g. r8 z+ k8 }$ A2209628 SYSTEM_CAPTURE     UI            Tooltips for Design Rule Checks are getting truncated) r- }8 W5 ]0 ~* U5 ^- z$ e4 A
1990258 SYSTEM_CAPTURE     VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
% q( _0 ~! D" h) |3 m/ |. |. B7 }2032005 SYSTEM_CAPTURE     VARIANT_MANAG Custom variables not saved for variants
  }; v2 {' J0 B6 r% f2228299 SYSTEM_CAPTURE     VARIANT_MANAG CAP parts should not show up in the Preferred Parts list when changing a RES" }4 a3 O9 a5 b7 ?6 ]/ R1 a6 ]! q
1627835 SYSTEM_CAPTURE     WIRING        Inconsistencies in wire movements& q- k  L3 m7 C, a1 |9 }, \
1670888 SYSTEM_CAPTURE     WIRING        Rotation error when a component is connected to a power symbol
  Z/ y2 ]3 R( b0 ]/ Z1721863 SYSTEM_CAPTURE     WIRING        Net names move to random locations when components are moved around the canvas.
1 \6 ~4 u) p( w' J2 M- e. |; g1960130 SYSTEM_CAPTURE     WIRING        Disconnected nets when using the mirror option/ i- _. f$ C! B$ y( Z
1961274 SYSTEM_CAPTURE     WIRING        XNet removed during pin swapping. r& q# C( f7 u1 E8 y# i2 e+ `" M
1968463 SYSTEM_CAPTURE     WIRING        System Capture should not allow illegal characters to be entered for net names
0 t  e' `: X; m& e3 `2 g2 V1973426 SYSTEM_CAPTURE     WIRING        Selecting multiple net names and trying to delete only deletes one net name.
$ @1 E" J0 H0 E2 u1978381 SYSTEM_CAPTURE     WIRING        'oops' does not remove the first vertex placed* O. d% S" v# z; j! y' C( r* n
1985029 SYSTEM_CAPTURE     WIRING        Net aliases are not dragged with circuit, they appear to move after the circuit is dropped9 A  Z0 F: G2 ]9 h
2013647 SYSTEM_CAPTURE     WIRING        Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections
. ?; n# v1 n8 s% L% B2014188 SYSTEM_CAPTURE     WIRING        Context menu not working in Variant mode* {4 A5 S" o4 Q0 a6 |( x, W9 c
2041879 SYSTEM_CAPTURE     WIRING        XNets generated for nets with pull-up resistors
( `6 n4 d( ]  F1 F7 b2050533 SYSTEM_CAPTURE     WIRING        Need an option to increase junction dot size
0 o& K$ s# Q3 P2061877 SYSTEM_CAPTURE     WIRING        Unable to add a power symbol with the Place - Special Symbol menu) F2 R6 j2 U  v- h  J( N0 \
2079409 SYSTEM_CAPTURE     WIRING        Increase the size of the wire connection dot in System Capture2 Y; ~( y+ g7 n8 T
2081884 SYSTEM_CAPTURE     WIRING        Symbols take a long time to move, and results in DRCs and broken connections' I% k3 D$ b; h0 N
2085263 SYSTEM_CAPTURE     WIRING        System Capture: Focus lost from the Format tab if font name starting with typed letter is not present
' r. P; Y3 C  ^2 _, J+ b* O2089569 SYSTEM_CAPTURE     WIRING        Ability to specify the solder dot radius size
* P* ~6 j5 R7 g4 w# h/ R# m  w
8 w% n+ O. Z# [3 @- K
QIR1详细特性说明: Hotfix_SPB17.40.007_README-Release_Notes.pdf (2.51 MB, 下载次数: 55) : N  B1 h3 I9 u' B6 d
待我上传完后附上链接,这次QIR1比较大,4.59 GB 1 I, y8 ?' P& }8 Z

* r: X" i" p* v, [; ]

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2 |; W' S* _6 ]0 U5 D# ~

/ [. [3 X6 e# X& Y5 i$ U% y  @
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6 a; @- U! q8 H/ E% i* N; f6 O% n# P2 F4 J8 w

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  • TA的每日心情
    开心
    2024-2-21 15:59
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    [LV.8]以坛为家I

    推荐
    发表于 2020-6-8 09:10 | 只看该作者
    已在本版置顶帖中更新了该补丁0 f  J/ K9 a+ y% \2 D" f
    https://www.eda365.com/thread-276156-1-1.html

    该用户从未签到

    推荐
     楼主| 发表于 2020-6-12 13:26 | 只看该作者
    laurence 发表于 2020-6-8 11:35
    ' `. |. R  D7 f, F更新QIR1后,出现严重bug,一导入网表PCB程序就会crash,请问大家有同样问题么?

    8 }8 F' ], h7 r3 g5 O  G6 T$ d强烈建议不要再之前的基础上安装补丁!必须完全卸载之前安装的17.4,然后全新安装,然后再装hotfix,否则会有些奇怪的问题!
    ; w$ |  V4 O8 `; o5 V

    该用户从未签到

    推荐
     楼主| 发表于 2020-6-12 13:29 | 只看该作者
    金志峰 发表于 2020-6-11 08:52
    : F$ Y$ Z1 k& {试着把.动态铜自动smooth disable掉试试,我这边更新动态铜会crash掉    不知各位有没有遇到过。

      g# n8 p$ H+ |7 x- a" j1 x动态铜自动smooth后软件会crash掉已经解了!全新安装17.4,然后再装QIR1,就没有问题了
    2 v6 L6 ~7 b' _, R: x. N1 l

    该用户从未签到

    2#
     楼主| 发表于 2020-6-8 02:54 | 只看该作者
  • TA的每日心情
    擦汗
    2019-12-12 15:00
  • 签到天数: 13 天

    [LV.3]偶尔看看II

    4#
    发表于 2020-6-8 08:49 | 只看该作者
    感謝大大的熱心分享囉!!

    该用户从未签到

    5#
    发表于 2020-6-8 09:06 | 只看该作者
    希望早日上传链接. 感谢分享.

    该用户从未签到

    7#
     楼主| 发表于 2020-6-8 10:50 | 只看该作者
    本帖最后由 金志峰 于 2020-6-9 01:39 编辑
    , E/ t0 Z6 i' r: a+ S% z, i% Q/ h
    dzkcool 发表于 2020-06-08 09:10:190 y( P# a6 y! d5 [6 T/ M% E5 R0 K9 Q/ Q
    已在本版置顶帖中更新了该补丁
    ; [9 [- q6 Y8 L) w/ _https://www.eda365.com/thread-276156-1-1.html

    . D2 c! G" ^) e; E! tOK,那我就不上传了
    8 }- o  H0 ]. U* X1 j4 o. C

    “来自电巢APP”

    该用户从未签到

    8#
    发表于 2020-6-8 11:35 | 只看该作者
    更新QIR1后,出现严重bug,一导入网表PCB程序就会crash,请问大家有同样问题么?

    点评

    还是不行,PCB导入网表就宕掉了  详情 回复 发表于 2020-6-13 17:57
    我也遇到相同的问题了。  详情 回复 发表于 2020-6-12 17:54
    强烈建议不要再之前的基础上安装补丁!必须完全卸载之前安装的17.4,然后全新安装,然后再装hotfix,否则会有些奇怪的问题!  详情 回复 发表于 2020-6-12 13:26
    试着把.动态铜自动smooth disable掉试试,我这边更新动态铜会crash掉 不知各位有没有遇到过。  详情 回复 发表于 2020-6-11 08:52
    我这边没有遇到……   详情 回复 发表于 2020-6-8 17:25

    该用户从未签到

    9#
    发表于 2020-6-8 13:06 | 只看该作者
    给力,给大神赞一个
  • TA的每日心情
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    2022-6-29 15:11
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    [LV.9]以坛为家II

    10#
    发表于 2020-6-8 14:30 | 只看该作者

    该用户从未签到

    11#
     楼主| 发表于 2020-6-8 17:25 | 只看该作者
    laurence 发表于 2020-06-08 11:35:238 g5 o" T; m' n% r: ]" S! Y4 I9 U
    更新QIR1后,出现严重bug,一导入网表PCB程序就会crash,请问大家有同样问题么?
    + s* v& U) N% x5 |3 Y% L/ O- D

    5 @, r+ W6 q9 @! x# K我这边没有遇到……
    4 ~5 q' [3 X3 @+ N9 ]

    “来自电巢APP”

    该用户从未签到

    12#
    发表于 2020-6-8 20:47 | 只看该作者
    感謝大大的熱心分享!
  • TA的每日心情
    开心
    2020-7-25 15:21
  • 签到天数: 1 天

    [LV.1]初来乍到

    13#
    发表于 2020-6-9 10:45 | 只看该作者
    能不能做种子呀,那个百度网盘真的太慢了  只有28KB/s
  • TA的每日心情
    无聊
    2021-8-31 15:05
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    [LV.1]初来乍到

    14#
    发表于 2020-6-9 11:23 来自手机 | 只看该作者
    我的破解完后pspice不能仿真了,怎么解决?

    该用户从未签到

    15#
     楼主| 发表于 2020-6-11 08:52 | 只看该作者
    laurence 发表于 2020-06-08 11:35:23
    - @" ?' u2 t5 J9 `! c更新QIR1后,出现严重bug,一导入网表PCB程序就会crash,请问大家有同样问题么?

    + s1 r1 y  N# Y/ ~' O- A1 @
    - s- p8 Y: @8 z% X试着把.动态铜自动smooth disable掉试试,我这边更新动态铜会crash掉    不知各位有没有遇到过。* c! k% S4 o, s8 Q! L! V

    “来自电巢APP”

    点评

    动态铜自动smooth后软件会crash掉已经解了!全新安装17.4,然后再装QIR1,就没有问题了[/backcolor]  详情 回复 发表于 2020-6-12 13:29
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