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本帖最后由 金志峰 于 2020-6-8 03:33 编辑 1 I! v0 h" u& x
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cadence orcad and allegro 17.4-2019 QIR1新特性
9 t( H7 a2 d; k( v! y, I; a·焕然一新的图标及UI
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QIR1中全新启动界面 （点击图片放大）6 g8 x3 M1 o+ Z# T0 |
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QIR1中全新启动界面（点击图片放大）
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QIR1中capture官方Dark主题（点击图片放大）(QIR1中UI界面中所有图标也全部更换全新并统一了)
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: I" P' W. s8 P; u( m1 k7 ^7 gQIR1中capture官方Light主题（点击图片放大）( A2 ^7 [' t# ^5 @
(QIR1中UI界面中所有图标也全部更换全新并统一了)
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, Y; ?: d$ @" {, N1 C# |2 GQIR1中PCB Editor新增官方Dark主题（点击图片放大）* q7 K5 O% b, ]. `! e: U4 h3 C0 U8 B
(QIR1中UI界面中所有图标也全部更换全新并统一了)+ F$ R& g. N# N
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4 G J* |! Y. K4 c9 r! ]6 {6 M! IQIR1中PCB Editor官方Light主题（点击图片放大）
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Fixed CCRs: SPB 17.4 HF007: c! G( ?8 ~; T8 h9 t* h
05-21-2020
% ]0 C# p: R- t: o: j% ^========================================================================================================================================================8 w% s7 B$ Z6 n3 d; |# A6 L# g
CCRID Product ProductLevel2 Title3 x: X& t q X% r9 B" `5 P$ T2 X8 h
========================================================================================================================================================
9 }, t% Y9 r( y, i9 T, o4 X2247686 ADW CORE Allegro EDM: Unable to create a project using a newly created flow9 k8 ^3 z- O7 C, r& k1 R9 y
2137594 ADW DBADMIN EDM is not allowing changes to STEP models
1 F0 l* E4 K! u) P4 H! Z2135452 ADW DBEDITOR DBEditor poor peRFormance in high-latency networks' h0 p9 U( ~: q: W2 Z
2113265 ADW LIBDISTRIBUTI Various database operations take a long time; rebooting server seems to fix the problem4 u' L" J5 o2 z6 c. U
2122941 ADW LIBDISTRIBUTI Lib_dist execution taking a long time to run; Capture CIS DBC file appears to be taking the most time
; U" c" u9 K1 w2127319 ADW LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250)' P2 c: k9 y! a! U+ y# w
1975317 ADW PART_BROWSER Space at the end of the line in CDS.LIB results in zero libraries being shown in System Capture library search
; x- ~, a$ C' r4 z2078057 ADW PART_BROWSER Symbol Graphics preview is not available in Designer Servers
7 a7 C" w; P. B- J2092863 ADW PART_BROWSER System Capture library search is not displaying the symbol and footprint preview8 b9 B# V+ s2 `( H' g: l9 X8 P
2086463 ADW PART_MANAGER System Capture cannot add components when accessing remote machine via Citrix% V- M+ H3 L% C0 A
2092868 ADW PART_MANAGER Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not flow from pstchip6 l9 R" D3 j9 O9 L6 V
2092872 ADW PART_MANAGER System Capture stops responding when importing from DE-HDL
( c- a. F1 k0 n3 [7 A0 T! W2113226 ADW PART_MANAGER System Capture stops responding while importing DE-HDL sheets1 E1 z3 D' x, Y7 ^: c
2212406 ADW PART_MANAGER Allegro System Capture: Part Manager is deleting properties from all instances upon Update
9 w, I; K( h4 T% s2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
+ G" c$ H1 Z Y% A) g5 W2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to Team Design
0 Z5 @, t" c1 d! d# f& l2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
, a+ B/ L: O) v m: i! j" y2048086 ALLEGRO_EDITOR 3D_CANVAS Wire bonds are not linked to die pad when component is embedded body down6 U: z# v: W& Q
2051277 ALLEGRO_EDITOR 3D_CANVAS Vias are offset from board in Z direction in 3D Canvas
5 x# f; R1 e0 {; c$ N1 J4 T2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas, _& e$ j) h! O. C- V4 v) Y3 E0 G P
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
6 M: ^: O7 s: p8 E" d2079732 ALLEGRO_EDITOR 3D_CANVAS Enhance 3D Canvas to merge the lines segment and overlapping lines and shapes
' z8 c. v7 J; J' R, L2206045 ALLEGRO_EDITOR ARTWORK Artwork Control Form fails to create film if Film record has a period (.) in the title
5 ^. _5 V* Q; ^2209200 ALLEGRO_EDITOR ARTWORK PCB Editor stops responding on rebuilding apertures without rotation) n$ N1 z/ K! _1 ]7 E6 z
2244407 ALLEGRO_EDITOR ARTWORK Automatic editing apertures with rotation takes time in the General Parameters tab of Artwork Control Form
/ G1 r! z5 L0 B( f- }2267942 ALLEGRO_EDITOR ARTWORK Allegro PCB Editor stops responding when generating apertures in HotFix 006# z9 Z4 |6 e$ M# m7 B2 {0 w: d
567342 ALLEGRO_EDITOR COLOR Add option under View menu for 'load color view'6 `8 j8 G# B6 @" W( i! R5 a
637828 ALLEGRO_EDITOR COLOR Line highlights in 'shape select' command2 }7 d2 s' `1 F$ `0 ^
720274 ALLEGRO_EDITOR COLOR Add menu option for the 'colorview load' command$ ]/ J# S" W- f* r/ q' z
1602652 ALLEGRO_EDITOR COLOR Color/Visibility behavior variation using "Enable Layer Select Mode"4 _0 W2 s) l2 M
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set& z1 H6 v% i- }) Y. Y0 F& p* h2 _
2207580 ALLEGRO_EDITOR COLOR Component color is inconsistent when display_nocolor_dynamics is set.2 ~$ Y' y5 ^0 u
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow
- m& M6 B3 q6 i2250988 ALLEGRO_EDITOR DATABASE Inner Layer keep out as illegal subclasses: Shape object may not exist on layer ROUTE KEEPOUT/INNER_SIGNAL_LAYERS$ E! A" Q( u" U4 p
2096958 ALLEGRO_EDITOR DFA Cannot launch Constraint Manager after assigning CSet and closing* e4 D m$ o5 n; G) Z
2049681 ALLEGRO_EDITOR DFM DFF check for plating in via should not flag DRC for surface mount testpoint Via
! U J' o' e8 u7 l, D2155060 ALLEGRO_EDITOR DFM Inconsistent behavior in displaying DRCs for Via to Via spacing
8 n0 j1 M2 s% x4 _; M1 N8 @2166431 ALLEGRO_EDITOR DFM DesignTrue annular ring thru pin pad to mask checks compared to smd pin to mask checks are inconsistent in behavior. U: J5 }. d: C. n% S
2221975 ALLEGRO_EDITOR DFM DFM missing mask check reporting mask is missing when pins have a mask geometry overlaying them.
9 w6 k2 f; N' h3 Q2 H2249498 ALLEGRO_EDITOR DRAFTING When a Symbol with a Dimension is placed on the board, an extra Dimension is added to the Symbol origin.7 z% i- [# _& G' p- h; }0 f! z2 P( G
2250631 ALLEGRO_EDITOR DRC_CONSTR Cannot import netlist into design due to illegal DRC element: no DBDoctor error A: |$ k2 n. ]( ?, O
1794593 ALLEGRO_EDITOR EDIT_ETCH Unable to deselect return path vias selected when creating High-speed via structures
1 S; I* e/ T* R; r+ q, ^, Y* O1 \2099538 ALLEGRO_EDITOR EDIT_ETCH Gloss - Via Eliminate shifts traces to another layer
# p# ~ R# d, m. _2204339 ALLEGRO_EDITOR EDIT_ETCH Differential pair line lost during slide operation
, I! h3 w1 ~* ~' D2208938 ALLEGRO_EDITOR EDIT_ETCH Slide operation makes one of the differential pair cline invisible
/ G) Z5 b$ Y4 g* U2222047 ALLEGRO_EDITOR EDIT_ETCH One of the traces disappear when sliding a differential pair in single trace mode/ L; ^& B' f8 H# ]8 J
2233991 ALLEGRO_EDITOR EDIT_ETCH One cline of a differential pair disappears temporarily upon sliding the Differential Pair in Single Trace Mode" t4 t. H7 o# K# A, U6 J
2240827 ALLEGRO_EDITOR EDIT_ETCH Cline of a Differential pair net disappears after sliding the other net of the Differential pair7 g2 \+ s! |( c
2245775 ALLEGRO_EDITOR EDIT_ETCH Differential pair slide in single trace mode removes other trace
* V' {$ H8 c8 s9 N5 X* Z1813358 ALLEGRO_EDITOR GRAPHICS Allegro PCB Editor enables shape boundary when disabling etch layer in Visibility pane
, \ B9 t7 K$ F4 i- y1911613 ALLEGRO_EDITOR GRAPHICS The subclass for boundary class stays on, even if Subclass for Etch Class is turned off from Visibility tab/ O: R Z4 ]5 y2 R' E8 n0 @
1966343 ALLEGRO_EDITOR GRAPHICS Shape boundary remains enabled even after turning off the etch layer visibility7 D ]5 J. Y, d$ L: X: f
2195276 ALLEGRO_EDITOR GRAPHICS Selecting File view is slow7 g# R/ u1 w: u w, R5 n) T
2031883 ALLEGRO_EDITOR INTERACTIV Sub-Drawing: Clipboard origin point is not set correctly( V0 \% ^2 w4 e
2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Shape ANDNOT operation0 r# N1 F; [" `2 T
2069247 ALLEGRO_EDITOR INTERACTIV DFA bubble on wrong layer after mirroring the part
4 I% S: a S4 q2103711 ALLEGRO_EDITOR INTERACTIV Placement edit mode popup 'Rotate' leaves ghost image in the background4 E Q' H3 z, x
2136859 ALLEGRO_EDITOR INTERACTIV DFA Problem if we mirror component while placing0 V1 h- U# u6 w0 `) b* R- O
2165027 ALLEGRO_EDITOR INTERACTIV Different behavior in OrCAD Capture when using crossprobe to select Power nets
0 u) u7 X+ f! g9 `6 |8 `, G2240235 ALLEGRO_EDITOR INTERACTIV The design file name changes automatically to board template name while creating new board (wizard).
2 Q! G9 g' Q) t( n3 D q |6 r2244765 ALLEGRO_EDITOR INTERACTIV License 4150+226 does not have AiDT/AiPT in release 17.2-20160 L; |# f5 J: G. S( C1 X
2259800 ALLEGRO_EDITOR INTERACTIV DFA DRC circle not shown on the layer of placement in Placement App Mode: S7 v* n) U. w% C% U& x
2120420 ALLEGRO_EDITOR INTERFACES Drill figures missing in the exported PDF if drill legend deleted) o' b) ~1 S" M# N
2136454 ALLEGRO_EDITOR INTERFACES Export - PDF output is not correct
2 r+ v$ d- k- ~1 V, P2116748 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets4 |& N3 f" ~. e0 b# E% N% E
2138977 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to 17.2-2016, HotFix 0573 ?+ m1 f5 M0 r# e) U
2247167 ALLEGRO_EDITOR IN_DESIGN_ANA IDA Impedance Analysis: Add an option to export CSV automatically
0 B/ d/ y) P4 m: |2222638 ALLEGRO_EDITOR IPC Documentation Editor crashes with error: Failed to complete the job because of unspecified error
+ W, G8 r2 L; k0 T2106425 ALLEGRO_EDITOR NC Disable undersize regular pad and oversize soldermask pad for start layers in Backdrill Setup and Analysis- s5 E6 s& _3 p1 D+ p) H
2091932 ALLEGRO_EDITOR OTHER Unsupported Prototypes command missing for the OrCAD licenses2 D d% f) r0 }/ U3 O4 G/ B1 G1 W
2221345 ALLEGRO_EDITOR OTHER Speed up Allegro PCB Editor startup by removing check for defunct PCB/Package co-design capability (NG_450)* g" f$ t1 g8 |! p2 Y
2257934 ALLEGRO_EDITOR PLACEMENT Error (SPMHGE-626) on place component: Symbol not valid on any layer
9 \# k" C6 { H7 ]: [2 Q7 y+ i2 L0 I1001000 ALLEGRO_EDITOR PLOTTING File - Plot in PCB Editor does not plot more than one copy
" z% R1 B) M! M- ]' W2234538 ALLEGRO_EDITOR REPORTS Allow Unused Blind/Buried Via report to run as Batch Process through the reports batch command& a; m' p! A5 J2 y: y z' e
2222738 ALLEGRO_EDITOR SCHEM_FTB Netrev not completing, showing error for electrical constraints data (pstcmdb.dat) import; Y1 v* l9 E' I! H* Z/ M
2255426 ALLEGRO_EDITOR SCHEM_FTB Netrev is running for hours without closing
' Y, x, H2 C$ j1702190 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script file: Some sub-classes not created and error for form field label6 V1 F* g- O$ d' i% O; r b1 K8 x
1791099 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor does not terminate when the script is run with '-nographic'
8 i$ h5 s' W8 n1791267 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script does not run with '-nograph' in release 17.2-2016
3 H- P: z/ p/ B( F5 G; ~1892520 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with '-nographic'
# t" G. b4 Q' [1962010 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with -nongraph option
3 Q9 W) e9 K* C+ g0 D2056857 ALLEGRO_EDITOR SHAPE Shape boundary error by shape parameter, `' K6 a2 ]/ b5 E2 }3 x
2081946 ALLEGRO_EDITOR SHAPE Shape Update takes twice the time in release 17.2-2016, HotFix 053 as compared to HotFix 0471 R, M7 G& k/ c3 M
2104559 ALLEGRO_EDITOR SHAPE PCB Editor crashes while performing shape operation 'andnot'! a/ w* `2 v4 ~, B/ R
2108207 ALLEGRO_EDITOR SHAPE No Void Overlap option is not working in Auto Metal Balancing (AMB)
* s' t$ j' e4 d8 W ~$ i2240996 ALLEGRO_EDITOR SHAPE Detecting Shape Island: Ignored for copied or moved shape
* c- w7 V% C- \, }1 D- M2258758 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes when routing two signals together% ]+ ?8 d. G& k( C7 P
717389 ALLEGRO_EDITOR skill Ability to set and return the application mode using SKILL
. N8 N, Q: s; o: | J5 x853160 ALLEGRO_EDITOR SKILL Need ability to get and set application modes using SKILL
5 C- M# I4 f5 c8 T9 ]$ E981446 ALLEGRO_EDITOR SKILL Request the ability to get and set application modes using SKILL
7 T; D5 x# c5 u5 j6 T9 e' M1235409 ALLEGRO_EDITOR SKILL SKILL option to get application mode, o$ T- Q8 P- X7 _
1316962 ALLEGRO_EDITOR SKILL SKILL option to switch between application modes/ O, i+ _+ t0 T6 N7 z
1553621 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function
& u9 q4 T: T7 p# g/ ~1885442 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function.
9 r& `. w9 q `5 E) P2080351 ALLEGRO_EDITOR SKILL SKILL to determine current application mode
4 e- G1 o; n/ h2195645 ALLEGRO_EDITOR THIEVING Thieving pad cannot be added on some areas in the board in latest hotfix but could be added earlier m6 Q# @- o4 T% \6 m
1721594 ALLEGRO_EDITOR UI_FORMS STEP name Filter for STEP Package mapping form should be case insensitive1 @8 ~4 [0 k' r$ S! @; t6 d* V3 ~, L
2090604 ALLEGRO_EDITOR UI_FORMS Undo/Redo UI grayed out when invoking Color192
6 x4 }) O! O# \/ d. z2203278 ALLEGRO_EDITOR UI_FORMS 'Width' keyword in Place Rectangle field is grayed out when Place Rectangle is selected& N' l5 F. S$ A* k! B0 _8 j
2209172 ALLEGRO_EDITOR UI_FORMS Labels truncated by drop-down lists in Options ('Manufacture' - 'Drafting' - 'Relative Copy')3 p6 g; l Y' X* j
2239426 ALLEGRO_EDITOR UI_FORMS Cannot start text size with decimal in 'Design Parameter Editor' - 'Text' for English (Denmark) regional settings
R+ | S c+ m5 E+ t% B2245035 ALLEGRO_EDITOR UI_FORMS The right edge of the default Define Grid form looks cut off in 17.4.
* X' @/ h$ I4 U$ V2245955 ALLEGRO_EDITOR UI_FORMS Resizing of 'Reject Item Selection' window not possible in release 17.4-2019, HotFix 004
4 ~8 W/ Z& M% q+ N: D, e; I6 x2249202 ALLEGRO_EDITOR UI_FORMS Extra click required to activate Pass field in Autorouter form
% \; `" h! u4 S% D: H7 c" s2259605 ALLEGRO_EDITOR UI_FORMS Add ability to resize Reject pop-up2 B" F1 |% }) q& H
2090517 ALLEGRO_EDITOR UI_GENERAL Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane1 \7 E$ }3 w, k, S1 U9 P3 X
2092436 ALLEGRO_EDITOR UI_GENERAL RefDes length of input string for Modify Design padstack is limited to 20 characters0 ]$ t% g2 J) D3 B1 H7 _
2134781 ALLEGRO_EDITOR UI_GENERAL The Pin Class is missing in Options tab when creating or opening a Mechanical Symbol
0 B/ y" I* {; |9 F, @; R$ y2168026 ALLEGRO_EDITOR UI_GENERAL Edit Properties UI slow to launch for boards with many drawing properties
2 ]. y- ]2 L4 l2191267 ALLEGRO_EDITOR UI_GENERAL Changing Visibility of any object type disables links in Layer Select Mode in the Visibility pane; f; S& K# a' s1 n) w
2208018 ALLEGRO_EDITOR UI_GENERAL Text on BGA pins not visible in release 17.4-2019 if not zoomed to maximum
# |3 d) f8 n2 R1 o$ f8 e2225753 ALLEGRO_EDITOR UI_GENERAL dark theme does not respect TRBICON size for 4K monitors
+ e( j4 l& ?0 ~3 F1 I& Z! ~3 u2256841 ALLEGRO_EDITOR UI_GENERAL Enlarge the Shape Copy to Layers form as the window is quite small and not resizable4 g& Q$ w1 D0 h" A+ U9 O* [
2258019 ALLEGRO_EDITOR UI_GENERAL Canvas turns white after closing STEP Package Mapping window
" @: G0 o' H4 X" m7 L5 c2258167 ALLEGRO_EDITOR UI_GENERAL Enhance 'Shape copy to layers' window in release 17.4-2019 to expand or resize
# ^8 W3 Z* ]% V0 I2262305 ALLEGRO_EDITOR UI_GENERAL Assign Differential Pair form list box size too small to add signals- C4 e8 Q- A. ?1 u8 T- G$ ^
2086574 APD OTHER APD is showing duplicate layer text on the vias
. d. R. l$ N; x1723825 APD SCRIPTS Allegro Package Designer in release 17.2 is not writing out to either jrl files or script files in real time.
+ l0 K9 v, I' I, E8 I2186363 APD UI_GENERAL Text on the Pin is not visible until zoomed in to certain extent
) |* L2 F- ?& Y3 e, C2253484 APD WIREBOND APD stops responding when running 'wirebond soldermask create' with 'Measure from soldermask pad'+ q" @% |6 l8 m# R8 b' R
2241725 CAPTURE DRC Waive DRC option not working from batch DRC window
1 X' O0 n+ R$ Y" R# B; D8 L2243645 CAPTURE DRC Online DRC bug in release 17.4-2019, hotfix 004 - offpage connector does not have wire: O8 a5 F2 K: S+ a6 ~, `8 i3 N
2250867 CAPTURE DRC Hanging wire custom DRC not working when selected standalone1 c1 M. g/ A" ?. H9 z
2252912 CAPTURE DRC Unable to create new DRC file using Browse button in DRC window
: k! b7 e6 |% ~! Q/ ^5 }' E7 d+ T2047391 CAPTURE PART_EDITOR Pin type cannot be changed in release 17.2-2016, hotfix 051
* F9 @' L! P8 c# e2183187 CAPTURE SCHEMATIC_EDI OrCAD Capture: Ctrl + N seems to call a legacy dialog that allows projects to be created with no name5 R T, `- O9 \/ `6 {: ~: Q+ U
2190602 CAPTURE SCHEMATIC_EDI Cascading options of Window menu not working in OrCAD Capture in release 17.4-2019* ^$ n/ _1 K6 m/ I0 S: @% L7 ]
2194374 CAPTURE UX Design Sync issues: Session log does not report information about errors
* Q! A4 U j0 |' T: K- D" J2183037 CIS LINK_DATABASE CTRL-L shortcut for Link DB-Parts for Query in CIS-Explorer not working/ d' }! i) k) x& P* n
2201323 CIS PLACE_DATABAS Capture CIS displays empty dialog on placing part from database in release 17.4-2019
7 b3 \( l7 u( h2216963 CIS PLACE_DATABAS Light Theme: Warning text not visible in Capture CIS dialog
& \1 h4 u+ O( m! Y. i2246354 CIS PLACE_DATABAS Warning (ORCIS-6159) pop-up window is blank.3 S" x8 S; `/ y' \0 r1 H
2230651 concept_HDL CHECKPLUS Discrepancy in the 'checkplus' marker files
# S1 X( ~$ p. j4 r9 e- }2 J2237145 CONCEPT_HDL CONSTRAINT_MG T-Points match groups get deleted after saving a design
6 \, v. j- Z7 J! i8 j2246452 CONCEPT_HDL CORE Page information gets removed from 'master.tag' of the top-level design when subdesigns are read-only
) ~' }# A/ C, q3 Q; \+ ?2057490 CONSTRAINT_MGR CONCEPT_HDL Constraint Manager Worksheet flips after running hier_write when CM is open
6 b5 j. r2 O( p- a( o2236329 CONSTRAINT_MGR CONCEPT_HDL Pin Pairs not added to Match Group. C. N& i2 y* i
2214367 CONSTRAINT_MGR INTERACTIV CSet assignment matrix sorting in Net Class-class random in Capture to Constraint Manager flow
( Q4 ~ J6 ^7 y6 O+ T0 g2243574 CONSTRAINT_MGR OTHER CM SKILL cmxlPutAttribute() cannot set constraint value
" _* J% Z; D* x2259598 CONSTRAINT_MGR OTHER Importing netlist: Error for electrical constraint data (pstcmdb.dat) import
$ V9 t3 W% F. e9 B$ d2207862 CONSTRAINT_MGR SYSCAP Save icon and 'File' - 'Save' menu in Constraint Manager is inactive5 _6 z; X9 C& ^" D3 N% h
2200316 CONSTRAINT_MGR UI_FORMS Expanding 'Analysis Mode' form resets column width
! }% r6 X5 u, {2097479 PCB_LIBRARIAN CORE Symbol import in Part Developer does not show the correct pin shape.6 b. w. Q4 D, m# }% N8 n$ K+ Y
2145385 PCB_LIBRARIAN CORE Error-SPLBPD-972 reports missing parentheses in the ALT_SYMBOLS property of a part3 c5 y* _. Y9 j( z Z
2202622 PCB_LIBRARIAN CORE When adding a new pin to a symbol in Symbol Editor, the space between pins changes
2 k( E- U2 {0 Y1955570 PCB_LIBRARIAN FLOW Using the PACK_SHORT property with more than 256 characters does not work or report an error on packaging
6 H, s. O8 Q! l) a: g2072190 PCB_LIBRARIAN FLOW Allow PACK_SHORT property value longer than 255 characters& r% b" I+ d& l" N9 _* |# K+ S/ \
1720395 PCB_LIBRARIAN IMPORT_OTHER Converting OrCAD Capture OLB to Design Entry HDL library adds braces to pin number1 M- @6 U4 Q: I$ T
2141340 PCB_LIBRARIAN SETUP SPLBPD-216 Error logged in PDV even when MAX_SIZE Sheet is defined
5 {( Q0 `4 c( V9 |) |" F* v2214973 PCB_LIBRARIAN SETUP Unable to apply symbol property templates when PDV lock directives are set0 e( w3 p/ w! J
2257527 PCB_LIBRARIAN SETUP Locking PDV directives prevents applying symbol property templates' |; m7 s" t3 J3 q* A
2033898 PCB_LIBRARIAN SYMBOL_EDITOR Running Symbol Editor with no arguments results in a background process, not an error.' k) `8 o: _# t6 U) J& V/ d
2093849 PCB_LIBRARIAN SYMBOL_EDITOR Symbols and font sizes appear different when placed in designs
4 }: h" f4 Z" r) L* X2200399 PCB_LIBRARIAN SYMBOL_EDITOR Multiple issues observed when editing parts in the New Symbol Editor
( I. N( j& N. F2 Y t" K2218940 PCB_LIBRARIAN SYMBOL_EDITOR Duplicate pins cannot be removed2 b! u3 |' _) a" h1 Z
2230542 PCB_LIBRARIAN SYMBOL_EDITOR Bus pin location changes after expanding or collapsing pins in Symbol Editor+ ~% c: {8 g: _1 L. w6 l @
2239303 PCB_LIBRARIAN SYMBOL_EDITOR Expanding and collapsing a bus is changing the msb and lsb for the pin name
! p5 \* l/ }5 t F3 o; ]8 A2243431 PCB_LIBRARIAN SYMBOL_EDITOR Group of pins that are not adjacent cannot be moved together
. h' I' H& a" ]9 V# o9 o& v. V2029056 PCB_LIBRARIAN SYMBOL_EDITOR Unable to change Grid Settings in Part Developer
3 a) o9 Q' O% e! {2 o( p% x2149948 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor and System Capture moved pins from 0.01 grid to 0.05 grid.4 F6 f* q3 j9 Q3 ^4 V4 O7 z
2206975 Pspice MODELEDITOR PSpice Model Import Wizard symbol preview readability improvement requested2 }$ ^( J/ ?4 @" L( u5 j A
2211187 PSPICE MODELEDITOR Model Editor color scheme not readable
1 q% n- L' o3 q6 @1 s. K" v% a2214415 PSPICE MODELEDITOR Symbol view in Model Import Wizard has a visibility problem" q0 a6 X9 N8 W0 n7 {
2199570 PSPICE PROBE Unable to 'select sections' after Monte Carlo runs with Temperature2 h) F/ a$ o/ G; L! z3 s& X& ^- o3 K
2244140 PSPICE PROBE Not able to select multiple sections to plot in probe
- U/ ]1 O) q l. R1 V( I2249565 PSPICE PROBE Selecting multiple traces for PSpice A/D Monte Carlo run not working
1 A$ W# l& Q- ?5 ^ U% ]2171626 PULSE CORE Pulse crashed with error related to third-party development kit platform issue$ O/ |, b# Z" z. U
2221523 PULSE UNIFIED_SEARC Cannot log in to third-party search providers but can log in to Cadence Online Support
: K1 E% E v3 ]2019229 RF_PCB OTHER Layer conversion file data does not update GDSII layer mapping using Package Symbol Wizard
; ` {4 ]( G- w0 s8 f( {820288 SIP_LAYOUT COLOR Layer Priority command does not seem to be functioning
. R, \$ W2 a2 o- F9 L, t8 x820305 SIP_LAYOUT COLOR Layer Priority menus do not match the Color dialog in the package substrate tools$ P" z% }% V4 {
2256044 SIP_LAYOUT DATABASE Fix teardrop does not work for some situation: Deleting fixed fillets: A, {4 R% c v, W8 N4 H# H
2254932 SIP_LAYOUT DEGASSING APD Plus generating assertion failures when running degassing mode with script
* X- `5 O, @* l2 P) c: P l$ t2106314 SIP_LAYOUT INTERACTIVE Large design causing severe lag in Windows Server machine% Q: G S9 }$ Z' j- F0 O& E, N
2096239 SIP_LAYOUT STREAM_IF Database fails to create stream out file% i6 O1 `2 m- M$ B
2079071 SIP_LAYOUT SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die& k$ U$ g+ E% A m
2251630 SIP_LAYOUT WIREBOND 'Change Profile' does not change the diameter of the wire bond) I. ?+ g5 S1 q( E) [
2253633 SIP_LAYOUT WLP Advanced degassing passing illegal arguments to dba routine8 I! g9 v3 z9 H
2259630 SIP_LAYOUT WLP Advanced WLP: Import PVS DRC results in error1 y; d; T8 }/ }2 v
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though uppercase input is enabled
K/ [0 G0 v Y$ e9 c8 r2131976 SYSTEM_CAPTURE AUTOMATION syscap exits when run with the -tclfile argument and an invalid Tcl file
A# ^, i+ \/ a- E. k1983063 SYSTEM_CAPTURE BLKDIAGRAM_AU Auto Shapes are being shown as part of components$ z& J, P r8 k( @/ x$ Y# t0 _
1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
8 ]3 v, X: b8 u* }/ H2247567 SYSTEM_CAPTURE COMPONENT_BRO Symbol property placeholder changes not updated on the canvas
! j1 m( S5 d% \& I2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System Capture is not being updated when individual netlist files are written
4 @" v3 A+ A; q5 [1 X$ W1863460 SYSTEM_CAPTURE DARK_THEME thumbnail preview of pages is in light them but dragging the page the previes is dark
. Z6 L L! S4 P; k& r0 [' b# i2168622 SYSTEM_CAPTURE EDIT_SEARCHRE Reports from Find Results are dumped even when the operation is canceled2 y2 B* @% s8 w% |$ c+ G
2168625 SYSTEM_CAPTURE EDIT_SEARCHRE Sort icons for columns in 'Find Results' are incorrectly placed: appear to be in adjacent column2 w! T6 S; v- p; {: j! _
1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture incorrectly reports unsaved changes when closing after running export physical
; M A9 Q% q. U9 y1931660 SYSTEM_CAPTURE EXPORT_PCB SDA is non-responsive while Allegro launches and opens a board when launched from SDA$ T2 U; B$ ]3 s2 w# {
2087387 SYSTEM_CAPTURE EXPORT_PCB System Capture: After Export PCB completes, busy cursor shown for a while
$ h1 M0 N. e d' q2 v6 ]2 v2202179 SYSTEM_CAPTURE FIND_REPLACE Replacing a net name with the same name by using Find and Replace results in a crash
" B) w. b/ _( A1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
/ u7 a ]2 U1 S1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page+ A6 H$ E; R) a! F
2231399 SYSTEM_CAPTURE IMPORT_BLOCK 'importBlock' Tcl command not working when using a script
3 D* Z/ A, X4 `9 g5 D! C3 A1907729 SYSTEM_CAPTURE IMPORT_DEHDL_ Import DE-HDL sheets - differential pair properties on nets are lost4 N) u# D9 ~) L+ T, S
2025949 SYSTEM_CAPTURE IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not translate in System Capture
( _, s7 D3 d/ t& l1942542 SYSTEM_CAPTURE IMPORT_PCB System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks% d2 Y9 p% [+ Z: W* w& \
1982320 SYSTEM_CAPTURE IMPORT_PCB View files are not created in the schematic-to-board flow% `) P! _! G" Q1 e; j
2117532 SYSTEM_CAPTURE MENUS_AND_TOO Ability to customize menus for a site: T* \( R0 T/ m* O6 w3 n
2213478 SYSTEM_CAPTURE MENUS_AND_TOO Help - About menu item appears twice8 X4 t. F6 r( K8 u8 S
1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlist and BOM! g) B! q- ~4 `) x5 V" s# ?& k# g
1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
5 C! q9 o: o7 c& e6 V% V: ]2189846 SYSTEM_CAPTURE MISCELLANEOUS Inconsistent display of same font
( g- u+ z5 m- ]( P9 Z' f2 N: O3 K) B5 B2178961 SYSTEM_CAPTURE NOTES Cannot add Japanese text in notes in release 17.4-2019 on Windows 10
- r& N/ _1 A) |( w2 y; M ^ ~" x1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture1 Z/ I9 y: Y n" x- p
2079857 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture: Unable to select design to open if license selection box is canceled the first time
S6 g/ t' b1 F% p" T3 \2065025 SYSTEM_CAPTURE PACKAGER Export to PCB Layout reports wrong path but exports correctly+ \; t, E9 [- S2 o! d0 d) f3 L
2229611 SYSTEM_CAPTURE PACKAGER Path for the 'packaged' folder shown in the 'Export Physical' is incorrect" O# ^' q: n2 E" G
1993146 SYSTEM_CAPTURE PROJECT_EXPLO Cannot move page up by only one position7 i. r) y% O) t6 k
1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts are missing reference designators and some have two properties - RefDes and REFDES/ J" F% d+ ?: b7 Z
2201060 SYSTEM_CAPTURE PROPERTY_EDIT Some of the icons in the Properties window do not have tooltips- \) H& @9 n- I- k# y e& Q
2246667 SYSTEM_CAPTURE SCRIPTING Running the 'replay.tcl' script gives an invalid command name error
0 z9 t, j& w- i+ d- y$ V2010032 SYSTEM_CAPTURE SHORTCUTS Cannot enter Page-Up/Page-Down as shortcuts
* o" }9 `2 [2 J# E- a2017985 SYSTEM_CAPTURE TDO Allegro System Capture ability for multiple users to open a design5 ^9 f l* ]6 J* e7 O& p! Z6 b6 _
2106743 SYSTEM_CAPTURE TDO Ability for multi-user access to the same schematic& ]( B6 C2 T2 O$ B0 U
2209628 SYSTEM_CAPTURE UI Tooltips for Design Rule Checks are getting truncated
7 T% T8 d' P+ d$ ?) J1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
: q9 g( u/ c j0 }1 Y8 |2032005 SYSTEM_CAPTURE VARIANT_MANAG Custom variables not saved for variants
5 u3 V* b) n# G% _" J" X/ p6 A1 b2228299 SYSTEM_CAPTURE VARIANT_MANAG CAP parts should not show up in the Preferred Parts list when changing a RES9 f% z4 ^- D' ~ V
1627835 SYSTEM_CAPTURE WIRING Inconsistencies in wire movements) n7 E0 I1 n# O8 R: h0 C7 ]" n
1670888 SYSTEM_CAPTURE WIRING Rotation error when a component is connected to a power symbol
* ^6 W, f5 {; T, B1721863 SYSTEM_CAPTURE WIRING Net names move to random locations when components are moved around the canvas.! t7 G9 _+ E9 ^; J4 h5 }. q
1960130 SYSTEM_CAPTURE WIRING Disconnected nets when using the mirror option( g; [. Q1 k& ?9 y" m1 |! g9 E
1961274 SYSTEM_CAPTURE WIRING XNet removed during pin swapping3 `% |* r1 U4 h/ s% M* m
1968463 SYSTEM_CAPTURE WIRING System Capture should not allow illegal characters to be entered for net names! p0 V$ L: `, W
1973426 SYSTEM_CAPTURE WIRING Selecting multiple net names and trying to delete only deletes one net name.
( J; [& T* _2 p7 U$ Y+ A1978381 SYSTEM_CAPTURE WIRING 'oops' does not remove the first vertex placed+ d1 Z5 [" X3 B. s$ P& b3 Q
1985029 SYSTEM_CAPTURE WIRING Net aliases are not dragged with circuit, they appear to move after the circuit is dropped
0 Z0 m+ d9 m E# x$ F2013647 SYSTEM_CAPTURE WIRING Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections
- K9 O, e* }3 A4 ]) h2014188 SYSTEM_CAPTURE WIRING Context menu not working in Variant mode& I: z* t# E5 h) y1 m4 \3 A, t
2041879 SYSTEM_CAPTURE WIRING XNets generated for nets with pull-up resistors3 l" v2 X+ G+ e) g
2050533 SYSTEM_CAPTURE WIRING Need an option to increase junction dot size$ {2 X0 H7 B4 h4 D- W( J
2061877 SYSTEM_CAPTURE WIRING Unable to add a power symbol with the Place - Special Symbol menu1 L0 o1 U% ^, R( Z. F5 R
2079409 SYSTEM_CAPTURE WIRING Increase the size of the wire connection dot in System Capture: D( Q, r% V, o" Q) y/ {
2081884 SYSTEM_CAPTURE WIRING Symbols take a long time to move, and results in DRCs and broken connections
+ A+ w: j) J* M! b9 H$ }4 E2085263 SYSTEM_CAPTURE WIRING System Capture: Focus lost from the Format tab if font name starting with typed letter is not present: R5 O6 |# F4 u3 M) A( a* E$ l
2089569 SYSTEM_CAPTURE WIRING Ability to specify the solder dot radius size; N% g' O' l, G3 y+ ]1 U
N1 a: ]& L8 y4 f8 LQIR1详细特性说明：
Hotfix_SPB17.40.007_README-Release_Notes.pdf
(2.51 MB, 下载次数: 55)
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待我上传完后附上链接，这次QIR1比较大，4.59 GB
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