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本帖最后由 金志峰 于 2020-6-8 03:33 编辑 ; I! S3 t% B+ t# W( ]
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cadence orcad and allegro 17.4-2019 QIR1新特性
% V4 k% {! x2 a& \/ X/ w W·焕然一新的图标及UI
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6 d' t6 k9 ~% v* _QIR1中全新启动界面 （点击图片放大）
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$ M3 w! z! F0 x$ ^QIR1中全新启动界面（点击图片放大）
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QIR1中capture官方Dark主题（点击图片放大）(QIR1中UI界面中所有图标也全部更换全新并统一了)
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, i+ I0 ]7 }) o- bQIR1中capture官方Light主题（点击图片放大）
% W) [1 ~3 k) Q# O(QIR1中UI界面中所有图标也全部更换全新并统一了)
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$ _/ j0 [* Q o( iQIR1中PCB Editor新增官方Dark主题（点击图片放大）
/ p7 R( U2 s+ d/ n(QIR1中UI界面中所有图标也全部更换全新并统一了)
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QIR1中PCB Editor官方Light主题（点击图片放大）8 z0 a3 \6 E( l5 u% V
(QIR1中UI界面中所有图标也全部更换全新并统一了)+ a2 N# g* l9 c$ g4 N. ^. ?) q
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Fixed CCRs: SPB 17.4 HF007; Q+ A. X2 l- Y) M' W4 i) J. y: i2 m
05-21-2020
7 `* P d' Y1 ~4 T; F========================================================================================================================================================4 s4 y- b1 I1 o1 _& i
CCRID Product ProductLevel2 Title# J, M1 m: I( O0 `1 l% U. B. S
========================================================================================================================================================
3 `5 t8 W6 }) @& w2247686 ADW CORE Allegro EDM: Unable to create a project using a newly created flow0 K6 L8 B$ p; N0 q/ E \1 G& p! |3 [& z y
2137594 ADW DBADMIN EDM is not allowing changes to STEP models' U" D& p2 |, l, h1 Z
2135452 ADW DBEDITOR DBEditor poor peRFormance in high-latency networks
! S. C3 m$ ?+ e2113265 ADW LIBDISTRIBUTI Various database operations take a long time; rebooting server seems to fix the problem
0 [4 I8 | ~+ M( A. z+ ~4 Y3 w2122941 ADW LIBDISTRIBUTI Lib_dist execution taking a long time to run; Capture CIS DBC file appears to be taking the most time
2 g ]# d9 \5 Q- W+ {2 d2127319 ADW LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250)
0 i' X. U+ U j8 O8 g8 D9 F6 B1975317 ADW PART_BROWSER Space at the end of the line in CDS.LIB results in zero libraries being shown in System Capture library search+ x. w7 Q* p7 z) U4 C6 y
2078057 ADW PART_BROWSER Symbol Graphics preview is not available in Designer Servers
% w# `6 @+ b3 S, F2 b2092863 ADW PART_BROWSER System Capture library search is not displaying the symbol and footprint preview
! i% H# ^2 {9 i6 f2086463 ADW PART_MANAGER System Capture cannot add components when accessing remote machine via Citrix+ D. w- q, ?6 w, J
2092868 ADW PART_MANAGER Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not flow from pstchip
5 s a/ S2 K( _7 f2 ]2092872 ADW PART_MANAGER System Capture stops responding when importing from DE-HDL
" V. M3 P* n/ } ~( A2113226 ADW PART_MANAGER System Capture stops responding while importing DE-HDL sheets" L- v# g3 C2 |1 h
2212406 ADW PART_MANAGER Allegro System Capture: Part Manager is deleting properties from all instances upon Update. C) B# I! W" j; |
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name7 J* s: Z9 V$ t# C
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to Team Design4 K0 R- O/ K8 O. M; D
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
; P" `$ x/ f. w2 H2048086 ALLEGRO_EDITOR 3D_CANVAS Wire bonds are not linked to die pad when component is embedded body down
- v3 p7 e2 v& t) l3 d0 Z4 {2051277 ALLEGRO_EDITOR 3D_CANVAS Vias are offset from board in Z direction in 3D Canvas- f7 D. {% N0 a8 r2 c
2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas4 J8 V" \- z1 C2 d4 ]8 z, Q0 J
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
8 r0 h. J) ^- {# h- [6 G- Y) }/ [2079732 ALLEGRO_EDITOR 3D_CANVAS Enhance 3D Canvas to merge the lines segment and overlapping lines and shapes% o! }; A5 y! U/ g
2206045 ALLEGRO_EDITOR ARTWORK Artwork Control Form fails to create film if Film record has a period (.) in the title0 Q2 [. x' o- e- B! z
2209200 ALLEGRO_EDITOR ARTWORK PCB Editor stops responding on rebuilding apertures without rotation
. M' O* c8 @6 j8 w0 v* g0 u1 @* ?2244407 ALLEGRO_EDITOR ARTWORK Automatic editing apertures with rotation takes time in the General Parameters tab of Artwork Control Form
& U x( p: k) q- Q, k, ^2267942 ALLEGRO_EDITOR ARTWORK Allegro PCB Editor stops responding when generating apertures in HotFix 0063 |! z1 g3 M# o
567342 ALLEGRO_EDITOR COLOR Add option under View menu for 'load color view'9 }7 g0 X7 Y6 y7 o) X# I
637828 ALLEGRO_EDITOR COLOR Line highlights in 'shape select' command
. u* G4 S/ ]" ?7 D6 p* j720274 ALLEGRO_EDITOR COLOR Add menu option for the 'colorview load' command, X. e% Z* I! i/ _9 @
1602652 ALLEGRO_EDITOR COLOR Color/Visibility behavior variation using "Enable Layer Select Mode"4 b+ v" x \( L! `) a
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set8 w# @" P* O0 J, Z' v
2207580 ALLEGRO_EDITOR COLOR Component color is inconsistent when display_nocolor_dynamics is set./ ~4 d& z |- P( g; g
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow4 G$ ^, o" h. l4 b+ P
2250988 ALLEGRO_EDITOR DATABASE Inner Layer keep out as illegal subclasses: Shape object may not exist on layer ROUTE KEEPOUT/INNER_SIGNAL_LAYERS
e8 p* w& q' m$ p: N P2096958 ALLEGRO_EDITOR DFA Cannot launch Constraint Manager after assigning CSet and closing
" o! Q" V; Y5 G5 |! e2049681 ALLEGRO_EDITOR DFM DFF check for plating in via should not flag DRC for surface mount testpoint Via' B7 U& O: J: R7 i
2155060 ALLEGRO_EDITOR DFM Inconsistent behavior in displaying DRCs for Via to Via spacing3 T' |8 N# a! u- k6 h: }1 V
2166431 ALLEGRO_EDITOR DFM DesignTrue annular ring thru pin pad to mask checks compared to smd pin to mask checks are inconsistent in behavior9 n" k$ a0 W8 e% S% B4 \
2221975 ALLEGRO_EDITOR DFM DFM missing mask check reporting mask is missing when pins have a mask geometry overlaying them.
1 I3 `" S$ Q6 C+ I8 A2249498 ALLEGRO_EDITOR DRAFTING When a Symbol with a Dimension is placed on the board, an extra Dimension is added to the Symbol origin., K* P @- U1 I/ P4 Y. H5 U& X
2250631 ALLEGRO_EDITOR DRC_CONSTR Cannot import netlist into design due to illegal DRC element: no DBDoctor error
2 d" b* b$ r( b( Q! w" i1794593 ALLEGRO_EDITOR EDIT_ETCH Unable to deselect return path vias selected when creating High-speed via structures
2 y5 ]; W6 a' |1 p8 o1 ~2099538 ALLEGRO_EDITOR EDIT_ETCH Gloss - Via Eliminate shifts traces to another layer
$ i% W/ F, r; U, b( K# v2204339 ALLEGRO_EDITOR EDIT_ETCH Differential pair line lost during slide operation
* ~/ Y3 a- j2 @ [9 z: P% X2208938 ALLEGRO_EDITOR EDIT_ETCH Slide operation makes one of the differential pair cline invisible. n. U' D' l' F% ]2 p: C
2222047 ALLEGRO_EDITOR EDIT_ETCH One of the traces disappear when sliding a differential pair in single trace mode, Z' d% O- E( G, p0 e
2233991 ALLEGRO_EDITOR EDIT_ETCH One cline of a differential pair disappears temporarily upon sliding the Differential Pair in Single Trace Mode
. R% Q1 l2 A* n% C. ]* P2240827 ALLEGRO_EDITOR EDIT_ETCH Cline of a Differential pair net disappears after sliding the other net of the Differential pair" `; D* L$ W* C' D6 C% ` g
2245775 ALLEGRO_EDITOR EDIT_ETCH Differential pair slide in single trace mode removes other trace& N7 _8 e: ~$ L$ P
1813358 ALLEGRO_EDITOR GRAPHICS Allegro PCB Editor enables shape boundary when disabling etch layer in Visibility pane
+ J2 W% G6 I5 \% ]( g1911613 ALLEGRO_EDITOR GRAPHICS The subclass for boundary class stays on, even if Subclass for Etch Class is turned off from Visibility tab( s4 Y& n; _1 O5 n f
1966343 ALLEGRO_EDITOR GRAPHICS Shape boundary remains enabled even after turning off the etch layer visibility
* x+ A c; n( p1 H% ]2195276 ALLEGRO_EDITOR GRAPHICS Selecting File view is slow1 M5 [7 z/ B! t1 T, U* m
2031883 ALLEGRO_EDITOR INTERACTIV Sub-Drawing: Clipboard origin point is not set correctly& A! |# j, x' m7 ]$ B
2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Shape ANDNOT operation5 K& f9 c" Y2 e+ d! ^
2069247 ALLEGRO_EDITOR INTERACTIV DFA bubble on wrong layer after mirroring the part
/ e6 E; ]* Y) p" C q2 p! l1 q: R2103711 ALLEGRO_EDITOR INTERACTIV Placement edit mode popup 'Rotate' leaves ghost image in the background
8 ~+ Y3 P8 `+ Q* p6 C, T& {- b2136859 ALLEGRO_EDITOR INTERACTIV DFA Problem if we mirror component while placing
, B- { G% B* Y/ e: G3 v2165027 ALLEGRO_EDITOR INTERACTIV Different behavior in OrCAD Capture when using crossprobe to select Power nets
& i) h3 ^) ^1 {2 L7 u2240235 ALLEGRO_EDITOR INTERACTIV The design file name changes automatically to board template name while creating new board (wizard).1 w0 i; B( \8 z, a
2244765 ALLEGRO_EDITOR INTERACTIV License 4150+226 does not have AiDT/AiPT in release 17.2-2016' X1 I6 b( g4 x2 \+ f& z
2259800 ALLEGRO_EDITOR INTERACTIV DFA DRC circle not shown on the layer of placement in Placement App Mode$ }! y) W! T7 o" l1 q
2120420 ALLEGRO_EDITOR INTERFACES Drill figures missing in the exported PDF if drill legend deleted
& ~6 ]( X" T/ F* X* q2136454 ALLEGRO_EDITOR INTERFACES Export - PDF output is not correct& u- P( ], l1 J0 G% J
2116748 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets% a! A9 o M g# m0 i
2138977 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to 17.2-2016, HotFix 0574 S3 b) g! n" ~/ f$ c3 b
2247167 ALLEGRO_EDITOR IN_DESIGN_ANA IDA Impedance Analysis: Add an option to export CSV automatically, v; V/ U# {/ t) [/ Y& _3 M4 O
2222638 ALLEGRO_EDITOR IPC Documentation Editor crashes with error: Failed to complete the job because of unspecified error
9 G7 ]% X" G' n$ R: n0 g& [2106425 ALLEGRO_EDITOR NC Disable undersize regular pad and oversize soldermask pad for start layers in Backdrill Setup and Analysis6 s2 `, L' a! W9 r. V
2091932 ALLEGRO_EDITOR OTHER Unsupported Prototypes command missing for the OrCAD licenses
- [2 E9 y9 ~3 e, M: M) f) d2221345 ALLEGRO_EDITOR OTHER Speed up Allegro PCB Editor startup by removing check for defunct PCB/Package co-design capability (NG_450)" N/ i" \; s! m* Z) _. ~1 P0 u
2257934 ALLEGRO_EDITOR PLACEMENT Error (SPMHGE-626) on place component: Symbol not valid on any layer7 Z7 I' O9 J) U0 ?5 U6 G
1001000 ALLEGRO_EDITOR PLOTTING File - Plot in PCB Editor does not plot more than one copy7 G, s. _# E9 L4 P
2234538 ALLEGRO_EDITOR REPORTS Allow Unused Blind/Buried Via report to run as Batch Process through the reports batch command
: U+ E9 O1 H/ A! B2222738 ALLEGRO_EDITOR SCHEM_FTB Netrev not completing, showing error for electrical constraints data (pstcmdb.dat) import
5 |0 f. V. k4 \' n6 o& u2 Y2255426 ALLEGRO_EDITOR SCHEM_FTB Netrev is running for hours without closing/ W+ {2 D' x0 j9 e
1702190 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script file: Some sub-classes not created and error for form field label/ d: z" ]8 k! @
1791099 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor does not terminate when the script is run with '-nographic'1 n% F6 N& Z& O$ g2 D$ w/ g4 s
1791267 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script does not run with '-nograph' in release 17.2-2016" c6 K, O2 `1 |6 y! V# A+ f( Y
1892520 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with '-nographic'
+ `# V i. T8 t- _5 D+ `) W3 h5 P1962010 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with -nongraph option1 c" u8 y( a6 b9 ^1 b- s/ T4 s
2056857 ALLEGRO_EDITOR SHAPE Shape boundary error by shape parameter
* {; U P e+ z2 u9 j$ T2081946 ALLEGRO_EDITOR SHAPE Shape Update takes twice the time in release 17.2-2016, HotFix 053 as compared to HotFix 047
# v- G' b" `' X1 e" _; x2104559 ALLEGRO_EDITOR SHAPE PCB Editor crashes while performing shape operation 'andnot'4 r1 q: @" t0 ~/ U
2108207 ALLEGRO_EDITOR SHAPE No Void Overlap option is not working in Auto Metal Balancing (AMB)- d- e0 T) _% [1 {: k3 _( O
2240996 ALLEGRO_EDITOR SHAPE Detecting Shape Island: Ignored for copied or moved shape
% j# @* S- s7 e+ `2258758 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes when routing two signals together
6 B: q' `1 d a& W, q2 x8 r717389 ALLEGRO_EDITOR skill Ability to set and return the application mode using SKILL& R/ a8 Z! v3 D$ ~
853160 ALLEGRO_EDITOR SKILL Need ability to get and set application modes using SKILL
7 w+ `4 t2 f- i981446 ALLEGRO_EDITOR SKILL Request the ability to get and set application modes using SKILL* ~& [' d8 d" H$ Z* O
1235409 ALLEGRO_EDITOR SKILL SKILL option to get application mode
) _1 _! M* `& U2 F4 q( }( ~, E1316962 ALLEGRO_EDITOR SKILL SKILL option to switch between application modes
6 W1 m* I! M0 d, ~1553621 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function; ^# j; X. g: `( W# a2 b* K
1885442 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function.
' E! z- U/ d+ V2 u2080351 ALLEGRO_EDITOR SKILL SKILL to determine current application mode
$ l0 l' c' i: q# u* W& a2195645 ALLEGRO_EDITOR THIEVING Thieving pad cannot be added on some areas in the board in latest hotfix but could be added earlier
6 Z6 |$ w1 J3 g1721594 ALLEGRO_EDITOR UI_FORMS STEP name Filter for STEP Package mapping form should be case insensitive
0 }' ?5 N0 ^* @7 Y9 }3 y2 E n2090604 ALLEGRO_EDITOR UI_FORMS Undo/Redo UI grayed out when invoking Color192& H/ I; c6 }; h. M
2203278 ALLEGRO_EDITOR UI_FORMS 'Width' keyword in Place Rectangle field is grayed out when Place Rectangle is selected
# h; y" J+ g0 E0 o: k0 f2209172 ALLEGRO_EDITOR UI_FORMS Labels truncated by drop-down lists in Options ('Manufacture' - 'Drafting' - 'Relative Copy')
$ N; a! m: s3 c" A9 ?2239426 ALLEGRO_EDITOR UI_FORMS Cannot start text size with decimal in 'Design Parameter Editor' - 'Text' for English (Denmark) regional settings
- \/ f! {& v9 ^% o2 U; T1 X2245035 ALLEGRO_EDITOR UI_FORMS The right edge of the default Define Grid form looks cut off in 17.4.* _, F$ r5 N! Y- E' L) w2 `- u
2245955 ALLEGRO_EDITOR UI_FORMS Resizing of 'Reject Item Selection' window not possible in release 17.4-2019, HotFix 004# j; L* e' H; T/ K
2249202 ALLEGRO_EDITOR UI_FORMS Extra click required to activate Pass field in Autorouter form
" s; }; y" ^- M0 H8 V2259605 ALLEGRO_EDITOR UI_FORMS Add ability to resize Reject pop-up6 x7 }! B R; y; {: x% ]
2090517 ALLEGRO_EDITOR UI_GENERAL Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane
0 I) x" \% E% o3 l) V; c9 E2092436 ALLEGRO_EDITOR UI_GENERAL RefDes length of input string for Modify Design padstack is limited to 20 characters/ p6 W$ j4 o) K/ ]4 D+ V
2134781 ALLEGRO_EDITOR UI_GENERAL The Pin Class is missing in Options tab when creating or opening a Mechanical Symbol
/ G. @( d: ^& j _# o! e& G2168026 ALLEGRO_EDITOR UI_GENERAL Edit Properties UI slow to launch for boards with many drawing properties8 J1 N) E; D( Z2 c2 y
2191267 ALLEGRO_EDITOR UI_GENERAL Changing Visibility of any object type disables links in Layer Select Mode in the Visibility pane4 Q3 Q7 w4 P! }
2208018 ALLEGRO_EDITOR UI_GENERAL Text on BGA pins not visible in release 17.4-2019 if not zoomed to maximum
$ e) v, C" k/ I, [$ {( O% T2225753 ALLEGRO_EDITOR UI_GENERAL dark theme does not respect TRBICON size for 4K monitors3 H/ a, B( \7 h
2256841 ALLEGRO_EDITOR UI_GENERAL Enlarge the Shape Copy to Layers form as the window is quite small and not resizable
H3 u! E+ ]+ d( y0 e2258019 ALLEGRO_EDITOR UI_GENERAL Canvas turns white after closing STEP Package Mapping window6 N! C3 R) c' v0 B- |$ ^
2258167 ALLEGRO_EDITOR UI_GENERAL Enhance 'Shape copy to layers' window in release 17.4-2019 to expand or resize8 z/ ^5 [+ ~# t3 x ?* q
2262305 ALLEGRO_EDITOR UI_GENERAL Assign Differential Pair form list box size too small to add signals
' h9 w: L4 W2 C8 s& m$ w8 \ E2086574 APD OTHER APD is showing duplicate layer text on the vias2 [/ w6 U1 u6 h) l
1723825 APD SCRIPTS Allegro Package Designer in release 17.2 is not writing out to either jrl files or script files in real time.
$ d0 |1 R1 b- c; ~1 l8 i! H) O2186363 APD UI_GENERAL Text on the Pin is not visible until zoomed in to certain extent7 j3 P7 R6 V5 I8 k3 q0 F
2253484 APD WIREBOND APD stops responding when running 'wirebond soldermask create' with 'Measure from soldermask pad'/ [# s% h+ t' z6 [
2241725 CAPTURE DRC Waive DRC option not working from batch DRC window
" @: Y8 C1 v- |, Q: ?9 I5 @2243645 CAPTURE DRC Online DRC bug in release 17.4-2019, hotfix 004 - offpage connector does not have wire
8 i3 V+ `8 D; G+ e9 B# |2250867 CAPTURE DRC Hanging wire custom DRC not working when selected standalone
3 u4 ]2 P. @$ M0 o! _2252912 CAPTURE DRC Unable to create new DRC file using Browse button in DRC window
. T7 d% g. v- E2 G0 | T, m1 N2047391 CAPTURE PART_EDITOR Pin type cannot be changed in release 17.2-2016, hotfix 051
1 y7 |; J- k( }0 j: i( c2183187 CAPTURE SCHEMATIC_EDI OrCAD Capture: Ctrl + N seems to call a legacy dialog that allows projects to be created with no name
* f" U% k2 u; i9 v6 e1 J2190602 CAPTURE SCHEMATIC_EDI Cascading options of Window menu not working in OrCAD Capture in release 17.4-2019
4 V2 o" ]2 ~( l2 w2194374 CAPTURE UX Design Sync issues: Session log does not report information about errors- M% `/ g" b- o% Y' G
2183037 CIS LINK_DATABASE CTRL-L shortcut for Link DB-Parts for Query in CIS-Explorer not working
. \' P5 l* _! e2201323 CIS PLACE_DATABAS Capture CIS displays empty dialog on placing part from database in release 17.4-2019% \: |) c. @& b8 ^' _
2216963 CIS PLACE_DATABAS Light Theme: Warning text not visible in Capture CIS dialog7 v, |7 q) d3 w; t2 x" j
2246354 CIS PLACE_DATABAS Warning (ORCIS-6159) pop-up window is blank.) G7 Q3 E1 k3 r# n/ R- x
2230651 concept_HDL CHECKPLUS Discrepancy in the 'checkplus' marker files, j4 ~% T$ @, R: A( U
2237145 CONCEPT_HDL CONSTRAINT_MG T-Points match groups get deleted after saving a design
K+ W3 R1 w& k, Z2246452 CONCEPT_HDL CORE Page information gets removed from 'master.tag' of the top-level design when subdesigns are read-only1 Q5 \8 y; @2 M8 q1 i8 y2 b
2057490 CONSTRAINT_MGR CONCEPT_HDL Constraint Manager Worksheet flips after running hier_write when CM is open5 n+ p* D" @6 q$ p# U3 n* z
2236329 CONSTRAINT_MGR CONCEPT_HDL Pin Pairs not added to Match Group
, s. c( g Y# [# s7 y2214367 CONSTRAINT_MGR INTERACTIV CSet assignment matrix sorting in Net Class-class random in Capture to Constraint Manager flow
" a7 g0 x* X$ Q6 [2 y2243574 CONSTRAINT_MGR OTHER CM SKILL cmxlPutAttribute() cannot set constraint value" v8 L; F9 B8 I" ?5 X
2259598 CONSTRAINT_MGR OTHER Importing netlist: Error for electrical constraint data (pstcmdb.dat) import4 j! \% S- |; e! S1 Q
2207862 CONSTRAINT_MGR SYSCAP Save icon and 'File' - 'Save' menu in Constraint Manager is inactive: t* ~9 T3 [) T: Y! F" k
2200316 CONSTRAINT_MGR UI_FORMS Expanding 'Analysis Mode' form resets column width4 T4 s& H- [9 e! H/ q" c( x
2097479 PCB_LIBRARIAN CORE Symbol import in Part Developer does not show the correct pin shape.1 f8 C% X" l, w7 t0 Q3 V3 r
2145385 PCB_LIBRARIAN CORE Error-SPLBPD-972 reports missing parentheses in the ALT_SYMBOLS property of a part
2 p! k. y, b8 l, j- g7 K2202622 PCB_LIBRARIAN CORE When adding a new pin to a symbol in Symbol Editor, the space between pins changes+ a2 i. ]6 O% z4 @( X, b4 X+ P
1955570 PCB_LIBRARIAN FLOW Using the PACK_SHORT property with more than 256 characters does not work or report an error on packaging
- `( ?# E1 m8 }6 n7 _2072190 PCB_LIBRARIAN FLOW Allow PACK_SHORT property value longer than 255 characters
2 I; A9 y8 F& F0 e$ U, R1720395 PCB_LIBRARIAN IMPORT_OTHER Converting OrCAD Capture OLB to Design Entry HDL library adds braces to pin number
8 b' L, g f5 e3 ~2 q2141340 PCB_LIBRARIAN SETUP SPLBPD-216 Error logged in PDV even when MAX_SIZE Sheet is defined
0 H0 o: c3 g5 U' n( g+ D2214973 PCB_LIBRARIAN SETUP Unable to apply symbol property templates when PDV lock directives are set# c7 Q7 `% C- r, h3 A4 t1 W2 D! |6 @
2257527 PCB_LIBRARIAN SETUP Locking PDV directives prevents applying symbol property templates' Q1 {0 j# P7 M% C; I* l
2033898 PCB_LIBRARIAN SYMBOL_EDITOR Running Symbol Editor with no arguments results in a background process, not an error.% k c' t, Y' L; b! T, C
2093849 PCB_LIBRARIAN SYMBOL_EDITOR Symbols and font sizes appear different when placed in designs, ?- P' m" A0 T
2200399 PCB_LIBRARIAN SYMBOL_EDITOR Multiple issues observed when editing parts in the New Symbol Editor
. u& i5 f8 b% k! u6 [; a2218940 PCB_LIBRARIAN SYMBOL_EDITOR Duplicate pins cannot be removed
9 S, @5 ?# [) X2230542 PCB_LIBRARIAN SYMBOL_EDITOR Bus pin location changes after expanding or collapsing pins in Symbol Editor
; m: K9 I2 W7 C# a7 V: s) E- c% T2239303 PCB_LIBRARIAN SYMBOL_EDITOR Expanding and collapsing a bus is changing the msb and lsb for the pin name' d' G' z# x! X! Y, B
2243431 PCB_LIBRARIAN SYMBOL_EDITOR Group of pins that are not adjacent cannot be moved together) w9 O5 [( v: H( I
2029056 PCB_LIBRARIAN SYMBOL_EDITOR Unable to change Grid Settings in Part Developer: P, ~$ G) M1 P v% L* m
2149948 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor and System Capture moved pins from 0.01 grid to 0.05 grid.5 t. I3 w5 i" H2 m4 j; R1 E
2206975 Pspice MODELEDITOR PSpice Model Import Wizard symbol preview readability improvement requested
' X' s6 _8 @( _2211187 PSPICE MODELEDITOR Model Editor color scheme not readable
% F. Q& q! f9 u: a1 f1 @7 P0 _2214415 PSPICE MODELEDITOR Symbol view in Model Import Wizard has a visibility problem% _( i0 H$ b6 q, N) [6 m
2199570 PSPICE PROBE Unable to 'select sections' after Monte Carlo runs with Temperature
: L; k9 w1 B1 ]6 t" E2244140 PSPICE PROBE Not able to select multiple sections to plot in probe) s1 ]8 F# H( N4 ]( h t
2249565 PSPICE PROBE Selecting multiple traces for PSpice A/D Monte Carlo run not working
4 B# Z% W% `+ j/ K. ^2171626 PULSE CORE Pulse crashed with error related to third-party development kit platform issue+ H2 e" g. n7 Q( T4 D
2221523 PULSE UNIFIED_SEARC Cannot log in to third-party search providers but can log in to Cadence Online Support
; |; j! B% J3 @7 N" K2019229 RF_PCB OTHER Layer conversion file data does not update GDSII layer mapping using Package Symbol Wizard. G! U- i9 w) ~9 z- b- K0 F9 ^" c
820288 SIP_LAYOUT COLOR Layer Priority command does not seem to be functioning' A e5 m% X4 ~/ I0 s# P8 K
820305 SIP_LAYOUT COLOR Layer Priority menus do not match the Color dialog in the package substrate tools; L6 j/ g# t; v
2256044 SIP_LAYOUT DATABASE Fix teardrop does not work for some situation: Deleting fixed fillets
) n1 T; n) {* K! ]8 I5 t% o9 j2254932 SIP_LAYOUT DEGASSING APD Plus generating assertion failures when running degassing mode with script. r: @' h9 m; v y- C$ K; w
2106314 SIP_LAYOUT INTERACTIVE Large design causing severe lag in Windows Server machine1 }) j% J1 W7 t! Y
2096239 SIP_LAYOUT STREAM_IF Database fails to create stream out file
1 ~+ f4 I5 {' |$ O6 \2079071 SIP_LAYOUT SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die
7 `) s9 E! ]' r# o0 B2 M- t3 x2251630 SIP_LAYOUT WIREBOND 'Change Profile' does not change the diameter of the wire bond
6 Q7 R2 s4 Y( z' y7 y" l2253633 SIP_LAYOUT WLP Advanced degassing passing illegal arguments to dba routine( a |1 n4 x5 J" E* p: z% w
2259630 SIP_LAYOUT WLP Advanced WLP: Import PVS DRC results in error
7 e" s1 l0 `7 v. P; L& K( i* @1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though uppercase input is enabled) u( _/ ?( J* i: p! o* K
2131976 SYSTEM_CAPTURE AUTOMATION syscap exits when run with the -tclfile argument and an invalid Tcl file
; s) }% @3 Y& _; f0 p8 \0 O- y1983063 SYSTEM_CAPTURE BLKDIAGRAM_AU Auto Shapes are being shown as part of components
) N# e7 O8 y8 h4 j: f1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name$ O6 X A% d; k- W/ e
2247567 SYSTEM_CAPTURE COMPONENT_BRO Symbol property placeholder changes not updated on the canvas* {; R0 G' [8 |! ] Q4 G
2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System Capture is not being updated when individual netlist files are written) t! L7 e( N7 J' Z9 T6 V* M
1863460 SYSTEM_CAPTURE DARK_THEME thumbnail preview of pages is in light them but dragging the page the previes is dark
* I* h' h' U* N! ^0 V ]% u2168622 SYSTEM_CAPTURE EDIT_SEARCHRE Reports from Find Results are dumped even when the operation is canceled
5 L7 q) f. J4 ?& t" s, w2168625 SYSTEM_CAPTURE EDIT_SEARCHRE Sort icons for columns in 'Find Results' are incorrectly placed: appear to be in adjacent column& o1 e1 Z! A6 ` j' y1 o. h) O' O# f
1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture incorrectly reports unsaved changes when closing after running export physical
4 t/ q' U7 U+ |/ h( @: ]1931660 SYSTEM_CAPTURE EXPORT_PCB SDA is non-responsive while Allegro launches and opens a board when launched from SDA) z- x" N: N+ P2 X& m- C
2087387 SYSTEM_CAPTURE EXPORT_PCB System Capture: After Export PCB completes, busy cursor shown for a while- Y7 {/ R6 P* n' E& G8 G
2202179 SYSTEM_CAPTURE FIND_REPLACE Replacing a net name with the same name by using Find and Replace results in a crash, ?. d& n- U) w- w2 a( c
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
7 {: o1 U3 \5 [5 v" R0 O: r1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
' s2 c1 ~: Y' O5 f1 u7 y1 o. z2231399 SYSTEM_CAPTURE IMPORT_BLOCK 'importBlock' Tcl command not working when using a script) U4 Y7 F% F; d6 p& Q; S; M
1907729 SYSTEM_CAPTURE IMPORT_DEHDL_ Import DE-HDL sheets - differential pair properties on nets are lost
a. o- o3 X- w% |1 Y- f0 M$ ]2025949 SYSTEM_CAPTURE IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not translate in System Capture
1 p" ^) W- U1 u' U3 ~4 S4 \; l1942542 SYSTEM_CAPTURE IMPORT_PCB System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks
2 c) P& m! | i9 `1 u( x1982320 SYSTEM_CAPTURE IMPORT_PCB View files are not created in the schematic-to-board flow$ J- ` e% E& d
2117532 SYSTEM_CAPTURE MENUS_AND_TOO Ability to customize menus for a site$ b8 J* ?6 |6 T2 @
2213478 SYSTEM_CAPTURE MENUS_AND_TOO Help - About menu item appears twice
! |1 W0 i }, _" h1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlist and BOM, w2 S0 I/ ^8 }( _+ F
1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
$ D3 ~- H6 g7 @& |) B8 M. g2189846 SYSTEM_CAPTURE MISCELLANEOUS Inconsistent display of same font
[! m+ O1 F; d6 S3 V3 d) X2178961 SYSTEM_CAPTURE NOTES Cannot add Japanese text in notes in release 17.4-2019 on Windows 10
# P6 c7 }" k5 ]) v J7 z1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture/ s6 r; H: r I& l* A! x* W
2079857 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture: Unable to select design to open if license selection box is canceled the first time5 b7 V9 G/ z& {" d% O0 J
2065025 SYSTEM_CAPTURE PACKAGER Export to PCB Layout reports wrong path but exports correctly/ r8 K5 O) w3 f/ p
2229611 SYSTEM_CAPTURE PACKAGER Path for the 'packaged' folder shown in the 'Export Physical' is incorrect- ?/ \" @- y, @' q0 y2 e
1993146 SYSTEM_CAPTURE PROJECT_EXPLO Cannot move page up by only one position
' T% n9 a$ V; S6 W b. K/ ?1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts are missing reference designators and some have two properties - RefDes and REFDES
* r. J5 n% [1 u2 X Y2201060 SYSTEM_CAPTURE PROPERTY_EDIT Some of the icons in the Properties window do not have tooltips
, t/ W% X8 a! e! Z: V2246667 SYSTEM_CAPTURE SCRIPTING Running the 'replay.tcl' script gives an invalid command name error: n* T9 `5 V$ U5 m$ S
2010032 SYSTEM_CAPTURE SHORTCUTS Cannot enter Page-Up/Page-Down as shortcuts% `) [8 s# H' P' r* |7 s
2017985 SYSTEM_CAPTURE TDO Allegro System Capture ability for multiple users to open a design4 e# g; m: @( A$ |' o
2106743 SYSTEM_CAPTURE TDO Ability for multi-user access to the same schematic
H( c! e, V! S2209628 SYSTEM_CAPTURE UI Tooltips for Design Rule Checks are getting truncated5 g( c' g/ ?3 E8 H) T" M3 C
1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number3 c4 l7 U" G% H0 K) \& a! C$ a
2032005 SYSTEM_CAPTURE VARIANT_MANAG Custom variables not saved for variants
9 R& |* Q$ F+ v7 M1 i4 k6 `/ L2228299 SYSTEM_CAPTURE VARIANT_MANAG CAP parts should not show up in the Preferred Parts list when changing a RES$ y. \, Z4 {4 M- s; H$ j$ m
1627835 SYSTEM_CAPTURE WIRING Inconsistencies in wire movements Z, o) s# R _; T. e
1670888 SYSTEM_CAPTURE WIRING Rotation error when a component is connected to a power symbol
6 U& I5 _8 P. v3 a1721863 SYSTEM_CAPTURE WIRING Net names move to random locations when components are moved around the canvas.
! X" S# v: \5 u0 J, Y* A, [1960130 SYSTEM_CAPTURE WIRING Disconnected nets when using the mirror option7 B0 w& d5 E [* v5 b
1961274 SYSTEM_CAPTURE WIRING XNet removed during pin swapping
; ~ j4 e4 t1 _6 F ^1968463 SYSTEM_CAPTURE WIRING System Capture should not allow illegal characters to be entered for net names; H( |# f+ T7 \4 c
1973426 SYSTEM_CAPTURE WIRING Selecting multiple net names and trying to delete only deletes one net name.
: h- w2 L, C# o1978381 SYSTEM_CAPTURE WIRING 'oops' does not remove the first vertex placed
0 @/ i' {" h6 B; v% j5 k1985029 SYSTEM_CAPTURE WIRING Net aliases are not dragged with circuit, they appear to move after the circuit is dropped# n* u9 d! `: {' \0 p. J" O
2013647 SYSTEM_CAPTURE WIRING Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections) x; p2 X* e4 j$ r+ Q3 W
2014188 SYSTEM_CAPTURE WIRING Context menu not working in Variant mode
, w& V- r t! ~1 M: q7 H' m& ~6 L9 }- A+ J2041879 SYSTEM_CAPTURE WIRING XNets generated for nets with pull-up resistors
& k: }) f3 x+ y5 Z2050533 SYSTEM_CAPTURE WIRING Need an option to increase junction dot size5 e+ G& g' P3 L9 h, E
2061877 SYSTEM_CAPTURE WIRING Unable to add a power symbol with the Place - Special Symbol menu
) w9 p8 p* F5 T4 M* f7 |" [2079409 SYSTEM_CAPTURE WIRING Increase the size of the wire connection dot in System Capture4 p! r' e, S0 z: M
2081884 SYSTEM_CAPTURE WIRING Symbols take a long time to move, and results in DRCs and broken connections
7 K/ ?/ c! e; e7 T2085263 SYSTEM_CAPTURE WIRING System Capture: Focus lost from the Format tab if font name starting with typed letter is not present
: A) R2 \, K7 Z9 V1 f3 @2089569 SYSTEM_CAPTURE WIRING Ability to specify the solder dot radius size
/ Y# p0 J! G4 a0 |1 X! [% F
" E( |: Y3 t z, eQIR1详细特性说明：
Hotfix_SPB17.40.007_README-Release_Notes.pdf
(2.51 MB, 下载次数: 55)
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待我上传完后附上链接，这次QIR1比较大，4.59 GB
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发表于 2020-6-8 02:00
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发表于 2020-6-8 09:10
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