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本帖最后由 金志峰 于 2020-6-8 03:33 编辑
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cadence orcad and allegro 17.4-2019 QIR1新特性 D5 d, g( P, Q6 ^
·焕然一新的图标及UI. l2 ~0 D2 ~5 _/ H* ]
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QIR1中全新启动界面 （点击图片放大）& w1 D( b# c: U! J
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QIR1中全新启动界面（点击图片放大）! K% f6 U" G8 R$ E
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4 @& J6 d# w; `/ q0 i+ cQIR1中capture官方Dark主题（点击图片放大）(QIR1中UI界面中所有图标也全部更换全新并统一了)
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QIR1中capture官方Light主题（点击图片放大）$ V9 B* m2 S: N; O* w$ R
(QIR1中UI界面中所有图标也全部更换全新并统一了)
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2 s Z `2 D) |QIR1中PCB Editor新增官方Dark主题（点击图片放大）8 [" S9 `& K8 R& X* H, f1 Y( d! h
(QIR1中UI界面中所有图标也全部更换全新并统一了)9 `3 M) K/ s" l! t3 V2 F
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QIR1中PCB Editor官方Light主题（点击图片放大）; e$ N9 L$ s9 w3 Q' O
(QIR1中UI界面中所有图标也全部更换全新并统一了)
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' h" O* U: H: ]1 vFixed CCRs: SPB 17.4 HF0072 y y. C. T$ ^( r( b
05-21-2020; K4 Q, y3 P. i5 J7 W. Y
========================================================================================================================================================7 m8 K- g K0 _: o) l, U& p
CCRID Product ProductLevel2 Title
V3 G3 S5 B4 N========================================================================================================================================================& |$ X+ o# s, H% d! m) O
2247686 ADW CORE Allegro EDM: Unable to create a project using a newly created flow
4 k0 l/ S; K: b7 `# l9 C2137594 ADW DBADMIN EDM is not allowing changes to STEP models5 U9 X( g' @& L1 w9 W" r% ^2 M+ s* Y
2135452 ADW DBEDITOR DBEditor poor peRFormance in high-latency networks$ a# ?/ c5 V4 g
2113265 ADW LIBDISTRIBUTI Various database operations take a long time; rebooting server seems to fix the problem) S& w' _8 _2 _: j% J
2122941 ADW LIBDISTRIBUTI Lib_dist execution taking a long time to run; Capture CIS DBC file appears to be taking the most time
1 T' v. Z; ^* M N; |+ K2127319 ADW LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250)
+ d. t+ X) c. v& R) K8 v1975317 ADW PART_BROWSER Space at the end of the line in CDS.LIB results in zero libraries being shown in System Capture library search5 z' H" e5 |* W( }- H
2078057 ADW PART_BROWSER Symbol Graphics preview is not available in Designer Servers0 F0 p s, d) k4 i
2092863 ADW PART_BROWSER System Capture library search is not displaying the symbol and footprint preview2 h3 T) O9 z/ U- e
2086463 ADW PART_MANAGER System Capture cannot add components when accessing remote machine via Citrix0 `5 E) z" [, i) b4 u
2092868 ADW PART_MANAGER Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not flow from pstchip
Z- x* W# Q* _0 x2 O7 u% X# Y2092872 ADW PART_MANAGER System Capture stops responding when importing from DE-HDL
- R1 }0 R8 j. O: R* D' l2113226 ADW PART_MANAGER System Capture stops responding while importing DE-HDL sheets
5 D, H9 u, }" g# s( s5 K* N# ]2212406 ADW PART_MANAGER Allegro System Capture: Part Manager is deleting properties from all instances upon Update0 k1 A9 k5 ^' j/ O3 Q/ s# O$ D
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
6 F/ S+ r$ f9 `" a2 g! s9 w2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to Team Design
; R) c% A% g7 P1 [( f+ t: n2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
5 b2 u+ l$ f/ ^5 G) a% y) V% Q( N2048086 ALLEGRO_EDITOR 3D_CANVAS Wire bonds are not linked to die pad when component is embedded body down8 k A% x& Q5 o, y0 h. `
2051277 ALLEGRO_EDITOR 3D_CANVAS Vias are offset from board in Z direction in 3D Canvas
8 ^ S7 d( J8 L' n2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas4 t$ r& n5 _1 Q6 h0 \) _& z' p
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
( B4 C+ h b9 i2079732 ALLEGRO_EDITOR 3D_CANVAS Enhance 3D Canvas to merge the lines segment and overlapping lines and shapes4 ^& O0 y$ h% S" w5 Y" ]: m3 \
2206045 ALLEGRO_EDITOR ARTWORK Artwork Control Form fails to create film if Film record has a period (.) in the title6 ^- E0 ]( V! p1 N W8 d5 |9 t' N9 Z
2209200 ALLEGRO_EDITOR ARTWORK PCB Editor stops responding on rebuilding apertures without rotation
4 X: G8 D; l% b+ M2244407 ALLEGRO_EDITOR ARTWORK Automatic editing apertures with rotation takes time in the General Parameters tab of Artwork Control Form, G* B1 k( t' d
2267942 ALLEGRO_EDITOR ARTWORK Allegro PCB Editor stops responding when generating apertures in HotFix 006
8 D/ E7 ?: V, ~; n5 D* j$ V! g567342 ALLEGRO_EDITOR COLOR Add option under View menu for 'load color view'
0 F6 N7 F! m+ \) H. \, m3 H637828 ALLEGRO_EDITOR COLOR Line highlights in 'shape select' command
* d `9 a* T7 m. T* X& a720274 ALLEGRO_EDITOR COLOR Add menu option for the 'colorview load' command u5 F9 c8 B- n! D4 ?' b, Y
1602652 ALLEGRO_EDITOR COLOR Color/Visibility behavior variation using "Enable Layer Select Mode"
4 Y! W' m9 A. S7 {2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set
8 l$ M9 K$ I0 d4 u% G4 q4 M2207580 ALLEGRO_EDITOR COLOR Component color is inconsistent when display_nocolor_dynamics is set.
. D/ F! B5 b# ]8 R& W2056497 ALLEGRO_EDITOR DATABASE Place manual is slow- | z% u0 q3 R
2250988 ALLEGRO_EDITOR DATABASE Inner Layer keep out as illegal subclasses: Shape object may not exist on layer ROUTE KEEPOUT/INNER_SIGNAL_LAYERS |0 B- r- Y$ [4 `( q: Z+ z7 ]
2096958 ALLEGRO_EDITOR DFA Cannot launch Constraint Manager after assigning CSet and closing
' p4 D9 ]. n( h8 G& I2049681 ALLEGRO_EDITOR DFM DFF check for plating in via should not flag DRC for surface mount testpoint Via
; ?) U$ y7 Q# [# @2155060 ALLEGRO_EDITOR DFM Inconsistent behavior in displaying DRCs for Via to Via spacing6 s0 j$ }" R8 ~+ F4 u) r
2166431 ALLEGRO_EDITOR DFM DesignTrue annular ring thru pin pad to mask checks compared to smd pin to mask checks are inconsistent in behavior
2 g& n3 Y$ K2 m. M" {2221975 ALLEGRO_EDITOR DFM DFM missing mask check reporting mask is missing when pins have a mask geometry overlaying them.; J' e8 {* X# L3 J* Y
2249498 ALLEGRO_EDITOR DRAFTING When a Symbol with a Dimension is placed on the board, an extra Dimension is added to the Symbol origin.
7 e+ w" [7 T/ N# k6 D2250631 ALLEGRO_EDITOR DRC_CONSTR Cannot import netlist into design due to illegal DRC element: no DBDoctor error, y e+ \0 l z4 D4 w& Z
1794593 ALLEGRO_EDITOR EDIT_ETCH Unable to deselect return path vias selected when creating High-speed via structures5 `, d/ ~) s8 c1 a" c) K( ]" o
2099538 ALLEGRO_EDITOR EDIT_ETCH Gloss - Via Eliminate shifts traces to another layer$ a2 X+ v, }- w+ y
2204339 ALLEGRO_EDITOR EDIT_ETCH Differential pair line lost during slide operation
Z; `' R& ~, T3 ]6 l q' s% t2208938 ALLEGRO_EDITOR EDIT_ETCH Slide operation makes one of the differential pair cline invisible
1 D) O7 Z' V4 g4 S& Y. J. F2222047 ALLEGRO_EDITOR EDIT_ETCH One of the traces disappear when sliding a differential pair in single trace mode2 z* r2 U+ e: r+ m0 |
2233991 ALLEGRO_EDITOR EDIT_ETCH One cline of a differential pair disappears temporarily upon sliding the Differential Pair in Single Trace Mode' W8 ~/ s: p. S, H
2240827 ALLEGRO_EDITOR EDIT_ETCH Cline of a Differential pair net disappears after sliding the other net of the Differential pair
: ]+ W8 _; V! z. b3 j2245775 ALLEGRO_EDITOR EDIT_ETCH Differential pair slide in single trace mode removes other trace% Z6 Y( _7 M: d" ]- p0 h7 y
1813358 ALLEGRO_EDITOR GRAPHICS Allegro PCB Editor enables shape boundary when disabling etch layer in Visibility pane$ {, D: T2 G0 ], _
1911613 ALLEGRO_EDITOR GRAPHICS The subclass for boundary class stays on, even if Subclass for Etch Class is turned off from Visibility tab
' y* j0 T* E. {- `' R1966343 ALLEGRO_EDITOR GRAPHICS Shape boundary remains enabled even after turning off the etch layer visibility
3 j$ X4 W, [) I$ s5 Q! \2195276 ALLEGRO_EDITOR GRAPHICS Selecting File view is slow
7 ~/ o) A5 o1 g" b: j& a7 ~. z. G2031883 ALLEGRO_EDITOR INTERACTIV Sub-Drawing: Clipboard origin point is not set correctly( w: _5 }3 X4 f
2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Shape ANDNOT operation" Z$ w0 {9 }( W" x# ]' J* Y$ p
2069247 ALLEGRO_EDITOR INTERACTIV DFA bubble on wrong layer after mirroring the part' I) N0 M* o \1 }, J3 e
2103711 ALLEGRO_EDITOR INTERACTIV Placement edit mode popup 'Rotate' leaves ghost image in the background8 `" G5 E. Z2 H, e6 j& z4 I
2136859 ALLEGRO_EDITOR INTERACTIV DFA Problem if we mirror component while placing$ ]0 \' b1 U% r4 F m! @
2165027 ALLEGRO_EDITOR INTERACTIV Different behavior in OrCAD Capture when using crossprobe to select Power nets& Q% i7 l( X: m
2240235 ALLEGRO_EDITOR INTERACTIV The design file name changes automatically to board template name while creating new board (wizard).' r# {, N& b6 M+ C+ s
2244765 ALLEGRO_EDITOR INTERACTIV License 4150+226 does not have AiDT/AiPT in release 17.2-2016* Z! F; Y8 _, x7 `
2259800 ALLEGRO_EDITOR INTERACTIV DFA DRC circle not shown on the layer of placement in Placement App Mode+ U& Y2 B4 R5 q) d; H& X4 M& H1 }
2120420 ALLEGRO_EDITOR INTERFACES Drill figures missing in the exported PDF if drill legend deleted+ ^' C8 G; V. b7 h+ S% O* p1 T
2136454 ALLEGRO_EDITOR INTERFACES Export - PDF output is not correct
9 }" ~2 v3 ^$ f9 z4 K2116748 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets5 C5 L& [% Y# W7 ?5 E* i8 e
2138977 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to 17.2-2016, HotFix 057' z+ B( _$ B: y6 E
2247167 ALLEGRO_EDITOR IN_DESIGN_ANA IDA Impedance Analysis: Add an option to export CSV automatically& g! I3 y8 [8 p3 Z" Z, h# R h% u+ v
2222638 ALLEGRO_EDITOR IPC Documentation Editor crashes with error: Failed to complete the job because of unspecified error2 [' K2 ^5 k8 K D, n- o% u
2106425 ALLEGRO_EDITOR NC Disable undersize regular pad and oversize soldermask pad for start layers in Backdrill Setup and Analysis
u' H1 b# h E1 n' N2091932 ALLEGRO_EDITOR OTHER Unsupported Prototypes command missing for the OrCAD licenses* e4 e" y- |$ o0 Z$ E
2221345 ALLEGRO_EDITOR OTHER Speed up Allegro PCB Editor startup by removing check for defunct PCB/Package co-design capability (NG_450)$ ^9 l9 v7 p, e2 A' ~& t
2257934 ALLEGRO_EDITOR PLACEMENT Error (SPMHGE-626) on place component: Symbol not valid on any layer" N! O1 p k4 d# Q: u$ l
1001000 ALLEGRO_EDITOR PLOTTING File - Plot in PCB Editor does not plot more than one copy% U3 v$ l# \0 Y+ d& j
2234538 ALLEGRO_EDITOR REPORTS Allow Unused Blind/Buried Via report to run as Batch Process through the reports batch command
* `2 g7 }% T$ ?4 d9 g$ T# f) O2222738 ALLEGRO_EDITOR SCHEM_FTB Netrev not completing, showing error for electrical constraints data (pstcmdb.dat) import6 i; Y1 p6 f r7 E/ q
2255426 ALLEGRO_EDITOR SCHEM_FTB Netrev is running for hours without closing* Q$ g: p8 D2 @: x% a
1702190 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script file: Some sub-classes not created and error for form field label
K& O& _# \, A( k) F1 `; R1791099 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor does not terminate when the script is run with '-nographic'% T# I( ~5 I6 Q! ^$ j
1791267 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script does not run with '-nograph' in release 17.2-2016! U1 Y4 `( X" a4 B: V$ {( D. d
1892520 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with '-nographic'
( B8 G- W; t o# e( q' Q( [6 t- a1962010 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with -nongraph option
- F! ]& D) N. E9 ~% U: z2056857 ALLEGRO_EDITOR SHAPE Shape boundary error by shape parameter0 C! L' Z$ e; L# X& w2 n2 ~) {
2081946 ALLEGRO_EDITOR SHAPE Shape Update takes twice the time in release 17.2-2016, HotFix 053 as compared to HotFix 047: y8 {: \7 ?9 p
2104559 ALLEGRO_EDITOR SHAPE PCB Editor crashes while performing shape operation 'andnot'6 m6 e q, Q0 D9 u, `% Q; T
2108207 ALLEGRO_EDITOR SHAPE No Void Overlap option is not working in Auto Metal Balancing (AMB); x4 l K( W( x, i" i3 K
2240996 ALLEGRO_EDITOR SHAPE Detecting Shape Island: Ignored for copied or moved shape' b& v" B/ U* b4 R# l4 y( a e
2258758 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes when routing two signals together% r7 l( J- t0 O
717389 ALLEGRO_EDITOR skill Ability to set and return the application mode using SKILL
! H: [) M# j3 n c% A853160 ALLEGRO_EDITOR SKILL Need ability to get and set application modes using SKILL- r4 H4 Y6 w! S/ ~
981446 ALLEGRO_EDITOR SKILL Request the ability to get and set application modes using SKILL
; Y# H# `% i5 }( w9 V1235409 ALLEGRO_EDITOR SKILL SKILL option to get application mode
7 O. s' u X) B4 m5 `1316962 ALLEGRO_EDITOR SKILL SKILL option to switch between application modes% Z# r2 J0 _9 R. }% Q: ]1 d
1553621 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function
2 F2 l5 D- q% P1 M/ v! V' C$ Y1885442 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function.8 \; x0 _- v, T) b
2080351 ALLEGRO_EDITOR SKILL SKILL to determine current application mode
3 C1 v0 V j' Q2195645 ALLEGRO_EDITOR THIEVING Thieving pad cannot be added on some areas in the board in latest hotfix but could be added earlier
, m4 ?5 k0 x, j" U, a$ l, B: H1721594 ALLEGRO_EDITOR UI_FORMS STEP name Filter for STEP Package mapping form should be case insensitive; f! [0 \5 e+ ]2 g( C4 s1 c
2090604 ALLEGRO_EDITOR UI_FORMS Undo/Redo UI grayed out when invoking Color1920 G3 g2 o5 X* ]* U: j/ D
2203278 ALLEGRO_EDITOR UI_FORMS 'Width' keyword in Place Rectangle field is grayed out when Place Rectangle is selected+ o1 ^) u Z8 e9 b6 ^: g0 x
2209172 ALLEGRO_EDITOR UI_FORMS Labels truncated by drop-down lists in Options ('Manufacture' - 'Drafting' - 'Relative Copy')8 F% `+ W: t2 d. W+ R/ k
2239426 ALLEGRO_EDITOR UI_FORMS Cannot start text size with decimal in 'Design Parameter Editor' - 'Text' for English (Denmark) regional settings% w$ H; u4 L U% x
2245035 ALLEGRO_EDITOR UI_FORMS The right edge of the default Define Grid form looks cut off in 17.4.
) V6 M4 c* @% n3 a4 _3 @$ U2245955 ALLEGRO_EDITOR UI_FORMS Resizing of 'Reject Item Selection' window not possible in release 17.4-2019, HotFix 004$ M: ^- v0 `% ]& I" K: [" S1 t
2249202 ALLEGRO_EDITOR UI_FORMS Extra click required to activate Pass field in Autorouter form
. }+ h0 }: c& j2259605 ALLEGRO_EDITOR UI_FORMS Add ability to resize Reject pop-up
* {; |6 c* `6 h% u& }- Y2090517 ALLEGRO_EDITOR UI_GENERAL Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane* m' b5 K/ J) Z5 b
2092436 ALLEGRO_EDITOR UI_GENERAL RefDes length of input string for Modify Design padstack is limited to 20 characters
! t/ K1 w4 d0 Q7 [1 I N2134781 ALLEGRO_EDITOR UI_GENERAL The Pin Class is missing in Options tab when creating or opening a Mechanical Symbol$ p/ }) ^& |( W& v" D Q& y
2168026 ALLEGRO_EDITOR UI_GENERAL Edit Properties UI slow to launch for boards with many drawing properties
9 [/ z1 `! X3 F2 |6 q$ D2191267 ALLEGRO_EDITOR UI_GENERAL Changing Visibility of any object type disables links in Layer Select Mode in the Visibility pane
* }/ R$ n- a3 ~/ _2208018 ALLEGRO_EDITOR UI_GENERAL Text on BGA pins not visible in release 17.4-2019 if not zoomed to maximum
" B4 l$ u0 D6 ~; i% W2225753 ALLEGRO_EDITOR UI_GENERAL dark theme does not respect TRBICON size for 4K monitors* {7 K: V/ o' U
2256841 ALLEGRO_EDITOR UI_GENERAL Enlarge the Shape Copy to Layers form as the window is quite small and not resizable! b. k5 _0 d5 |) V
2258019 ALLEGRO_EDITOR UI_GENERAL Canvas turns white after closing STEP Package Mapping window0 e! U, E7 A# H8 |; S7 B
2258167 ALLEGRO_EDITOR UI_GENERAL Enhance 'Shape copy to layers' window in release 17.4-2019 to expand or resize
# ?9 @1 u0 { J5 O0 i# p, U2262305 ALLEGRO_EDITOR UI_GENERAL Assign Differential Pair form list box size too small to add signals
7 b3 l% E2 `% h2086574 APD OTHER APD is showing duplicate layer text on the vias
! A- O' {0 O: Q1723825 APD SCRIPTS Allegro Package Designer in release 17.2 is not writing out to either jrl files or script files in real time.
+ `; F; p# q5 A2186363 APD UI_GENERAL Text on the Pin is not visible until zoomed in to certain extent, Y. C0 r4 V% s) i; r! v
2253484 APD WIREBOND APD stops responding when running 'wirebond soldermask create' with 'Measure from soldermask pad'0 G. U6 L# P4 V
2241725 CAPTURE DRC Waive DRC option not working from batch DRC window* ^; W- _, F n( C8 d( K/ n
2243645 CAPTURE DRC Online DRC bug in release 17.4-2019, hotfix 004 - offpage connector does not have wire
/ M; h) L. Q: T' \2250867 CAPTURE DRC Hanging wire custom DRC not working when selected standalone
2 \: B% ^. R: C# [* Z E* ^2252912 CAPTURE DRC Unable to create new DRC file using Browse button in DRC window+ }; v, x: b$ G# k0 F
2047391 CAPTURE PART_EDITOR Pin type cannot be changed in release 17.2-2016, hotfix 051
! X$ F- ]) @9 @6 z, \2183187 CAPTURE SCHEMATIC_EDI OrCAD Capture: Ctrl + N seems to call a legacy dialog that allows projects to be created with no name
# I- x! [- f, e! Q2190602 CAPTURE SCHEMATIC_EDI Cascading options of Window menu not working in OrCAD Capture in release 17.4-2019, d6 L& b5 V& ?8 V, N
2194374 CAPTURE UX Design Sync issues: Session log does not report information about errors
) r% Q) z+ b2 E" I( v4 H2183037 CIS LINK_DATABASE CTRL-L shortcut for Link DB-Parts for Query in CIS-Explorer not working4 M. t0 i/ _; |2 \6 ]
2201323 CIS PLACE_DATABAS Capture CIS displays empty dialog on placing part from database in release 17.4-2019/ s+ l1 a7 l9 ^$ o3 p
2216963 CIS PLACE_DATABAS Light Theme: Warning text not visible in Capture CIS dialog- T5 u; z% l6 `* C1 l8 g
2246354 CIS PLACE_DATABAS Warning (ORCIS-6159) pop-up window is blank.
9 L1 I2 D( _# d' n% e) g2230651 concept_HDL CHECKPLUS Discrepancy in the 'checkplus' marker files
0 D6 O, X5 p7 l2237145 CONCEPT_HDL CONSTRAINT_MG T-Points match groups get deleted after saving a design8 [7 o9 k7 c0 _( N ~
2246452 CONCEPT_HDL CORE Page information gets removed from 'master.tag' of the top-level design when subdesigns are read-only
! h% y, V' ?* R8 x$ ?" v' l2057490 CONSTRAINT_MGR CONCEPT_HDL Constraint Manager Worksheet flips after running hier_write when CM is open
: N; P& d- Q r( B3 C' R. B" e2236329 CONSTRAINT_MGR CONCEPT_HDL Pin Pairs not added to Match Group! n' b, H* B; F" z; X* \
2214367 CONSTRAINT_MGR INTERACTIV CSet assignment matrix sorting in Net Class-class random in Capture to Constraint Manager flow' e) }4 M) F' Q- j% m% D
2243574 CONSTRAINT_MGR OTHER CM SKILL cmxlPutAttribute() cannot set constraint value
. Y1 M( b3 b, U u. F2259598 CONSTRAINT_MGR OTHER Importing netlist: Error for electrical constraint data (pstcmdb.dat) import
1 E5 R) x8 a5 i2207862 CONSTRAINT_MGR SYSCAP Save icon and 'File' - 'Save' menu in Constraint Manager is inactive
c! ^+ t3 ~5 b. j2200316 CONSTRAINT_MGR UI_FORMS Expanding 'Analysis Mode' form resets column width; J% c2 I0 x" ]" k* y" y
2097479 PCB_LIBRARIAN CORE Symbol import in Part Developer does not show the correct pin shape.
1 L& }2 _- m0 w2 w" [9 \2145385 PCB_LIBRARIAN CORE Error-SPLBPD-972 reports missing parentheses in the ALT_SYMBOLS property of a part4 O3 b" t6 l5 e3 l
2202622 PCB_LIBRARIAN CORE When adding a new pin to a symbol in Symbol Editor, the space between pins changes5 A; q, P3 x7 p' {: y
1955570 PCB_LIBRARIAN FLOW Using the PACK_SHORT property with more than 256 characters does not work or report an error on packaging9 ?* \, {! U9 K; \% x$ |$ ^
2072190 PCB_LIBRARIAN FLOW Allow PACK_SHORT property value longer than 255 characters
. j. I4 j v- T& U1720395 PCB_LIBRARIAN IMPORT_OTHER Converting OrCAD Capture OLB to Design Entry HDL library adds braces to pin number
0 V0 k- S( A; L" S0 N( I; u' c+ o2141340 PCB_LIBRARIAN SETUP SPLBPD-216 Error logged in PDV even when MAX_SIZE Sheet is defined
' r7 W* b4 J( a7 Q6 E& e) ?$ h2214973 PCB_LIBRARIAN SETUP Unable to apply symbol property templates when PDV lock directives are set
. K1 e4 F" M. n6 S7 i2257527 PCB_LIBRARIAN SETUP Locking PDV directives prevents applying symbol property templates: h) J2 s9 h& [2 w+ E7 P; F- i
2033898 PCB_LIBRARIAN SYMBOL_EDITOR Running Symbol Editor with no arguments results in a background process, not an error.4 Q, @7 z% v4 a, b& m
2093849 PCB_LIBRARIAN SYMBOL_EDITOR Symbols and font sizes appear different when placed in designs1 k" k% |8 e2 m* B% ]3 a
2200399 PCB_LIBRARIAN SYMBOL_EDITOR Multiple issues observed when editing parts in the New Symbol Editor
7 r, m/ T; f! K3 x E, p2218940 PCB_LIBRARIAN SYMBOL_EDITOR Duplicate pins cannot be removed
" v4 I, D' g. _$ B0 T5 V* n+ _8 I, H( N2230542 PCB_LIBRARIAN SYMBOL_EDITOR Bus pin location changes after expanding or collapsing pins in Symbol Editor7 [) |" F( r9 [
2239303 PCB_LIBRARIAN SYMBOL_EDITOR Expanding and collapsing a bus is changing the msb and lsb for the pin name. O/ n( e" ]7 L/ \. m2 W- ]
2243431 PCB_LIBRARIAN SYMBOL_EDITOR Group of pins that are not adjacent cannot be moved together) v( Q0 [/ v0 c. {1 C8 [
2029056 PCB_LIBRARIAN SYMBOL_EDITOR Unable to change Grid Settings in Part Developer
' m) T2 g7 F- ?2 M9 i2149948 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor and System Capture moved pins from 0.01 grid to 0.05 grid.- A' j1 h6 W5 g7 ]7 d
2206975 Pspice MODELEDITOR PSpice Model Import Wizard symbol preview readability improvement requested
, D$ Z/ P) o/ I3 O2211187 PSPICE MODELEDITOR Model Editor color scheme not readable. a3 U6 K6 \% \7 I
2214415 PSPICE MODELEDITOR Symbol view in Model Import Wizard has a visibility problem0 W7 l" a3 ?! c' W, l
2199570 PSPICE PROBE Unable to 'select sections' after Monte Carlo runs with Temperature
' W2 E( Q# ?$ z7 Y1 }4 U" X" j! J- b5 X2244140 PSPICE PROBE Not able to select multiple sections to plot in probe
- @$ }7 ]9 g2 X2249565 PSPICE PROBE Selecting multiple traces for PSpice A/D Monte Carlo run not working8 L5 M0 U: D: J/ Q' I
2171626 PULSE CORE Pulse crashed with error related to third-party development kit platform issue3 ~/ {$ w# Z- W" G
2221523 PULSE UNIFIED_SEARC Cannot log in to third-party search providers but can log in to Cadence Online Support% }) F5 T( U& m; B- Q, g
2019229 RF_PCB OTHER Layer conversion file data does not update GDSII layer mapping using Package Symbol Wizard
8 V: i1 D: S& O- q# O9 h820288 SIP_LAYOUT COLOR Layer Priority command does not seem to be functioning7 e, y, Y2 d6 B4 m) ^/ k
820305 SIP_LAYOUT COLOR Layer Priority menus do not match the Color dialog in the package substrate tools
, ^* L* r' ?1 r( q2256044 SIP_LAYOUT DATABASE Fix teardrop does not work for some situation: Deleting fixed fillets
: b t0 _& ~! Q) D2254932 SIP_LAYOUT DEGASSING APD Plus generating assertion failures when running degassing mode with script I5 i" v1 I9 w E- r
2106314 SIP_LAYOUT INTERACTIVE Large design causing severe lag in Windows Server machine
* W4 Q4 W) |9 w. c8 g! C, |4 t% R1 E2096239 SIP_LAYOUT STREAM_IF Database fails to create stream out file, `) f* t# b/ R+ V$ ]& [
2079071 SIP_LAYOUT SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die: F1 }$ Q: T, z, B+ V4 f( r
2251630 SIP_LAYOUT WIREBOND 'Change Profile' does not change the diameter of the wire bond
8 ^9 `* \' E% o2253633 SIP_LAYOUT WLP Advanced degassing passing illegal arguments to dba routine( {$ i- d2 z1 k. E& Y8 u
2259630 SIP_LAYOUT WLP Advanced WLP: Import PVS DRC results in error5 e4 A( B' G6 {+ C0 ~2 h
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though uppercase input is enabled
" i, W, U% l t. ~' p2 m7 ]2 G! c2131976 SYSTEM_CAPTURE AUTOMATION syscap exits when run with the -tclfile argument and an invalid Tcl file* u/ b' v, ~" B* c" o, N3 k
1983063 SYSTEM_CAPTURE BLKDIAGRAM_AU Auto Shapes are being shown as part of components
2 f: t( L0 t5 A& A" k1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name4 n7 B4 K+ G! l( s* v. I6 z5 C8 w
2247567 SYSTEM_CAPTURE COMPONENT_BRO Symbol property placeholder changes not updated on the canvas
7 z! L& R+ a( k! D* I9 x2 E2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System Capture is not being updated when individual netlist files are written% Y* J' O1 R( U
1863460 SYSTEM_CAPTURE DARK_THEME thumbnail preview of pages is in light them but dragging the page the previes is dark. O# J. Y' S2 @( h# p5 S
2168622 SYSTEM_CAPTURE EDIT_SEARCHRE Reports from Find Results are dumped even when the operation is canceled a0 U! P/ L' I; a+ i% J# k) O
2168625 SYSTEM_CAPTURE EDIT_SEARCHRE Sort icons for columns in 'Find Results' are incorrectly placed: appear to be in adjacent column
! N3 W* x0 x# a- m- l1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture incorrectly reports unsaved changes when closing after running export physical
/ \( r" P8 ^$ n+ \. X1931660 SYSTEM_CAPTURE EXPORT_PCB SDA is non-responsive while Allegro launches and opens a board when launched from SDA' y8 v6 v) t+ L1 n) w; ]
2087387 SYSTEM_CAPTURE EXPORT_PCB System Capture: After Export PCB completes, busy cursor shown for a while7 y: f! l& j4 D' J0 O* W4 R
2202179 SYSTEM_CAPTURE FIND_REPLACE Replacing a net name with the same name by using Find and Replace results in a crash
( ?) T) {* ?4 h! A* Z1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
8 w. n" E0 R3 l$ S4 s1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
8 B! }3 @7 W) V$ ~2231399 SYSTEM_CAPTURE IMPORT_BLOCK 'importBlock' Tcl command not working when using a script4 e) q- U0 _6 }4 E; s
1907729 SYSTEM_CAPTURE IMPORT_DEHDL_ Import DE-HDL sheets - differential pair properties on nets are lost3 r; G/ w7 y8 G/ J; n" g. a. `# C
2025949 SYSTEM_CAPTURE IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not translate in System Capture
7 b g; o4 ^5 f1942542 SYSTEM_CAPTURE IMPORT_PCB System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks
4 u; d$ ?8 X+ }& ~( Y* W* a1982320 SYSTEM_CAPTURE IMPORT_PCB View files are not created in the schematic-to-board flow
8 Y, | E9 {: m" P' S2 v1 j2117532 SYSTEM_CAPTURE MENUS_AND_TOO Ability to customize menus for a site
* g _# t' f/ w8 ]$ s% y4 F2213478 SYSTEM_CAPTURE MENUS_AND_TOO Help - About menu item appears twice' ]' E1 T# J6 O4 I
1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlist and BOM
7 o1 e) r* L" L7 e1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it& C- X2 h j; X. F4 x( W
2189846 SYSTEM_CAPTURE MISCELLANEOUS Inconsistent display of same font
9 h/ E* L: ?$ J R! z/ @2178961 SYSTEM_CAPTURE NOTES Cannot add Japanese text in notes in release 17.4-2019 on Windows 10
1 @: p9 ]/ L3 r% \" [1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
( G; I2 _9 U% l2079857 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture: Unable to select design to open if license selection box is canceled the first time
6 I1 l" s% P4 e+ S3 ^8 @* p2065025 SYSTEM_CAPTURE PACKAGER Export to PCB Layout reports wrong path but exports correctly
' e, D( o5 D5 H8 y1 p+ d2229611 SYSTEM_CAPTURE PACKAGER Path for the 'packaged' folder shown in the 'Export Physical' is incorrect$ S, y# b8 b2 r& F) a* \' W
1993146 SYSTEM_CAPTURE PROJECT_EXPLO Cannot move page up by only one position
+ T, \; @8 v( M1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts are missing reference designators and some have two properties - RefDes and REFDES7 ^7 O/ v$ k6 K. o8 p2 e# Q j4 n
2201060 SYSTEM_CAPTURE PROPERTY_EDIT Some of the icons in the Properties window do not have tooltips* g c; A$ ]' E) Z2 T. K
2246667 SYSTEM_CAPTURE SCRIPTING Running the 'replay.tcl' script gives an invalid command name error
x1 Y, ~. v' i ` E2010032 SYSTEM_CAPTURE SHORTCUTS Cannot enter Page-Up/Page-Down as shortcuts
* o7 n; A/ u5 A" o2017985 SYSTEM_CAPTURE TDO Allegro System Capture ability for multiple users to open a design
: h) [ O: F! c2106743 SYSTEM_CAPTURE TDO Ability for multi-user access to the same schematic
I( z# _0 d6 ]! [. o" \6 B2209628 SYSTEM_CAPTURE UI Tooltips for Design Rule Checks are getting truncated. }" W7 H7 U3 Q4 Z. w/ N: T
1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number6 K5 u& b4 }( W/ g
2032005 SYSTEM_CAPTURE VARIANT_MANAG Custom variables not saved for variants+ [0 J: B- n, m$ ?( n' X) f
2228299 SYSTEM_CAPTURE VARIANT_MANAG CAP parts should not show up in the Preferred Parts list when changing a RES0 H w g2 h2 {
1627835 SYSTEM_CAPTURE WIRING Inconsistencies in wire movements
% U& ]( r" h3 G$ j1670888 SYSTEM_CAPTURE WIRING Rotation error when a component is connected to a power symbol
, ?/ v) e, V+ P1 Z. }1721863 SYSTEM_CAPTURE WIRING Net names move to random locations when components are moved around the canvas.
) w" x- i: Y$ z P8 c3 F1 {1960130 SYSTEM_CAPTURE WIRING Disconnected nets when using the mirror option2 {7 ?) p# R$ x7 X
1961274 SYSTEM_CAPTURE WIRING XNet removed during pin swapping
- k) Y( Q7 i: ?. J/ j) _1968463 SYSTEM_CAPTURE WIRING System Capture should not allow illegal characters to be entered for net names' T- F8 H# i r
1973426 SYSTEM_CAPTURE WIRING Selecting multiple net names and trying to delete only deletes one net name.
0 Q. J# m9 p* |, f+ i! I1978381 SYSTEM_CAPTURE WIRING 'oops' does not remove the first vertex placed" a5 U1 \2 u* k5 d6 [
1985029 SYSTEM_CAPTURE WIRING Net aliases are not dragged with circuit, they appear to move after the circuit is dropped9 P2 k' V/ Z# U# n
2013647 SYSTEM_CAPTURE WIRING Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections# r1 }6 f8 S Q, G9 {" F
2014188 SYSTEM_CAPTURE WIRING Context menu not working in Variant mode
# y/ n, z5 r* m* `. e9 ~: X2041879 SYSTEM_CAPTURE WIRING XNets generated for nets with pull-up resistors9 g5 `2 R T2 [+ i
2050533 SYSTEM_CAPTURE WIRING Need an option to increase junction dot size
! q: H9 Y% m) P3 _- ?( F2061877 SYSTEM_CAPTURE WIRING Unable to add a power symbol with the Place - Special Symbol menu: a; v$ Y+ u6 F Z. U9 e, Y
2079409 SYSTEM_CAPTURE WIRING Increase the size of the wire connection dot in System Capture' s7 I8 ]# i: r9 ~- \9 g! }
2081884 SYSTEM_CAPTURE WIRING Symbols take a long time to move, and results in DRCs and broken connections/ L8 L; v- W9 Q4 y8 \
2085263 SYSTEM_CAPTURE WIRING System Capture: Focus lost from the Format tab if font name starting with typed letter is not present
0 w0 O/ w; i' e2089569 SYSTEM_CAPTURE WIRING Ability to specify the solder dot radius size
3 C/ K) y2 `, W9 r) q6 U0 b ~9 f) F/ b
QIR1详细特性说明：
Hotfix_SPB17.40.007_README-Release_Notes.pdf
(2.51 MB, 下载次数: 55)
$ Y: u M. Q; m9 N9 m/ g3 C9 N1 i待我上传完后附上链接，这次QIR1比较大，4.59 GB 4 _7 ~ V: O% H# ^5 P
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发表于 2020-6-8 02:00
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