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* F2 z& P7 N! o6 A2 p+ S+ B1 I$ `作品名:[AD 10][2层] XILINX_LCD2VGA(XC3S50AN+SDRAM_32M+LM1117-3.3)原理图、PCB源文件( T: X" u8 b" |3 m( t
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* A, C, ?* {$ U3 j4 [& f. _4 J文件描述, N- x/ ^+ ^# O6 B9 S! E
1. 作品用途:XILINX_LCD2VGA. d- u- b7 O6 ~1 P8 d
2. 软件版本:AD 100 Y3 Q1 h- z7 E2 j5 V( W" S
3. 层数:2层板9 x' c9 L( q. P% T
4. 用到的主要芯片:XC3S50AN+SDRAM_32M+LM1117-3.3
/ F6 S6 w% l9 o. a5. PCB尺寸:100mm*78mm0 P: R* g5 Y1 s) k B5 p% v/ m
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0 N+ n+ @. ~) ]6 V% c作品截图如下:1 N/ i6 [2 ^& C6 n& a [4 c
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全层截图:5 V, d- r I) Z0 l* J
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叠层信息截图如下:
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Comment(属性) | Designator(位号) | Footprint(封装) | Quantity(数量) | 104 | C1, C10, C35, C37, C39, C42, C45, C51, C52 | 0805 | 9 | 104 | C11, C12, C13, C14, C15, C34, C36, C40, C41, C46, C53 | 0603 | 11 | 0603 | C31, C32, C33, C43, C44, C49, C50, C54, C55, C56, C57, C58, C59, C60 | 0603 | 14 | 1206 | C38 | 1812 | 1 | 10 | C80 | 0603 | 1 | LED | D1, D6, D9 | 0603 | 3 | D | D2, D3, D4, D5, D8 | SOT-23 | 5 | CON6 | J1 | SIP6 | 1 | 40PIN | J5 | LCD | 1 | CON4 | J8 | SIP4 | 1 | SW DIP-4 | J9 | DIP8 | 1 | 1uH | L1, L2, L3, L4, L5 | 0603 | 5 | 22 | R1, R2, R3, R4, R10, R11, R12, R13, R14, R15, R20, R21, R22, R23 | 0603 | 14 | 10K | R5, R6, R7, R8, R17, R24, R25, R26, R28, R29, R30, R31, R32, R34, R35, R36, R37, R38, R39, R41, R42, R43, R44, R45, R46, R47, R48, R51, R52, R54, R55, R56, R57, R58, R59, R60, R61 | 0603 | 37 | RES4 | RN1, RN2, RN3, RN4 | SO_8A | 4 | TEST | TP1, TP2 | SMA | 2 | XC3S50AN | U1 | QFP20X20 | 1 | SDRAM_32M | U3 | SOL-54 | 1 | LM1117-3.3 | U4 | SOT-89 | 1 | LM1117-1.2 | U5 | SOT-23 | 1 | DIP16 | U6 | SSOP16 | 1 | DIP14 | U7 | SO-14 | 1 | DIP20 | U8 | VO20 | 1 | 20.000MHz | Y1 | CRY_1 | 1 | 32768Hz | Y2 | CRY_2 | 1 | 附件:
" p4 | ^; [2 u# Q原理图和PCB源文件如下:
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