还有没有在用0RCAD10.3精简版本的朋友？昨天开始不能使用了！

hubin6688

还有没有在用0RCAD10.3精简版本的朋友？昨天开始不能使用了！把系统时间往前调一天就可以了，好像是时间到期了，现在网上下载的10.3和10.5都不能用了，时间调一下就可以了，有没有哪位朋友遇到这个问题？

great058

我也碰到这个问题。

great058

SERVER xxx ANY 27001
DAEMON cdslmd c:\cdslmd.exe
7 K" L9 i; K; _: S" B! W( E; U# --------------------------------------------------------------------
#
! X3 `2 d9 E* C; O1 L. f4 o#       License for Cadence PSD Series
5 _8 {7 @* j  a6 M#
# --------------------------------------------------------------------
' A8 L  `+ B; t5 U! Y3 [" O7 B#       Generated especially for
- ^5 a. N2 a/ L0 j( i#       User:    xp04
0 l# o; ~$ L3 R( T9 c* _7 T6 A: X#       Company:
3 R4 Q- t8 W! p% a7 D- S; c# --------------------------------------------------------------------
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#       Mendling with Feature lines will only invalidate them!
#
6 v+ Q8 J: v. M$ h7 X' ~# --------------------------------------------------------------------
% t' [8 L4 O: H9 [; i! M! j#
PACKAGE EFA-CDS-01 cdslmd 2019.12 50D0C0F14EEEF46F0FE0 \
. K4 C# D6 u: M        COMPONENTS="A2dxf ABIT actomd adv_package_designer_expert \
        adv_package_engineer_expert ADV_USUPUC_ALL \
% l3 O* s7 A, }" c2 P/ h1 F3 B        Advanced_Package_Designer Affirma_NC_Simulator \
) P( C' M) z# {' p& N) [" [; o        Affirma_sim_analysis_env Affirma_transaction_analysis \
9 t0 C% h2 S; B6 s" D        Affirma_verification_cpit_rtim Allegro_CAD_Interface \
. S" S3 ]$ p1 _4 p# F" x        Allegro_design_expert Allegro_Designer Allegro_designer_suite \
! a, L6 h4 a7 P- p" ]* [        allegro_dfa allegro_dfa_att Allegro_Expert Allegro_Librarian \
" b  |1 F3 W+ b        allegro_non_partner Allegro_PCB Allegro_PCB_Interface \
) X9 ^' _; F$ Q; |  a        Allegro_performance Allegro_studio Allegro_Symbol \
        Allegro_Viewer_Plus allegroprance ANALOG_WORKBENCH APD \
        archiver arouter AWB_Batch AWB_BEHAVIOR AWB_DIST_SIM \
' ^' X+ R6 G' a2 U3 m' I        AWB_MAGAZINE AWB_MAGNETICS AWB_MIX AWB_PPLOT AWB_RESOLV_OPT \
3 b7 k8 ]7 ~! }/ r. x        AWB_RESOLVE_OPT"
7 k+ m  {7 g! N! v) g) r$ `PACKAGE EFA-CDS-02 cdslmd 2019.12 006030C10306920F9721 \
        COMPONENTS="AWB_SIMULATOR AWB_SMOKE AWB_SPICEPLUS AWB_STATS \
9 k; F) Y$ Q3 k% J; D- t        AWBAA AWBSimulator Base_Digital_Body_Lib Base_Verilog_Lib \
" N+ b3 N7 d4 J9 S6 @9 s$ Q        BOARDQUEST BoardQuest_Designer BoardQuest_Team BOGUS \
        Cadence_chip_assembly_rtr_ALL Cadence_chip_assembly_rtrEngr \
; K5 Z8 }; O' [' W2 T        caeviews cals_out Capture Capture_CIS_Studio CaptureCIS \
! x( }" ~5 D/ R/ ?, Z& j9 E( W" }        cbds_in cdxe_in CHDL_DesignAccess CheckADV_ALL CheckFST_ALL \
        Checkplus_Expert CISoption comp Concept_HDL_expert \
        Concept_HDL_rules_checker Concept_HDL_studio ConceptHDL \
( X) i4 f/ A2 m7 t        CP_Ele_Checks cpe crefer cvtomd CWAVES debug DFM_USUPUC_ALL \
        DISCRETE_LIB dracula_in"
& H" i/ F' K2 A+ \PACKAGE EFA-CDS-03 cdslmd 2019.12 40A0708139C03D1415F7 \
        COMPONENTS="dxf2a EB_4SUPUC_ALL EB_USUPUC_ALL eCapture \
        EDIF_Netlist_Interface EDIF_Schematic_Interface EditBase_ALL \
        EditFST_ALL EditPlace_ALL EditRoute_ALL EMCdisplay EMControl \
        EMControl_Float EMI_ALL expert expgen explorer Express \
4 y- }- L; v0 ?* `; C        ExpressPlus Extended_Digital_Body_Lib Extended_Verilog_Lib \
2 P9 U7 [! I! \! ~        fethman fetsetup FloatPC_ALL floorplan Framework \
  W& N* x& m. \$ h% R( B) t        fst_Usupuc_all FUNCTION_LIB gbom glib gloss gphysdly gscald \
1 N5 N6 ?  u. ?) S% l/ H/ K        gspares HDL-DESKTOP hp3070 HYB_USUPUC_ALL IC_autoroute_ALL \
        IC_device_place_ALL IC_devicegen_ALL"
+ q* I9 d0 Q( N- NPACKAGE EFA-CDS-04 cdslmd 2019.12 30801091DAE1B711FC58 \
        COMPONENTS="IC_deviceplace_ALL IC_edit_ALL IC_editfast_ALL \
        IC_gcell_route_ALL IC_hsrules_ALL IC_Inspector_ALL \
& l( z3 w# R7 L+ b; t7 g        IC_InspectorEngr IC_InspectorEngr_ALL IC_mp_route_ALL \
        IC_power_route_ALL IDF_Bi_Directional_Interface \
$ S( Z" n, I; U        iges_electrical intrgloss Intrica_powerplane_builder intrroute \
        intrsignoise IPB_4SUPUC_ALL IPB_USUPUC_ALL ipc_in ipc_out \
        IPlaceBase_ALL Layout LayoutEE LayoutEngEd LayoutPlus \
6 }8 U' b7 V$ w$ h9 _( p4 r        LEAPFROG-BV LEAPFROG-CV LEAPFROG-SLAVE LEAPFROG-SV \
8 r  t& F" a& ]2 K7 [# }# U        LEAPFROG-SYS LID11 LINEAR_LIB LSE lwb MAG_LIB MASTERTAG mdin \
        mdout mdtoac mdtocv"
0 V. z  ]3 p1 X" F7 SPACKAGE EFA-CDS-05 cdslmd 2019.12 709080B1B225997E86A8 \
! ], V# \, L# h  C' N$ h- |3 F0 ?        COMPONENTS="MIXAD_LIB modelIntegrity multiwire \
        NC_VHDL_Simulator NC_SystemC_Simulator Nihongoconcept \
        OpenModeler OpenModeler_SFI OpenModeler_SWIFT OpenSim \
        OpenWaves Optimizer OptimizerAA OrCAD OrCAD_Capture_CIS_option \
; E; }3 B+ `+ B) T6 D       
        PB_USUPUC_ALL PCB_design_expert PCB_design_studio PCB_designer \
        pcb_editor pcb_interactive PCB_librarian_expert pcb_prep \
        PCB_studio_variants pcomp PE_Librarian PlaceBase_ALL placement \
" w8 D8 R. Q/ I- N1 F        PlaceOrIPlace_ALL plotVersa PO1100 PO1110 PO1300 PO1310 PO1320 \
0 j5 J% X; C! ^; d1 n; A        PO1330"
PACKAGE EFA-CDS-06 cdslmd 2019.12 4030F0D1DDB23CB51B53 \
        COMPONENTS="PO1340 PO1400 PO1410 PO1420 PowerIntegrity \
$ k" C7 o: i" s! A. g  d( |2 r        PPRoute_ALL Prevail_Board_Designer Prevail_Designer PS2010 \
        PS2200 PS3010 PSpice PSpiceAA PSpiceAAOptimizer PSpiceAAStudio \
1 o/ q* b) k: k- z3 h        PSpiceAD PSpiceADAA PSpiceADStudio PSpiceBasics PSpiceStudio \
, J* I! G; u. @8 W        ptc_in ptc_out PWM_LIB PX3500 PX3710 PX3910 quanticout \
& P- m9 p& e  a        RapidPART rapidsim RB_4SUPUC_ALL RB_6SUPUC RB_6SUPUC_ALL \
4 K/ H5 K0 k4 s4 c        RB_USUPUC RB_USUPUC_ALL realchiplm RouteADV RouteADV_ALL \
; n' W. a9 t6 B# s3 }* e$ h        RouteBase RouteBase_ALL RouteDF"
6 [' M- b# H: v6 ^3 w. {PACKAGE EFA-CDS-07 cdslmd 2019.12 40F0106176E4BBB2D3D1 \
        COMPONENTS="RouteDFM_ALL RouteFST RouteFST_ALL RouteHYB_ALL \
3 V3 b$ x5 }# h! K+ i# J, ^        RouteMin_ALL RouteMVIA_ALL RouteOrEdit_ALL rt sdrc_in sdrc_out \
* A/ t& h3 L' m* O        shapefill signal_explorer signoise SigNoise_Float SigNoiseCS \
        SigNoiseEngineer SigNoiseStdDigLib Sigxp sigxp_explorer \
+ K+ h2 W" f' z' S* G        Sigxp_tier Sigxp_tier_EXPERT SimVision skillDev SPECCTRA_256U \
: ?6 d7 d8 J) t2 J2 \/ }3 |6 A        SPECCTRA_6U SPECCTRA_ADV SPECCTRA_APD SPECCTRA_autoroute \
! x/ c$ P/ X$ o0 ~" Z        SPECCTRA_autoroute_ALL SPECCTRA_autorouteEngr \
        SPECCTRA_designer SPECCTRA_designer_ALL SPECCTRA_designerEngr \
        SPECCTRA_DFM SPECCTRA_expert SPECCTRA_expert_ALL \
        SPECCTRA_expert_system SPECCTRA_expert_system_ALL \
' z5 f$ K  I7 Q# u( y* h! t9 c        SPECCTRA_expert_systemEngr SPECCTRA_expertEngr"
PACKAGE EFA-CDS-08 cdslmd 2019.12 4010E001C03C574EA29E \
        COMPONENTS="SPECCTRA_HP SPECCTRA_PCB SPECCTRA_PCB_ALL \
        SPECCTRA_PCBEngr SPECCTRA_performance SPECCTRA_performance_ALL \
        SPECCTRA_QE SPECCTRA_VT SPECCTRAQuest SPECCTRAQuest_expert \
( E: T; K3 H. F2 ~        SPECCTRAQuest_Planner SPECCTRAQuest_SI_expert \
        SPECCTRAQuest_signal_expert SPECCTRAQuest_signal_explorer \
1 @5 {' [6 W0 q3 q+ h9 Q        SQ_Digital_Logic_SI_Lib SQ_FPGA_SI_Lib SQ_Memory_SI_Lib \
        SQ_Microprocessor_SI_Lib stream_in stream_out StudioPSpiceAD \
        swap SWIFT sx Synlink_Interface Team_EFA tscr tune tw01 tw02 \
        UET ULMdelta ULMecho ULMhotel ULMindia ULMjuliette ULMmike \
        Unison_SPECCTRA_4U VB_4SUPUC_ALL VB_6SUPUC"
: w/ O% O" F6 M' E# `PACKAGE EFA-CDS-09 cdslmd 2019.12 B0800091DEDE2463C4D0 \
        COMPONENTS="VB_6SUPUC_ALL VB_USUPUC VB_USUPUC_ALL \
        VERILOG-SLAVE VERILOG-XL vgen VHDLLink viable ViewBase \
        ViewBase_ALL ViewBaseEngr ViewBaseEngr_ALL \
        Virtuoso_custom_router_ALL Virtuoso_custom_routerEngr \
        visula_in vloglink VXL-LMC-HW-IF VXL-TURBO VXL-VCW VXL-VET \
( P3 f$ ?% D5 p/ E2 |8 X        VXL-VLS VXL-VRA WinActel WinAltera WinAMDMACH WinAtmel \
        WinAutoRouteU WinCapture WinCaptureCIS WinDesignLab WinDevEqu \
7 t: S- D" O. \        WinEditRouteU WinExpress WinExpressPlus WinLayout WinLayoutEE \
        WinLayoutPlus WinMACHfiveVP WinMicroSim WinMinc"
PACKAGE EFA-CDS-10 cdslmd 2019.12 D0303001C3A577CFA14E \
        COMPONENTS="WinOptimizer WinOrCAD WinParts WinPCBoards WinPLD \
9 _) ^( Q5 i& N0 R8 s+ U( e        WinPLSyn WinPLSynPart WinProbe WinPSpice WinPSpiceAD WinStmEd \
        WinXilinx"
#
5 ]+ @& t3 {8 o# --------------------------------------------------------------------
#
INCREMENT EFA-CDS-01 cdslmd 2019.12 23-dec-2019 uncounted AD8107572717EEA50D97 "" ANY
$ o' |9 m" v( v, i1 B; |INCREMENT EFA-CDS-02 cdslmd 2019.12 23-dec-2019 uncounted AD9107572C17EEA50E92 "" ANY
INCREMENT EFA-CDS-03 cdslmd 2019.12 23-dec-2019 uncounted BDA107572D17EEA51F91 "" ANY
INCREMENT EFA-CDS-04 cdslmd 2019.12 23-dec-2019 uncounted BDB107572A17EEA52094 "" ANY
& M' I% D0 r+ A0 b1 b. r- JINCREMENT EFA-CDS-05 cdslmd 2019.12 23-dec-2019 uncounted BDC107572B17EEA52193 "" ANY
% p# ~! ~* K1 ?6 I# U6 X" UINCREMENT EFA-CDS-06 cdslmd 2019.12 23-dec-2019 uncounted BDD107572017EEA5229E "" ANY
INCREMENT EFA-CDS-07 cdslmd 2019.12 23-dec-2019 uncounted BDE107572117EEA5239D "" ANY
INCREMENT EFA-CDS-08 cdslmd 2019.12 23-dec-2019 uncounted ADF107572E17EEA51490 "" ANY
INCREMENT EFA-CDS-09 cdslmd 2019.12 23-dec-2019 uncounted BD0107572F17EEA5158F "" ANY
7 A( {1 M1 G/ c* m4 G1 lINCREMENT EFA-CDS-10 cdslmd 2019.12 23-dec-2019 uncounted AD810787261AEEA50D98 "" ANY
#
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#
#       License generated by Team EFA 2004 Keygen

great058

看License的日期刚好是2019.12 23

zg927

也是16.3精简版没碰到这个问题啊

great058

zg927 发表于 2020-1-7 12:11
也是16.3精简版没碰到这个问题啊

看你License的日期到期日期是什么时候？

zg927

great058 发表于 2020-1-7 18:29
& Y7 y2 |% L1 p看你License的日期到期日期是什么时候？

, E2 E3 L1 a6 l, I) W* T在哪看日期啊？
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great058

zg927 发表于 2020-1-9 15:16
在哪看日期啊？

7 _* a9 \5 ~! b- b& U( M用记事本打开License
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zg927

great058 发表于 2020-1-14 09:10
用记事本打开License

显示都是2010的日期
。。。。。。。。。
' N% \# o( B$ W9 L" O$ ^
4 T& C5 ?; z) B8 L; b* ]INCREMENT WinProbe cdslmd 16.0 31-dec-2010 uncounted \
        EDD703435562B757EC3C VENDOR_STRING=JERM HOSTID=ANY \
% S9 H/ G& S& ?5 C2 J3 }        ISSUER=Ghost/ZWT SN=2006-08-27T00:00:00:123 TS_OK \
        SIGN2=EDD703435562B757EC3C
INCREMENT WinDevEqu cdslmd 16.0 31-dec-2010 uncounted \
        6DD773933F6DB5A7595B VENDOR_STRING=JERM HOSTID=ANY \
+ E1 P. H. V/ [9 m# K/ g  i7 S        ISSUER=Ghost/ZWT SN=2006-08-27T00:00:00:123 TS_OK \
: O2 [& `. h; {        SIGN2=6DD773933F6DB5A7595B
INCREMENT WinDesignLab cdslmd 16.0 31-dec-2010 uncounted \
        5D8733638BE1778ECB36 VENDOR_STRING=JERM HOSTID=ANY \
        ISSUER=Ghost/ZWT SN=2006-08-27T00:00:00:123 TS_OK \
        SIGN2=5D8733638BE1778ECB36
INCREMENT WinMicroSim cdslmd 16.0 31-dec-2010 uncounted \
        3D7783A3AA631F31D9CD VENDOR_STRING=J:PERM HOSTID=ANY \
+ T5 t" K- B; U3 P* }' V        ISSUER=Ghost/ZWT SN=2006-08-27T00:00:00:123 TS_OK \
        SIGN2=3D7783A3AA631F31D9CD

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hubin6688

下载个cracklock软件，就可以使用了，可以百度下这个软件的使用教程