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DAEMON cdslmd c:\cdslmd.exe
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" U+ A! X L: B. s# Mendling with Feature lines will only invalidate them!
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8 G$ M: r! t" {PACKAGE EFA-CDS-01 cdslmd 2019.12 50D0C0F14EEEF46F0FE0 \
0 k- D0 N' M! j COMPONENTS="A2dxf ABIT actomd adv_package_designer_expert \+ x# X8 Y8 q! R7 S. y
adv_package_engineer_expert ADV_USUPUC_ALL \
$ r |7 f V: O- Q! ?7 n- h! ~ Advanced_Package_Designer Affirma_NC_Simulator \
# R0 Y5 V" d% e5 k Affirma_sim_analysis_env Affirma_transaction_analysis \
$ w; u9 V3 @( E2 Q- D" D/ Y Affirma_verification_cpit_rtim Allegro_CAD_Interface \, O4 m- L4 [5 E' [( I
Allegro_design_expert Allegro_Designer Allegro_designer_suite \
' Y1 Y4 w, u8 Y- A* G9 U4 V" b allegro_dfa allegro_dfa_att Allegro_Expert Allegro_Librarian \
4 h9 i9 U+ x- @( p ~ allegro_non_partner Allegro_PCB Allegro_PCB_Interface \
8 z& E+ i! g1 d Allegro_performance Allegro_studio Allegro_Symbol \
2 E' f/ m$ m/ X Allegro_Viewer_Plus allegroprance ANALOG_WORKBENCH APD \1 A1 ]+ M& \ Q' c/ R. ?) P
archiver arouter AWB_Batch AWB_BEHAVIOR AWB_DIST_SIM \
0 i( X: r2 c8 ^( p4 j AWB_MAGAZINE AWB_MAGNETICS AWB_MIX AWB_PPLOT AWB_RESOLV_OPT \2 Q2 p7 D$ N L. u; N) |3 z
AWB_RESOLVE_OPT"
& W; e7 |' G" _+ M- S" }PACKAGE EFA-CDS-02 cdslmd 2019.12 006030C10306920F9721 \8 s* _! q: n4 w4 d/ {) B$ a$ `
COMPONENTS="AWB_SIMULATOR AWB_SMOKE AWB_SPICEPLUS AWB_STATS \
( p( j" P: d. H7 P: M) ?/ H4 A AWBAA AWBSimulator Base_Digital_Body_Lib Base_Verilog_Lib \
/ q: f8 K. V( Y L5 B0 o- B8 t BOARDQUEST BoardQuest_Designer BoardQuest_Team BOGUS \
( `" w1 q- c+ r" k; h1 \& c0 e- t J Cadence_chip_assembly_rtr_ALL Cadence_chip_assembly_rtrEngr \
) o5 i6 P5 u( d! ^2 K+ F caeviews cals_out Capture Capture_CIS_Studio CaptureCIS \
2 l0 A# ]: n0 c cbds_in cdxe_in CHDL_DesignAccess CheckADV_ALL CheckFST_ALL \4 ?0 @* j! b; ~# i7 u
Checkplus_Expert CISoption comp Concept_HDL_expert \/ Z1 `9 A% Q" X6 Y7 }- V2 G) X
Concept_HDL_rules_checker Concept_HDL_studio ConceptHDL \4 x1 M. H$ c7 p; W+ l5 {
CP_Ele_Checks cpe crefer cvtomd CWAVES debug DFM_USUPUC_ALL \
$ l0 u4 ?! H" F7 g3 W1 k DISCRETE_LIB dracula_in"# n) ?. e2 B2 u3 `( d( E1 e
PACKAGE EFA-CDS-03 cdslmd 2019.12 40A0708139C03D1415F7 \. a/ Z% X& O1 L1 R5 c( }% |6 w8 s
COMPONENTS="dxf2a EB_4SUPUC_ALL EB_USUPUC_ALL eCapture \
9 _1 u& i; L9 r2 O EDIF_Netlist_Interface EDIF_Schematic_Interface EditBase_ALL \# o2 M+ E9 h( |2 i
EditFST_ALL EditPlace_ALL EditRoute_ALL EMCdisplay EMControl \& n( a" B. @+ u5 ?0 z: X
EMControl_Float EMI_ALL expert expgen explorer Express \
4 A4 \: b9 X) H* a ExpressPlus Extended_Digital_Body_Lib Extended_Verilog_Lib \; D0 X9 M4 k3 ^# V3 K
fethman fetsetup FloatPC_ALL floorplan Framework \* S1 X; `8 e2 }2 z8 J2 V
fst_Usupuc_all FUNCTION_LIB gbom glib gloss gphysdly gscald \6 |; d' q4 u3 k: ^: b' J1 a
gspares HDL-DESKTOP hp3070 HYB_USUPUC_ALL IC_autoroute_ALL \
, Z% N. f4 F x, q IC_device_place_ALL IC_devicegen_ALL"
& |& }+ T; e' d0 K) yPACKAGE EFA-CDS-04 cdslmd 2019.12 30801091DAE1B711FC58 \
! K7 Y: f7 D7 t COMPONENTS="IC_deviceplace_ALL IC_edit_ALL IC_editfast_ALL \
- [. \! q, H( u, e1 O IC_gcell_route_ALL IC_hsrules_ALL IC_Inspector_ALL \
$ z3 a" B; v; A" P' a IC_InspectorEngr IC_InspectorEngr_ALL IC_mp_route_ALL \
% u4 d& n( Z1 T IC_power_route_ALL IDF_Bi_Directional_Interface \
9 L% x/ {# S1 ~3 R iges_electrical intrgloss Intrica_powerplane_builder intrroute \
1 v6 A! e% V3 n intrsignoise IPB_4SUPUC_ALL IPB_USUPUC_ALL ipc_in ipc_out \; K$ w6 ^$ Q4 ~. `* J/ E% ? ^
IPlaceBase_ALL Layout LayoutEE LayoutEngEd LayoutPlus \
7 ~4 v' I) Y0 ~) Y LEAPFROG-BV LEAPFROG-CV LEAPFROG-SLAVE LEAPFROG-SV \
' j6 r+ H W! T& x1 X7 j2 i LEAPFROG-SYS LID11 LINEAR_LIB LSE lwb MAG_LIB MASTERTAG mdin \
) I0 S- V* o# I9 ?$ H; i& E mdout mdtoac mdtocv"
. H# K+ {! q# V. d* ~, P9 sPACKAGE EFA-CDS-05 cdslmd 2019.12 709080B1B225997E86A8 \
4 `% A8 T7 }2 r0 B COMPONENTS="MIXAD_LIB modelIntegrity multiwire \
- ]# Z& ^4 _6 m* u5 b NC_VHDL_Simulator NC_SystemC_Simulator Nihongoconcept \
, i0 q' b( D" c8 l: A OpenModeler OpenModeler_SFI OpenModeler_SWIFT OpenSim \ K$ A3 f7 f8 r i) N8 i0 m
OpenWaves Optimizer OptimizerAA OrCAD OrCAD_Capture_CIS_option \
4 e( }- E. {5 ?7 D/ ?. F, q; B) ? % B+ L( R r/ F U; S$ I
PB_USUPUC_ALL PCB_design_expert PCB_design_studio PCB_designer \
+ h5 o) `9 N+ G. B9 J8 w pcb_editor pcb_interactive PCB_librarian_expert pcb_prep \
9 B( {& V" ?8 G PCB_studio_variants pcomp PE_Librarian PlaceBase_ALL placement \ @# R$ r$ {$ q: `1 _
PlaceOrIPlace_ALL plotVersa PO1100 PO1110 PO1300 PO1310 PO1320 \
2 N) X! d; [6 G$ \ PO1330"9 @: z1 \* ?- ]5 L/ F, p; |
PACKAGE EFA-CDS-06 cdslmd 2019.12 4030F0D1DDB23CB51B53 \
* C% \4 v7 j: G9 A1 H1 ~ COMPONENTS="PO1340 PO1400 PO1410 PO1420 PowerIntegrity \
/ Q2 Y- M Y" Z PPRoute_ALL Prevail_Board_Designer Prevail_Designer PS2010 \6 J# A$ e2 z% C9 d
PS2200 PS3010 PSpice PSpiceAA PSpiceAAOptimizer PSpiceAAStudio \: J% ^! V$ q, H/ j k# h
PSpiceAD PSpiceADAA PSpiceADStudio PSpiceBasics PSpiceStudio \
. g3 P4 p* C, Q3 J) `2 G ptc_in ptc_out PWM_LIB PX3500 PX3710 PX3910 quanticout \
2 K2 } ^1 ^4 k7 X2 ^ RapidPART rapidsim RB_4SUPUC_ALL RB_6SUPUC RB_6SUPUC_ALL \
5 Y' \5 E( O: l$ X RB_USUPUC RB_USUPUC_ALL realchiplm RouteADV RouteADV_ALL \
8 ~ B5 D& k0 F9 L \6 n RouteBase RouteBase_ALL RouteDF"& N. p. W8 U- s4 L5 _; H' R
PACKAGE EFA-CDS-07 cdslmd 2019.12 40F0106176E4BBB2D3D1 \- f; H7 e; d; c% T' z
COMPONENTS="RouteDFM_ALL RouteFST RouteFST_ALL RouteHYB_ALL \* O. Q7 E% G8 P3 S) f& D* Q
RouteMin_ALL RouteMVIA_ALL RouteOrEdit_ALL rt sdrc_in sdrc_out \* p! f5 R! D; Q4 |1 V. k
shapefill signal_explorer signoise SigNoise_Float SigNoiseCS \& m% E4 S, F6 X4 Z6 x4 {! C; b l+ i
SigNoiseEngineer SigNoiseStdDigLib Sigxp sigxp_explorer \/ g# ~0 ~ ?# E4 m3 p4 J8 P" x
Sigxp_tier Sigxp_tier_EXPERT SimVision skillDev SPECCTRA_256U \5 H3 \& k& x: T/ w: D) P1 G2 f
SPECCTRA_6U SPECCTRA_ADV SPECCTRA_APD SPECCTRA_autoroute \
! D W* p! g- F3 Q! _ SPECCTRA_autoroute_ALL SPECCTRA_autorouteEngr \/ T0 L) @- \' P( B% T" D, Y
SPECCTRA_designer SPECCTRA_designer_ALL SPECCTRA_designerEngr \
6 @% M" D( O5 u; h; |. q* I V& q- p \: x SPECCTRA_DFM SPECCTRA_expert SPECCTRA_expert_ALL \
, g3 M% a: w( N, W SPECCTRA_expert_system SPECCTRA_expert_system_ALL \
4 K- U0 @# T$ b3 \5 H+ n SPECCTRA_expert_systemEngr SPECCTRA_expertEngr"
( p* h7 V; b3 W& v$ wPACKAGE EFA-CDS-08 cdslmd 2019.12 4010E001C03C574EA29E \
0 l/ j, h; b4 D3 f, ~, N: i' Z COMPONENTS="SPECCTRA_HP SPECCTRA_PCB SPECCTRA_PCB_ALL \5 o3 w5 z- W M" M
SPECCTRA_PCBEngr SPECCTRA_performance SPECCTRA_performance_ALL \- e, F% g2 t$ z; W6 m; d: M5 j
SPECCTRA_QE SPECCTRA_VT SPECCTRAQuest SPECCTRAQuest_expert \1 M% n, N0 F) F1 X6 l, h8 R
SPECCTRAQuest_Planner SPECCTRAQuest_SI_expert \
6 ?, P4 r5 T Z# b9 V6 O# Z SPECCTRAQuest_signal_expert SPECCTRAQuest_signal_explorer \
4 v( ^. `, x2 K4 A. I SQ_Digital_Logic_SI_Lib SQ_FPGA_SI_Lib SQ_Memory_SI_Lib \
: W3 C( x) k& P SQ_Microprocessor_SI_Lib stream_in stream_out StudioPSpiceAD \- |( d" w# U1 N
swap SWIFT sx Synlink_Interface Team_EFA tscr tune tw01 tw02 \
# Q8 @& l1 }8 B* ]3 m- ^6 F UET ULMdelta ULMecho ULMhotel ULMindia ULMjuliette ULMmike \
* Y |# q( B! G+ ? Unison_SPECCTRA_4U VB_4SUPUC_ALL VB_6SUPUC"2 q' `8 {& C* `' R3 a. u0 R/ X4 ]8 [
PACKAGE EFA-CDS-09 cdslmd 2019.12 B0800091DEDE2463C4D0 \
- w) s1 v1 X j+ P/ s' ^ COMPONENTS="VB_6SUPUC_ALL VB_USUPUC VB_USUPUC_ALL \7 {4 g! ~! I& F& j2 U8 x
VERILOG-SLAVE VERILOG-XL vgen VHDLLink viable ViewBase \
1 y$ A3 v( s$ i; ^2 D ViewBase_ALL ViewBaseEngr ViewBaseEngr_ALL \& s4 M1 o( F' I* S% ~# i
Virtuoso_custom_router_ALL Virtuoso_custom_routerEngr \: {/ p, O' s* X4 u$ |
visula_in vloglink VXL-LMC-HW-IF VXL-TURBO VXL-VCW VXL-VET \
. N$ v+ x6 [& q VXL-VLS VXL-VRA WinActel WinAltera WinAMDMACH WinAtmel \
6 y; K$ Y8 |0 A! R8 y( l! X4 C WinAutoRouteU WinCapture WinCaptureCIS WinDesignLab WinDevEqu \
2 E& r6 a* F9 i WinEditRouteU WinExpress WinExpressPlus WinLayout WinLayoutEE \
3 I4 w- F2 P! ~9 t- R WinLayoutPlus WinMACHfiveVP WinMicroSim WinMinc"7 Y/ g0 c0 @# b6 T' y: @' C( K1 |
PACKAGE EFA-CDS-10 cdslmd 2019.12 D0303001C3A577CFA14E \
' O8 o2 k" }2 e. f q: O COMPONENTS="WinOptimizer WinOrCAD WinParts WinPCBoards WinPLD \( ~- U( F. O: g0 i/ a/ D$ ?9 N' p
WinPLSyn WinPLSynPart WinProbe WinPSpice WinPSpiceAD WinStmEd \
8 ^: N: Y$ S+ E* V$ X. ` WinXilinx"/ E: u3 T6 r+ r1 \
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INCREMENT EFA-CDS-01 cdslmd 2019.12 23-dec-2019 uncounted AD8107572717EEA50D97 "" ANY2 h( r5 Y: j0 ]0 H# _: Y
INCREMENT EFA-CDS-02 cdslmd 2019.12 23-dec-2019 uncounted AD9107572C17EEA50E92 "" ANY. ~9 M/ M3 U+ A1 b+ s, B" V& y% H
INCREMENT EFA-CDS-03 cdslmd 2019.12 23-dec-2019 uncounted BDA107572D17EEA51F91 "" ANY
2 B: u* Z# v7 ~, ~2 ?" tINCREMENT EFA-CDS-04 cdslmd 2019.12 23-dec-2019 uncounted BDB107572A17EEA52094 "" ANY+ y( f x6 u& W0 e# q0 a: r! H
INCREMENT EFA-CDS-05 cdslmd 2019.12 23-dec-2019 uncounted BDC107572B17EEA52193 "" ANY3 D5 k/ w3 v* U, T
INCREMENT EFA-CDS-06 cdslmd 2019.12 23-dec-2019 uncounted BDD107572017EEA5229E "" ANY
8 v) t3 [* C8 ^) h j# cINCREMENT EFA-CDS-07 cdslmd 2019.12 23-dec-2019 uncounted BDE107572117EEA5239D "" ANY
2 T% c; P4 n) l* w4 M. z. oINCREMENT EFA-CDS-08 cdslmd 2019.12 23-dec-2019 uncounted ADF107572E17EEA51490 "" ANY
1 N0 z6 `7 O$ i7 ]; cINCREMENT EFA-CDS-09 cdslmd 2019.12 23-dec-2019 uncounted BD0107572F17EEA5158F "" ANY
: Z6 k1 G: r& ]7 V$ y, q# ^8 e5 y0 e6 nINCREMENT EFA-CDS-10 cdslmd 2019.12 23-dec-2019 uncounted AD810787261AEEA50D98 "" ANY% H0 T# N; D; }
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2 O: {4 G5 F1 \+ N5 p# License generated by Team EFA 2004 Keygen
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