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DAEMON cdslmd c:\cdslmd.exe
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" {/ C i( x0 R# License for Cadence PSD Series
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3 {/ Z- [& S2 Y5 j# Generated especially for' Y' }" _2 Q8 M; @, k5 }, s! s4 C. D3 Q
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+ U" A. {& J+ O4 ] n. TPACKAGE EFA-CDS-01 cdslmd 2019.12 50D0C0F14EEEF46F0FE0 \7 B$ g( L- h0 N! c1 m4 o( T
COMPONENTS="A2dxf ABIT actomd adv_package_designer_expert \1 v$ w- v" z9 E* t: o# M
adv_package_engineer_expert ADV_USUPUC_ALL \
, v+ d" c' Q( R* X8 S7 a Advanced_Package_Designer Affirma_NC_Simulator \
5 P0 K5 Q* H+ Y Affirma_sim_analysis_env Affirma_transaction_analysis \
5 d5 ]( A4 t" I; P/ c, X( r9 z X! O- Z- P Affirma_verification_cpit_rtim Allegro_CAD_Interface \/ I/ Y( h; A$ z
Allegro_design_expert Allegro_Designer Allegro_designer_suite \
% y) {8 e, k( g4 T9 Z3 a, R, [) z allegro_dfa allegro_dfa_att Allegro_Expert Allegro_Librarian \8 O3 ]6 m# v+ L
allegro_non_partner Allegro_PCB Allegro_PCB_Interface \! K5 u1 e9 l: w8 m) Z1 p5 q) G( g
Allegro_performance Allegro_studio Allegro_Symbol \4 T7 w+ H8 t9 M% Q, ]0 J
Allegro_Viewer_Plus allegroprance ANALOG_WORKBENCH APD \7 t' p# K- w- `$ l6 Y
archiver arouter AWB_Batch AWB_BEHAVIOR AWB_DIST_SIM \
7 [+ t" e5 L5 q1 I, L AWB_MAGAZINE AWB_MAGNETICS AWB_MIX AWB_PPLOT AWB_RESOLV_OPT \* F( {% l0 F6 X2 ], U) G% R8 }
AWB_RESOLVE_OPT" M& n9 P3 T: a
PACKAGE EFA-CDS-02 cdslmd 2019.12 006030C10306920F9721 \
- Q/ `$ T; r7 t COMPONENTS="AWB_SIMULATOR AWB_SMOKE AWB_SPICEPLUS AWB_STATS \# X0 c& w* e# ? o1 Q: F: A4 ?
AWBAA AWBSimulator Base_Digital_Body_Lib Base_Verilog_Lib \8 j/ |5 C! u" A& T( v
BOARDQUEST BoardQuest_Designer BoardQuest_Team BOGUS \
f6 |+ p8 l, ^2 ]' O$ _' ] Cadence_chip_assembly_rtr_ALL Cadence_chip_assembly_rtrEngr \9 A, j( i6 h% W8 @
caeviews cals_out Capture Capture_CIS_Studio CaptureCIS \
0 L( s$ X" H6 T F% V/ g! \ cbds_in cdxe_in CHDL_DesignAccess CheckADV_ALL CheckFST_ALL \
7 N# z- F! ~2 V# D% p Checkplus_Expert CISoption comp Concept_HDL_expert \
; J3 g6 _$ n$ b9 f9 g4 s& j Concept_HDL_rules_checker Concept_HDL_studio ConceptHDL \1 m4 }$ Q8 U+ _! N2 \2 G
CP_Ele_Checks cpe crefer cvtomd CWAVES debug DFM_USUPUC_ALL \# I6 V9 n" G; l9 B' T3 d( A" ]3 L" p
DISCRETE_LIB dracula_in"# ?$ ?! D8 ^6 I* I3 X! `
PACKAGE EFA-CDS-03 cdslmd 2019.12 40A0708139C03D1415F7 \
) V, A R' }+ v- O/ I COMPONENTS="dxf2a EB_4SUPUC_ALL EB_USUPUC_ALL eCapture \" H/ ]$ O$ C' k$ l, w! b4 x
EDIF_Netlist_Interface EDIF_Schematic_Interface EditBase_ALL \
/ d0 c5 J4 f2 b0 B5 P3 P: M; B EditFST_ALL EditPlace_ALL EditRoute_ALL EMCdisplay EMControl \
% S' Q, ]- p: q! `' x! f EMControl_Float EMI_ALL expert expgen explorer Express \
) ~8 [7 B, M* C% V- ?$ q1 L ExpressPlus Extended_Digital_Body_Lib Extended_Verilog_Lib \
! F* s: N* d( D fethman fetsetup FloatPC_ALL floorplan Framework \
! \; p4 o- C! R fst_Usupuc_all FUNCTION_LIB gbom glib gloss gphysdly gscald \% |# g `- r5 B! u# Q
gspares HDL-DESKTOP hp3070 HYB_USUPUC_ALL IC_autoroute_ALL \: Q Y( ^9 {1 B0 ?0 l9 I: H
IC_device_place_ALL IC_devicegen_ALL"
4 e8 T& k- b3 N0 {0 b8 qPACKAGE EFA-CDS-04 cdslmd 2019.12 30801091DAE1B711FC58 \* i' F- p6 L/ n/ e: \
COMPONENTS="IC_deviceplace_ALL IC_edit_ALL IC_editfast_ALL \
2 @- @5 l" I9 P* i: V: N: A2 } IC_gcell_route_ALL IC_hsrules_ALL IC_Inspector_ALL \0 L3 ` m# |0 V3 V* Y1 z/ t
IC_InspectorEngr IC_InspectorEngr_ALL IC_mp_route_ALL \4 h" o4 X5 j' I5 R7 `% O
IC_power_route_ALL IDF_Bi_Directional_Interface \
7 ?9 k9 x) J* V+ _2 ]) k* m8 Y. X iges_electrical intrgloss Intrica_powerplane_builder intrroute \; a* E4 R) |* v X+ G, L4 p) D9 h
intrsignoise IPB_4SUPUC_ALL IPB_USUPUC_ALL ipc_in ipc_out \( I) b9 [$ s+ m0 b: t& \
IPlaceBase_ALL Layout LayoutEE LayoutEngEd LayoutPlus \
% ^2 S- J c* K- |6 x o LEAPFROG-BV LEAPFROG-CV LEAPFROG-SLAVE LEAPFROG-SV \
& e9 ^* E0 J% Q: K1 l Z7 {- {& n LEAPFROG-SYS LID11 LINEAR_LIB LSE lwb MAG_LIB MASTERTAG mdin \7 T4 W1 s% s( S/ E- p2 R
mdout mdtoac mdtocv"+ Q- s9 L& J$ i3 b) E
PACKAGE EFA-CDS-05 cdslmd 2019.12 709080B1B225997E86A8 \
. c7 w: g* ~' h, q3 ` COMPONENTS="MIXAD_LIB modelIntegrity multiwire \
3 C5 T6 X% o, d I! p NC_VHDL_Simulator NC_SystemC_Simulator Nihongoconcept \3 F1 _$ d9 p( p
OpenModeler OpenModeler_SFI OpenModeler_SWIFT OpenSim \
: a/ j4 t% X1 p- x' Q! Z5 ` OpenWaves Optimizer OptimizerAA OrCAD OrCAD_Capture_CIS_option \
+ x3 C0 U, _$ t% d) }9 Y( q; r
0 v# z; M8 T5 ]- g! X" Y PB_USUPUC_ALL PCB_design_expert PCB_design_studio PCB_designer \6 L/ r/ F" O* r+ [' K
pcb_editor pcb_interactive PCB_librarian_expert pcb_prep \7 n1 g6 p2 x t( M* h6 G: Q6 l! p8 [
PCB_studio_variants pcomp PE_Librarian PlaceBase_ALL placement \
' H) K6 B& R6 K7 v D, K PlaceOrIPlace_ALL plotVersa PO1100 PO1110 PO1300 PO1310 PO1320 \ Q# _( o7 ^+ M7 `' f. Q+ l
PO1330"
! O7 ]% T3 l5 M* G" t) v( oPACKAGE EFA-CDS-06 cdslmd 2019.12 4030F0D1DDB23CB51B53 \
8 x6 M( a0 }! e$ ^6 f7 }, d4 z COMPONENTS="PO1340 PO1400 PO1410 PO1420 PowerIntegrity \
! j) u1 H+ E& T: x( V9 V5 ^- M PPRoute_ALL Prevail_Board_Designer Prevail_Designer PS2010 \# X, m/ o. U, e5 A' [
PS2200 PS3010 PSpice PSpiceAA PSpiceAAOptimizer PSpiceAAStudio \2 a; w7 K( O, Q) b1 X
PSpiceAD PSpiceADAA PSpiceADStudio PSpiceBasics PSpiceStudio \6 b/ [! D/ P3 ~+ H4 s* A
ptc_in ptc_out PWM_LIB PX3500 PX3710 PX3910 quanticout \/ G) D x+ {! E1 f4 {8 U3 C- T
RapidPART rapidsim RB_4SUPUC_ALL RB_6SUPUC RB_6SUPUC_ALL \. I" ^+ x4 @& {# s. e
RB_USUPUC RB_USUPUC_ALL realchiplm RouteADV RouteADV_ALL \9 v# e: m/ [1 Q" G# @; `
RouteBase RouteBase_ALL RouteDF"
( ?& [2 V$ R ~- b% IPACKAGE EFA-CDS-07 cdslmd 2019.12 40F0106176E4BBB2D3D1 \
6 `" T8 W# c! B6 _8 L# @ COMPONENTS="RouteDFM_ALL RouteFST RouteFST_ALL RouteHYB_ALL \
; Z8 s+ M* |; `4 A RouteMin_ALL RouteMVIA_ALL RouteOrEdit_ALL rt sdrc_in sdrc_out \( X: L, h2 R8 G, ]! r
shapefill signal_explorer signoise SigNoise_Float SigNoiseCS \/ Z2 p6 H: c( O$ ]# }/ q' d
SigNoiseEngineer SigNoiseStdDigLib Sigxp sigxp_explorer \
. J$ D: I& i- X5 J! J7 m. p5 w Sigxp_tier Sigxp_tier_EXPERT SimVision skillDev SPECCTRA_256U \; o6 y6 o# a7 c" f9 y- Q
SPECCTRA_6U SPECCTRA_ADV SPECCTRA_APD SPECCTRA_autoroute \
3 A; e, C; q1 _. H: p0 p9 N! P SPECCTRA_autoroute_ALL SPECCTRA_autorouteEngr \
& u" b$ r' S( p C, | SPECCTRA_designer SPECCTRA_designer_ALL SPECCTRA_designerEngr \8 g8 h1 ?8 O+ ?" ^4 _, a) u
SPECCTRA_DFM SPECCTRA_expert SPECCTRA_expert_ALL \) l- i" D) |9 R% j2 D2 ^) Z- A
SPECCTRA_expert_system SPECCTRA_expert_system_ALL \2 O7 ~' {: w! o2 y8 p7 _# a
SPECCTRA_expert_systemEngr SPECCTRA_expertEngr"; E. q: p) v5 U+ Y
PACKAGE EFA-CDS-08 cdslmd 2019.12 4010E001C03C574EA29E \/ w& w% c" {: L+ F! b+ `
COMPONENTS="SPECCTRA_HP SPECCTRA_PCB SPECCTRA_PCB_ALL \
' u8 k; A; R! l' z SPECCTRA_PCBEngr SPECCTRA_performance SPECCTRA_performance_ALL \, n; i2 x4 u1 W2 F
SPECCTRA_QE SPECCTRA_VT SPECCTRAQuest SPECCTRAQuest_expert \
/ y3 k9 p% M/ l u: V6 V SPECCTRAQuest_Planner SPECCTRAQuest_SI_expert \
% h$ q- ~; X: O SPECCTRAQuest_signal_expert SPECCTRAQuest_signal_explorer \
& l- T% |. g; q SQ_Digital_Logic_SI_Lib SQ_FPGA_SI_Lib SQ_Memory_SI_Lib \9 M8 J. k7 S K
SQ_Microprocessor_SI_Lib stream_in stream_out StudioPSpiceAD \
; T" ^- t! \) w7 g: p1 j6 K swap SWIFT sx Synlink_Interface Team_EFA tscr tune tw01 tw02 \$ l+ A# V9 q) A% B) i
UET ULMdelta ULMecho ULMhotel ULMindia ULMjuliette ULMmike \
. S, O1 z: ^/ q* l8 q4 D, p5 e Unison_SPECCTRA_4U VB_4SUPUC_ALL VB_6SUPUC"
( @: @( a) }8 P0 G- t0 T+ fPACKAGE EFA-CDS-09 cdslmd 2019.12 B0800091DEDE2463C4D0 \7 @% d) L1 B+ z @0 ?
COMPONENTS="VB_6SUPUC_ALL VB_USUPUC VB_USUPUC_ALL \3 u+ W) d8 f8 Q& [$ J. @1 E3 X# o( n
VERILOG-SLAVE VERILOG-XL vgen VHDLLink viable ViewBase \
$ e& M2 `' y7 O ViewBase_ALL ViewBaseEngr ViewBaseEngr_ALL \: E3 N$ _0 t: [5 z0 [, d- r9 H
Virtuoso_custom_router_ALL Virtuoso_custom_routerEngr \
. A% {" y4 i' A; S8 j visula_in vloglink VXL-LMC-HW-IF VXL-TURBO VXL-VCW VXL-VET \( r* h* c5 Q1 u+ Q, A
VXL-VLS VXL-VRA WinActel WinAltera WinAMDMACH WinAtmel \/ o+ F, h F; e# c
WinAutoRouteU WinCapture WinCaptureCIS WinDesignLab WinDevEqu \
2 z: W" j+ e2 z) z2 B1 J2 t$ c3 l: Q WinEditRouteU WinExpress WinExpressPlus WinLayout WinLayoutEE \
8 A% Z2 F9 r" F6 ~$ k1 l WinLayoutPlus WinMACHfiveVP WinMicroSim WinMinc"6 R: U% D$ W% u$ k8 ?- p& X% \
PACKAGE EFA-CDS-10 cdslmd 2019.12 D0303001C3A577CFA14E \
3 y+ f, V4 t$ _6 i0 z COMPONENTS="WinOptimizer WinOrCAD WinParts WinPCBoards WinPLD \8 d* x& t3 c7 ?
WinPLSyn WinPLSynPart WinProbe WinPSpice WinPSpiceAD WinStmEd \
/ c! d5 c8 k, I6 F; W1 b' r* U) l* ^ WinXilinx"( t' S7 x- S3 Q6 c& k) F; v) ^
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INCREMENT EFA-CDS-02 cdslmd 2019.12 23-dec-2019 uncounted AD9107572C17EEA50E92 "" ANY9 N& w( x8 h+ }$ C ? E" k
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INCREMENT EFA-CDS-07 cdslmd 2019.12 23-dec-2019 uncounted BDE107572117EEA5239D "" ANY
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INCREMENT EFA-CDS-09 cdslmd 2019.12 23-dec-2019 uncounted BD0107572F17EEA5158F "" ANY
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