一个OrCAD与Allegro的问题

Dandy_15 · 发表于 2009-9-24 13:10

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一个很多人多会见到的问题，也很好解决，但想弄明白，所以想与大家讨论一下！一、PIN 如果Type为POWER，则可以重名，很好理解，但是问题在后面，如果将Pin Visible 选上，问题就来了，在生成NETLIST时，系统不提示错误，可以生产，但会有Warning,如Warning[ALG0051] Pin "GND" is renamed to "GND#21" after substituting illegal characters in Package MEGA88VS，如果不选中Pin Visible ，就不点问题也没有。不知道为什么。如果不选中Pin Visible，看到不引脚名，就更容易出错，特点是在多电源系统里。当然用GND#1,GND#2这样的方法可以解决，但总觉得不好，都是GND，还分什么1呀2的，而且这样花的时间也多，要多打几个字，占的空间也多，不好排版。看过几家大的公司，有的分了1，2，3，有的就没分，就全部是GND，不知道他们是怎么做的，还是不理会这些Warning！二、还有一个问题就有，Value，Part，Footprint,还有NET，PIN NAME的长度问题，cadence的文档中讲的是不能超过30个字符（有的资料是31），但在其实中是Value，Part，Footprint加起来不能超过29[31-2（两个_连接符）]个，实际的操作中很容易超过29个字符，经常要做这方面的处理，虽然只是给出Warning，不影响正确性，但总觉得不爽。不知道大家有没有这样的问题，是怎么解决的！谢谢

Dandy_15 · 发表于 2009-9-24 13:12

ADM是分开了的，用GND_1,GND_2进行区分，Type还是Passive，不知道这样算不算不规范！

numbdemon · 发表于 2009-9-25 17:09

这个没什么规范，达成共识就可以了。
警告的内容可以忽略。

不需要追求完美，关键就是网表不出错，电气连接不出错，制造的电路板不出错。
抓住重点就好

Dandy_15 · 发表于 2009-9-25 21:51

谢谢numbdemon 的指点，有些问题还是弄明白的好。
以下我查到的资料，供大家讨论。
在网上查了半天的资料，还是没解决的方案，
看下面国外的论坛：http://www.edaboard.com/ftopic186601.html
WHEN I TRY TO create netlist in Capture CIS the flowing masseg appear,

#170 Warning [ALG0051] Pin "VSS" is renamed to "VSS#K5" after substituting illegal characters in Package G24V-3_7N , U0D1A: DSP - G24, Pg 17,20 - DSP - AFE IO (0.50, 0.90).

- the pin type = Power
- Pin name = VSS
- Connected to Net = GND_SIGNAL

i try to rename the pin to GND_SIGNAL but masseg still appears.
Hi

Check your ECR matrix, it will take off the warning/error message. You have to be very cautious while setting that.

The warning is to indicate that your "VSS" (Power) is getting short to "GND_SIGNAL". Also modify it to "AGND/DGND/GND".

The above two method should solve your problem.

Centiago

再看一下OrCAD官方论坛:http://www.chronology.com/forums/ShowPost.aspx?PostID=12807

illegal characters in schematic symbol???

All:

When generating the netlist, the following Warings occur:

#92 Warning [ALG0051] Pin "GND" is renamed to "GND#9" after substituting illegal characters in Package LT1765EFE
#99 Warning [ALG0051] Pin "Vss" is renamed to "VSS#34" after substituting illegal characters in Package IDT71016S ,
#79 Warning [ALG0051] Pin "VCC" is renamed to "VCC#1" after substituting illegal characters in Package H8S2168AA
#89 Warning [ALG0051] Pin "VIN" is renamed to "VIN#3" after substituting illegal characters in Package LT1765EFE

I very puzzled, and it seems that, GND, VSS, VCC, VIN are all illegal pin name in schmatic symbol, so tool rename them. Which names are illegal when creating schamtic symbl? I dont see any docs.
Maybe this problem is caused by same name in one schematic symbol, but I have set these pins with same name to "POWER" property. Previously, it is allowed same name if the pin property is power.

Thanks
Peter

You didn't say which netlister you were using but by the error msgs it looks like Allegro. You may have to consult the Allegro documentation to see if it objects to duplicate pin names. As an alternative, check the netlist itself -perhaps these pins are still connected to correct nets by pin number with pin name as a reference only ?

Ron O.

Dandy_15 · 发表于 2009-9-25 21:52

最后看了一下Candence的Help文件，是这么说：
Pin Bubbles
Use the BUBBLE and BUBBLE_GROUP properties for tracking and checking signal states and circuit behavior. The pins need to be bubbled correctly

while they are being designed in Design Entry HDL. Symbols that are built correctly should not cause any problems and should successfully

complete the design integrity checks within Design Entry HDL. These properties also provide for much more readable designs when looked at

logically.
Cadence libraries include the DeMorgan equivalent parts as alternate symbol versions. When placing parts, the correct symbol should be used to

establish signal states and to provide design integrity. You can use the bubble command in Design Entry HDL to toggle the signal states on pins.

Pin Types
Designate the pin types and add pin loading information in Part Developer. This information gets stored in the chips.prt file and is crucial for

some Design Entry HDL integrity checks and layout analysis with SigNoise. Signal noise analysis uses the pin type and loading information to

accurately model the behavior of components.
The information can also be input manually into the chips.prt file by using a text editor. However, this requires you to be aware of the syntax

and file format.
Whenever appropriate the input pins should be placed on the left side of the symbol with outputs on the right.

Pin Naming
Pins should be designated with functional names. Each pin name must be unique to that symbol and must have a matching entry in the chips.prt

file. Typically, a pin name must be alphanumeric, but you can have numbers as pin names for scalar pins. The other characters that are supported

by Design Entry HDL as valid characters in pin names are as follows:
-
#
$
%
+
=
|
?
^
_
.
(
)

For pins that have ( or ) in their names, hlibftb reports errors if you run verification checks from within Part Developer. However, you can use

such pins in Design Entry HDL schematics by turning off the multi_format_vector option. Because of this reason, it is suggested that you do not

use ( or ) in pin names.

The following are not valid for pin names:
All extended character sets
/
;
!
<
>
:
\
"
,
*
When creating parts manually, place the SIG_NAME properties outside the symbol, next to the pin it is attached to. Text size is not too

important on these properties since they are not displayed on the schematic.
Follow low asserted pin names with an asterisk (*) (for example, OE*) or _N (for example OE_N). Do not differentiate low asserted pins with any

other nomenclature. All low asserted pins should appear as bubbles and not straight pin stubs.
设为Power可重名只是OrCAD的规定，那是OrCAD公司的规则，便Candence却不认同，Allegro是不准同名的，只要同名就有Warning,再看看Allegro的NETLIST，
'GND'
'@SR888.SCHEMATIC1(SCH_1):GND':
C_SIGNAL='@sr888.schematic1(sch_1):gnd';
NODE_NAME U2 3
'@SR888.SCHEMATIC1(SCH_1):INS1860963@MY LIBRARY.MEGA88VS.NORMAL(CHIPS)':
'GND#3':;
NODE_NAME U2 5
'@SR888.SCHEMATIC1(SCH_1):INS1860963@MY LIBRARY.MEGA88VS.NORMAL(CHIPS)':
'GND#5':;
这才明白，Allegro的NETLIST中pin name的信息，这样能重名吗？
再看看PADS的netlist:
*NET*
*SIGNAL* GND
U6.12 R14.2 R13.2 J6.10 J6.8 J6.6 U6.10 D10.2
D16.1 D15.1 U6.13 D17.1 J6.3 C8.2 C16.2 U2.5
C20.2 U2.3 C15.2 U6.5 C18.2 U5.3 U2.21 U4.3
C17.2 C25.2 C22.2 C6.1 C21.2 D8.2 J6.4 D18.1
U6.1 C19.2 C7.1 D4.1 D9.2 C24.2 D12.2 U6.11
D11.2 C23.2 J1.2 J1.4 MH13.1 MH12.1 MH6.1 C27.2
MH9.1 C29.2 MH5.1 J5.5 C30.2 C10.2 C31.2 C11.1
P2.5 J5.6 U7.7 C3.2 C26.2 C1.2 C2.2 U3.15
P2.10 C4.2 C28.2 J4.13 P1.5 C5.2 U1.2 C14.2
C9.2 J4.15 P1.10 P1.11 MH10.1 P2.11 MH8.1 U7.3
这样，没用pin name信息，当然可以重名了！

看来，没什么好想的，只能用#1,#2,#3来区分了，这样就知道是同一个地上的不同引脚，如果用1，2，3来分的话，不怎么好，DATA1,DATA2,DATA3，它也是用1，2，3来分的，名子也都是data，但不是同一网络。

Dandy_15 · 发表于 2009-9-25 22:01

这个没什么规范，达成共识就可以了。0 F8 h4 h \5 [- l+ ^ q
警告的内容可以忽略。
; A. H, p. e$ Q' O9 G0 H
% n% L& U* g2 W' p+ v不需要追求完美，关键就是网表不出错，电气连接不出错，制造的电路板不出错。/ I; G* b$ e5 J6 d, U1 t
抓住重点就好3 Q3 ]' l7 @" p; Z7 ]
numbdemon 发表于 2009-9-25 17:09

如果没有规范的要求，就很难达成共识，有的在一个公司，大家这么规定还可以，但是到了别一个公司，又是另一种共识，请问这样的共识有用吗？而且没有统一的要求，是很难达成共识的。

Dandy_15 · 发表于 2009-9-25 22:09

3# numbdemon
其实定义Type是很在必要的，且在后期这个属性是会传到Allegro中的，allegro对pin Type有很严格的要求，在仿真的时候都用得上.

numbdemon · 发表于 2009-9-28 11:49

5# Dandy_15
1.Pin Name信息并非网表需要关注的主要信息，真正关系到电气连接的是pin number，所以仅从这一点出发，对于电源引脚命名为相同名字还是不同的名字，可以随便选择。当然软件本身会阻止你使用错误的命名方法(把非电源类型的引脚命名相同的名称)。
2.OrCAD原本只是Cadence公司半路购买来的产品，它与Allegro的配合并不是最默契的(最默契的要属concept，即HDL)，所以有些瑕疵也是在所难免的。关于pin name的警告完全可以忽略。因为实质上它不会影响到电气连接。
3.关于pin type，由于在allegro进行相关仿真时有它自己的一套设置和配置方法，在OrCAD绘图时，不必要考虑。而且如果不能保证考虑完全正确，就会造成无用功，浪费工作时间和效率。所以一般的设计流程中可以不考虑pin type。除非你需要在OrCAD中使用Pspice仿真。

当然上述只是我个人意见，如果公司有自己的要求和规范，工作中还是要遵守的。但是心里要明白原理图设计的最重要目标是保证电气连接。

yangjijun · 发表于 2009-10-20 20:10

严格的来说GND_1,GND_2.....都来表示GND的确超级不爽,给人的感觉是有3种地网络,都是CADENE把别人的ORCAD乱改惹的祸

Dandy_15 · 发表于 2009-10-26 08:14

8# numbdemon
我个人觉得，如果画原理图是一个人，画PCB是一个人，做SI仿真又是一个人的话，如果各管各的，你讲得可能比较实用，如果考虑到整个项目的话，有些工作在前面做比在后面可能会更好，毕竟做原理图对整个电路更了解些，以上只是人个观点，不对之处，还请指正。

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