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装完还是显示052
& M3 i- U5 n* {* ^Fixed CCRs: SPB 17.2 HF053* A3 k& l* W S
03-01-2019
6 R7 S7 K& X z0 j! M========================================================================================================================================================2 u. E* W* w- g) }4 `
CCRID Product ProductLevel2 Title
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2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right
7 e, r: ^% k3 s) m! A2 C2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag$ C2 r3 h/ v; r$ A' L- ~
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
2 j! p5 S2 q& w& _* ^2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design- q# s$ ~* t) b: j7 H8 A
2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error
# i. T# t7 q/ i5 e2 | H2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
: j; p5 F- R/ ` F( j; C2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer
4 \' y" h( {0 l2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down
4 h) O: Z- F- J* ~2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction# A5 a/ Q, g n" T( x
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
3 y9 [0 q: n8 ~7 ?) y6 J' }2 Z2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned: A9 ]$ H* H0 r! T
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded$ G9 E7 N, x& I1 N
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone" Z4 l8 r3 G( G
1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.
# a1 n8 I# c4 l- S( S% H# m1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization7 g" i' R, h6 L' x( k% w! ?
2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack
# ]/ b1 V1 o- ^" a. T6 j4 c1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols
, {& E, _: b J- u' b) W9 j1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines
' b0 D6 b" u0 _/ W- S' f1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.+ B/ P: C) g8 f- K& F
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types
# f0 z' {" t0 L. }2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.8 i' @' M: A0 P& X8 g
2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command) b9 H: m; L0 p7 M( p8 X- ~8 I
2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation( |$ W! H7 j1 H, [( J) O9 E
2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
' [" j) X, l. d2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column
6 E4 {) S8 _4 a. V2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.
3 F4 Z6 P: w. V9 k2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table: F# j# N: z, K
2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
5 d9 P; D* _" f1 k3 S2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value
. m6 {& r8 R; v# E* \( {8 Y$ X: F2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added+ J- U0 q* ]0 M. [4 u# C6 l5 U$ s
2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
+ T9 {+ y7 k% l6 t2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev' v" L) r# \; Y5 A
2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point* h3 @# N5 ~% [3 C. T, L; {. Q1 Q( \
2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding
0 |! z/ \8 l+ t1 Y% i8 h6 G2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update+ G" Y- U: T$ |9 u7 n, ]
2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.
6 q7 I* `2 \8 O, A) J2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
7 v6 R2 K! E* O7 ~1 K9 O* G2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.
* c# m9 m/ o% ]1 r3 ]2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
2 [ n1 W$ {5 a) v, M; o1 _7 P1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
; F1 R6 ~4 v0 Y# a& z% i2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
, ]' u: q0 A; W' G: ]5 u! s2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash- |: i& O* J N! U3 y" Q
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas1 t2 T. A! B+ h0 y* _- _& i, P
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
. `/ T _: p9 p: Y: w4 T7 I# j7 f! G1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash
$ K1 G% W4 e3 D- t% W1699433 APD EDIT_ETCH Field solver runs when not expected$ w$ h i- @' i5 F- e# Q
1937159 APD EDIT_ETCH Routing clines takes long time
7 o' y6 D/ p& A5 O1 E: P* \) ^2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region$ V5 y0 b0 m- A% V) K
2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051$ K' d; ^% ^) ~ V; ~
2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture" i3 D+ | g" b: C3 f; [
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
# H8 T& T2 a) I, N8 k2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project
/ ^9 |0 Q$ Q/ X) a( ]1 r2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification$ Q9 j! o) w7 U$ `9 H+ P
2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM! `' Q# I0 w; K' N H
2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source5 L- u' w( A- _7 n( A2 O' q
2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol& l$ j" i5 R* S. O2 C/ w( x
2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks/ D- u# k2 s- e" p+ D; j
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
3 M0 z' v# u" v' E2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library m3 J/ H- T/ I7 l2 T/ }' R
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
( \1 j: Q6 y4 O8 j2 y0 x9 \9 [1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
- ~+ f4 f8 x: a- V5 c* K, L8 S1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled
* o5 D8 q2 G- u0 C9 Y9 @- I1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components# I5 B1 S/ {( w. H6 q' \( h6 ]
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names& {/ E* U. e9 T6 I
2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character
. L$ P9 T' G0 w1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas% a9 g3 ~8 ]9 G% u) }( T
1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option# `! \2 w) G$ y6 C z5 |6 d
1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped @2 r. _9 k5 U- j' B
1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical
C6 h' F7 x: k/ M2 L1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
' G0 D0 T. f9 B' o3 E1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas& Q. m" j3 l9 f3 ~. |
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
/ E* D7 D* \" j8 \# H1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast
% Q0 Y6 A, V1 [1 S9 \1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently
' U2 K# X( c! f( r0 T1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
- C! m+ ?4 l5 a! F' q* q7 H& F( X1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI
: Y$ W, L" [6 S1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created
0 ^! t. Q# @, b8 S- T2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library& C, I- n1 a& m5 W# H
1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it8 u# S/ c: b7 M1 q
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL" E) M, S& v2 X
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
8 V# ~9 P3 k5 z- {. A1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message
' f/ j% [& _' i. O7 N K1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor5 ~5 c3 T- ]/ c6 O2 f5 t0 S# p
2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder4 i) d/ d, c$ _
1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
$ o$ c; p2 \2 R3 S) v2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component
; A/ Q0 H4 D" q0 Q1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES
3 @/ y, i. u- M: Y8 Y( m: k& m( _1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option$ y0 {1 W& N/ Z( ~: H4 U: a8 J3 C5 _
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor+ }2 z" Q/ N9 t5 I1 H
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发表于 2019-4-8 19:46
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