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装完还是显示052
0 U9 s1 V* c9 A) sFixed CCRs: SPB 17.2 HF0531 q& [& m' u7 b# {
03-01-2019
; }+ O: a% [/ y+ I" c3 |========================================================================================================================================================
8 F9 {6 D! Q( Y' \7 }0 t& uCCRID Product ProductLevel2 Title- @5 U4 f7 r& w( T2 ?% x
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! K/ f2 ~5 g3 c# G. S) B2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right4 d c. ?, L: t' R9 Z# W
2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag
6 R! s, n' I7 t/ y! L) ?- a( z$ N3 W2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name. h& n* f3 A( M( N. M
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design+ Z, p) ~# ]2 {. C: d2 A: A k
2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error
" P3 z$ I+ g5 U5 `3 W2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object9 ~; Y7 j$ I' [9 t
2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer
5 [" D% P* J/ w1 X2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down
2 \4 R u! C+ t) P0 |' W H; l2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
2 f" f: [& C) \2 ]$ M2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
5 r% Q4 t7 L; x. [; J+ h. D: G) ^2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned
, a) I" |: d" w( X; @+ Y& m2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
: E/ d" ~) \1 J, F2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
" k9 r) b7 R: {4 M0 W+ }- D" q1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.' P- f8 h% }3 Z9 p! M1 R
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization% D$ q8 H1 k: e8 X
2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack
5 B c7 e- S+ n7 I; Q4 E9 v$ X9 D1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols' ]3 ^- e- _/ R B( q* w
1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines
$ ]6 i* Z% [4 U8 y1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol./ ?+ V6 U4 v8 Q
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types
+ {) [5 g9 z) D$ U; Q5 r Q2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.
4 S. l0 M" Y0 V v" ^2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command/ r9 }% k" Y, t5 I f7 C6 ~ ~/ M
2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation+ Y& X7 |7 W& m# V' X
2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design7 v, ~; N/ l; h3 e; i! k4 |7 B
2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column
6 h$ B L. r- w$ N2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.
z4 _$ p, x3 p+ S- ?* H# R/ Z2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table
* |8 m0 |# Z; G$ w7 N+ j- ^( q2 b2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
; Z: w" X( t) @" f" X$ A2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value
4 n+ ?; {7 P* j" T6 f% N2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added. Q C: _- U' |+ P
2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
6 b) f3 j" d; u: k) _; D9 l2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev8 d# U' O! \7 O7 r' U
2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point! D4 F% e2 T% f( F* m9 `* d
2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding/ k) I# W7 w4 l5 S$ z9 g
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update7 h% P$ p( q+ a! s9 Z0 y, O
2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.: c* t( |$ D4 S% {# F8 P/ D0 j
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
& Z0 x; P/ t4 f* ?2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.6 w/ j& x* P! G# I; X9 f+ \- O. J
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash' X, I/ k/ |3 s+ v4 J
1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
1 x# C3 H2 f/ }( p0 M- M+ q f! o% V2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
4 t: y2 u4 n+ Z' l+ t9 c2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash. C( [+ j+ w' L$ D' N L, V
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas
8 u& \7 B- A4 t$ L4 f5 f' {7 g2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden0 M0 p& F# o- a1 Z p* J4 @' O
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash1 N) r! W% @# H& `$ }* e; g
1699433 APD EDIT_ETCH Field solver runs when not expected
( \2 b. U- W' K K1937159 APD EDIT_ETCH Routing clines takes long time
: B, r) L4 a: s5 s1 d1 _5 U2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region
' A, Y: f1 _0 G: _: q) P1 N; U2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051: @) z) c- x, I& d; z; [+ v
2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture" I. z2 q; G& i# z4 S6 r' w+ v
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
" C' }2 g0 [) m; h2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project
2 t/ R6 M$ s; f- {& v W2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification
+ f/ Z, g! g! n% |* h1 _6 h r% V2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
" r: v1 T% y- l+ Z6 k- j4 I" V2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source
/ r+ ]* H0 @: j3 X( n: R$ m2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol) }& j8 {. }- x; _
2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
: z2 O8 M7 e3 k9 L* N$ d2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor8 J4 w& j3 y5 n/ z/ Z
2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library8 @8 U: ?0 F; e
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
% t7 `( U) P3 B8 g8 m; [( i1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
% T" N& N5 o% E) Q2 \9 ?6 V1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled
" W0 y g+ C* X/ `/ Q; n/ X1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components5 q2 Q0 ?, `8 H9 q: n
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names
$ P1 j* W, ~; w' W8 ?! J2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character' _# b. A- `/ m9 [/ H- ~
1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas; ]# I- g; f8 w9 {
1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
, r8 G0 `. Q) M4 y1 m1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped; S' j F' E9 B( \+ p
1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical; E1 U* T! s& p) E3 d8 ?3 T
1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
5 O6 O. ?# }! T' R# j1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas; W& i1 {' l& |1 B% s
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment% L% }% w2 i/ q* w
1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast- P* ~1 [ Y% a/ O' _
1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently
. y8 R& b' m. r! d1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
* X' J4 J9 c" H5 c7 @1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI8 R& E7 v* ~. T9 d( z9 b0 T. [' h
1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created& J7 i. a) n0 X
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library3 k9 B1 I+ T& ~# U5 z4 \( {! s
1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it* O a3 \* ~3 }/ \# Q1 ]* c
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL* F' M, H) S' ]$ ?, J& A- b ~ ^
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
: E* x0 \5 W _8 c# {1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message
- N' R ]% O, _- c4 d$ f1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor; R* g8 B2 _0 D
2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder
0 t3 w4 i, u% R# N: T! @- J' u N1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
; A# X( }9 h: t/ f* I2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component
: I8 k5 A1 O! z+ U' D. I8 R1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES2 j. E5 L0 l: {/ k2 n6 i' |: ^; k$ K
1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option
8 a) i, ~7 w4 R% ~2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor
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发表于 2019-4-8 19:46
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