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装完还是显示052
$ d. K% `, P* H3 ` P! [) i; MFixed CCRs: SPB 17.2 HF053
% S2 S' w% y6 W u, B4 T0 H" S03-01-2019
$ Q# p! N1 @' L% K8 O# R2 V% O========================================================================================================================================================
# U( o* h" C# v3 W, QCCRID Product ProductLevel2 Title& B( R# z; d7 g* h; v
========================================================================================================================================================
. p! M9 z+ g) N2 o2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right' |. z8 V0 S8 s' G& _: z" }. F6 k
2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag" E, b6 Y4 ~" [' q. T t
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name1 `; G& _( `$ P9 r* E
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
5 t! |8 W, f, P1 J6 k2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error6 F. I) c+ U& d1 m5 W7 L3 \
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object! X1 K: ]' D* O( \
2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer, x4 s6 {( ^# L" C: c2 h
2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down! i9 j* ~( x* F7 f
2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction. z5 ^) m9 {& z/ L/ A2 V& {' n' i
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
* g J( }; u/ d2 o: M1 ]2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned
9 i! z0 O6 V1 z9 @' |8 Q2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded F& V1 K* V7 v* G0 K2 |$ v6 V0 D+ s
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
! E( p* P& q& R5 ^4 ~1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.% Y! ^6 V7 o+ n A; [5 `
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization
1 s# v2 m" ?( y& G2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack
- J! p5 k1 H! }4 W1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols
7 Q+ u& s+ `$ K* N. A" {1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines% ?; J( v. J: W6 V; g# s( r6 D: V
1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.
+ p7 U. R0 L8 c: ]( d( q% y3 i1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types( k1 f0 g6 _% r6 R8 R* l
2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin., i% i( M2 S0 @% ]
2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
: z9 }( l0 N' |+ K/ O4 S2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation
: s+ Y) K# Q" m# Y* W& w) p0 i. f. }2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
/ A( h! N0 U$ @: u2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column
" z& q' Q5 n0 @* d, _2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.
& H3 w; u5 @3 U g; U6 p) @. o2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table
2 B4 e, s7 I! ^2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
4 m" m, s2 S$ F' r8 e Z2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value5 [! Z, y& T4 s$ V6 I' h; n
2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added' y- \+ k) ?9 k h2 t+ u
2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
% r( ^' n" {, D% ]2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev
" J# @% W! c3 p: i2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point c7 x, Y; A2 l' d* z
2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding
6 g& a$ p! r: C+ d8 w8 j2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update G& ?6 E- Z5 P% C" P2 r( k
2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.6 S1 y8 c2 [2 m4 @$ a7 r) A4 k# b4 n
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present) t7 }3 [: i# Y9 L2 A8 ?, _
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.7 C2 R6 \, _$ a: _
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
( S$ X( Y# D8 O/ o1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
0 z! y% p$ n, _0 S: u" O/ z2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
0 l) |1 m3 b' u2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash1 k2 _8 z; [, M1 w" t0 Y/ {- T
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas
7 O* X0 R8 w5 p- k: N2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
, W: i" [/ _- j9 Q, d& x p9 ~1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash
, z: O V \+ K- @0 _# p- ?( p$ k3 P1699433 APD EDIT_ETCH Field solver runs when not expected
+ x% _# o& q2 q1937159 APD EDIT_ETCH Routing clines takes long time
" a) C) \- p* [- y$ P$ f- ]5 v2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region
& i7 J0 V: p3 D( l5 f8 ~0 o1 h2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051
/ j7 x6 |5 R) u7 ~. c9 |" i7 E" ?7 k2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture
# m% [4 V9 O& y4 _$ d+ j$ a2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
9 C) v) o, q; J* A9 ~+ T; v& T2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project
: W# H* l5 S7 l* ?/ d, v2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification
6 y8 B, N4 a3 x/ G2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
0 O. I! e5 o3 r2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source; Z, T. B$ t; }# l, Y
2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol8 [6 c' P) d: w" w& b5 M. g
2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks) e7 d- I- f! k
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor U6 _: _. j, ^& x9 u' g
2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library; T0 \# W/ }+ S
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty$ v# V% k3 p2 F, o- y. \
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error0 A( w$ f9 U7 f0 Q
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled) W: X2 I/ Q( R6 G
1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components; ?. R2 h1 i0 g) O" y% Z' U
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names
6 D$ o' \8 `) ]7 b9 B. q2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character
: r/ Z2 \3 R, S5 _$ e2 D. M1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
* n4 E) E( c- U3 a1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
b8 |& V: Z1 j- w1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped: L+ Y% }) H4 t7 Y( v a3 {
1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical* t7 I1 x, J# a
1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names5 h4 g1 K3 U/ V) o
1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas" P/ ]* x r( t1 z$ l
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
8 l; j `6 D! s- [8 o$ I6 M1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast
. K0 m: j5 ?. y/ \; |4 Y1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently. |9 D/ `* h h) F3 X* j
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page* x$ |& x9 Z W2 b3 C# k; g
1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI
! W; L0 r, m W% R1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created
; n' M1 } L& L7 T7 u1 I \2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
) S$ Q/ M7 b% e1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
* P& B4 D/ n q+ z3 I& z h+ G1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL
u [& Q4 X' E5 r( X1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture/ O& v) g+ W: H/ `2 ^
1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message
; ]- O$ B2 V- z; O( N1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor
4 }7 D4 P3 p0 e3 B. ]2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder
) A7 u# P. K& @( W' h1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message+ f& N; G4 C& _# I
2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component7 Z1 o, j& _# A8 B" ]/ g6 R
1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES o6 w! F4 \ \/ I+ \; ]2 f. Q V
1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option
8 _' b8 K5 M8 b! f/ G2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor
7 J" C4 E' M2 _, U( A0 L4 k. w8 O% O: m( _- T
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发表于 2019-4-8 19:46
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