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装完还是显示052
4 h% n# E0 R& P" iFixed CCRs: SPB 17.2 HF053
) R" t5 P: d( k. G' i: X. r03-01-2019. F8 n, M2 x. w
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CCRID Product ProductLevel2 Title
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2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right
3 S7 f f; Y. Z8 |2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag q5 j8 g! J t- q5 A; Y
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name; |$ t. X) M5 D/ k5 w
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design3 r& c1 C3 n- s2 f' N+ [
2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error& S* o* `" N( i8 a* {3 h3 e1 ~3 `
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
% E& [! B+ B& W6 b- m2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer$ d( S4 c: J2 y2 k/ Y4 W
2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down2 N! N0 z. M, b" Q& t, j9 c
2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction& Z- X, R% j* u2 Q. e7 l4 Y' P
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
. n$ O4 m! s5 W& r% q- @. \2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned
$ K l0 b, G& Y2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded0 O& F+ k2 K* s+ a2 m
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone( t; y. {6 u! {$ E- n
1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.
1 [. X! \+ U ?1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization7 b; V* N+ |. t5 R# l- A6 P6 G
2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack/ Q6 {) r2 ~, j5 y* s
1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols
7 X" {/ X9 k, D$ Z1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines
2 G1 m/ @2 a2 h7 y6 T' K1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.- L7 P. ]! @0 X. E, b
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types! \" }. s( R: m2 f. x
2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.
' w3 O2 h( |/ a/ B4 _2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
6 X) H. b+ M4 o4 S+ |1 [2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation
" v+ z' L) S* Z; z3 L7 x2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
& y# m7 Z7 t! \( C i2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column! s9 \+ ?9 j8 N- b
2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.
% \/ M% T: n1 f/ L1 v5 A. C9 h5 D2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table6 b% w8 {5 l6 Z: [
2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data5 X- v; c1 k- G+ V) J
2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value
, S! D Y" m0 y: @& R2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added8 A7 J7 `, L6 ]$ k0 d; y2 }- z
2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
# {. t o" |' x; {; f2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev i- U7 l& i, `7 i5 F& d# e
2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
9 _( k# e- Y4 \; b3 e9 e2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding
5 ]7 |3 t2 C$ m* B" q2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update! N) M5 d) Q) h( t" j
2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.
+ }4 B* F" O! B/ T" J( j0 ?2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present, p, K/ s! e) { X- f* U- |
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.% P4 v4 H8 M8 ]! y( K( ~: z8 v
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
3 l6 o8 ~; X- O0 J7 L' n, O1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
4 {5 b- F; }' j! h2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
4 D% v! p* J5 S2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash
/ G3 g) f/ C; K5 g4 A( u2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas% \2 w$ ~/ g- ]: K* J! ]% H
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden0 S+ M0 a! P) T
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash# M9 x% a" e4 E5 Y4 Q
1699433 APD EDIT_ETCH Field solver runs when not expected. U9 Z: S- D' w* ?2 Q a+ V
1937159 APD EDIT_ETCH Routing clines takes long time. x+ Z# L9 q# |" e i) K1 d
2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region- t8 O9 E( F' B- Q! i
2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051
% y/ z- r, J' u( \2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture
N0 ]2 x2 i$ K6 X" A2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved. U7 ~+ w$ r. c
2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project
, I$ H# S0 G1 h4 m# r: [1 N2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification2 r) A+ o! ?! `- L% D
2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
* z) [7 |$ z" c2 P$ b( }2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source% Q b3 q) l9 G. C8 P% [( e
2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol
6 T8 {& d& M8 w( }# V+ d2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
5 ~5 k$ I C# S5 T% |( J' j2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor' w4 [. O( m" R+ W! F( J2 \3 L2 u1 L5 Y
2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library2 ? q( F' v! ?; w+ D8 P0 k+ S
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
) U; o. g6 N$ e0 p5 G, ]1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error& ]; w0 D9 Q5 C/ A9 s
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled6 x+ r, R% ?0 z
1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components$ ?* P- d9 J* l
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names
0 ~2 N# p: j* j7 T( r1 T2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character5 v0 o% s7 Q* }) Z( u. t( W7 q1 ~5 r
1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas; l6 K" V" V3 K5 P& B: `
1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option8 V! P5 R+ D) Q# `! {. r: C& O
1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped* h& k+ f1 m; M6 d# f! W$ J1 }4 c5 C
1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical
" o5 \: ?: {" y* q) R1 m7 R1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
1 o" L+ Y" j$ }* a1 z/ A1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas
. |1 v$ p+ |$ o8 R& j1 u0 O) T9 p1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
6 ^7 d$ K8 V7 V9 `" ?1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast
! g9 Q$ |+ v b2 L; h' E1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently
Q; O! }, g2 k( b3 q1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page8 g$ u9 o, E) f* T0 d. W
1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI2 z$ y! T0 c; B! R# @, |& H
1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created8 ~! j& w) X2 \8 l- k8 V
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library! q) m+ N9 p' w
1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it( e) F f, L8 a) f. ?1 S
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL
, i0 e$ b6 K/ z& u7 J1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
& S$ z8 j% _7 U+ b K! R4 A$ s) R1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message
; w) m( \* o" }/ i' h1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor
6 }& q" s& ~' E3 U5 c0 d# ^2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder! o( N6 K3 `) G
1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message* s- x# P2 Q3 d; T/ [* t
2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component! Z8 d0 o5 ?6 G6 x! _/ \
1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES* t. {) @/ Z* z7 f9 M; }
1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option
+ Y: t) c6 ?. ^/ Q0 l) \ y2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor
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