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装完还是显示052
. F5 q+ [2 ~1 M8 G& c& iFixed CCRs: SPB 17.2 HF0536 {5 a; ?" k* T* X( N
03-01-2019
+ r2 v# p) r( k- h0 a* s========================================================================================================================================================5 S/ ~0 C {2 ?# f- U Q( D' r6 E
CCRID Product ProductLevel2 Title0 w7 M4 f3 D- o9 c0 o- T+ J
========================================================================================================================================================7 ?5 w( m7 i1 L" X
2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right" `1 q/ Z% [0 k- _9 d8 m; u
2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag
0 c0 c0 v% _1 b. o6 @) {6 X, v2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
) E0 S2 H2 |) Y* M$ y( d2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design# E# t2 f4 x X5 `# z( Y1 w7 y
2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error
* D$ @- e5 f- e! d2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object: ]3 o/ R. y5 c( K
2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer
: L4 t1 k4 L5 O% ^2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down3 k' ` Q7 W4 P4 f
2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
0 @1 {. \) s7 A9 E9 g P+ g; k2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
0 a8 j6 J2 y% o0 D( o7 Z2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned
9 j& R o& Z0 ]: }/ _2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded @2 k# E. t) d) v7 v
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone; N$ r: _ m" j3 V% S8 t
1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.
; C8 r: Y! h8 T$ E: j; { r) v1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization
; `# d; V6 E/ y3 M) w2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack
% m4 _% ~( K3 b0 g" A: ]4 G* L1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols
8 R1 M3 \7 N9 `/ H2 ?) J1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines3 j' l; d2 V* E$ x7 i
1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.& Y( ?2 `" J0 h- m6 S* t# d. H
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types, }# e5 m6 O( Q1 q+ W4 z, m
2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.% k; C- t! {: E) V' M& q* l
2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command$ v, h1 n3 M6 P, B6 i( T- X
2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation
1 r( P5 l, x* T7 \. d: c. \2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
% S8 v- [# s# v. k. v7 P7 N6 J/ o2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column! Y/ c0 V! w! Q2 x
2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.6 i+ P, C, L- B" k( i% Z* C
2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table" v! {0 w( z8 p# ]. {( n
2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
0 S$ S) U" Q/ R- Z H* n* b2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value
& Q0 [9 {0 |. v) T& j: @2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added% _3 b7 w, a4 s& |. N* k- P
2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
- }. h$ f6 i5 k1 ^2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev- m1 E1 ^; M. e4 Z* J: R
2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
+ M: h+ b3 N3 r! a, _: W! W9 }9 I2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding
5 m9 v3 m+ J# Q2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update# P8 z( \8 w5 e% |
2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.! S: J& P' N- t- ~
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
2 q! W5 |5 R% e2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.; a$ s# A# \; |; M5 k% \
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash8 N s9 e1 ?; ~- o6 ]- U- X; W, T
1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
h! ~; ]2 W/ ~9 Z! y% p2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
* p1 D/ W6 C U+ e) U1 l2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash
" m* i% T' ?$ c# t2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas
9 n/ F" ]! k# M( @2 a- R( N2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
; |! c4 t5 n# l- I1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash
- t4 j* v5 ?! J3 ~" H ]8 i d; a3 s1699433 APD EDIT_ETCH Field solver runs when not expected
' D+ r, d V9 D& ~# ~* [3 L1937159 APD EDIT_ETCH Routing clines takes long time
+ L* Z1 g3 i' Z! S+ T2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region3 e' b) a5 O1 e! ]# Y
2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 0516 @# @9 @" w `. t y0 U
2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture4 ?9 b' b6 ~! Z: P) d8 T/ ^4 y0 ?% _
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
5 f6 X- Z" J! N2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project
4 z7 S4 @4 z( A8 X2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification! }6 S. k1 w' j |" N
2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
4 E2 L( Z/ b; E% l' `$ q; e% j2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source3 ~) @- y. F* ^1 y& |8 a1 E1 E
2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol
; W- v0 U! I5 \ ~3 L6 U2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
% K! M& v; i3 J1 Y& M$ x2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor7 ?0 O, S: A& F
2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library7 J2 Z' \: Q; d/ A
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty2 _- j$ o9 |/ w
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error, I4 w/ }+ q' [
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled
' h: [% W+ X# M' ?# f8 ^$ q" ?1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components$ {' l5 T( e3 l K+ H, o
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names0 i J' D8 P s; Y
2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character
: C5 g8 `$ a! c& f9 ?5 O1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
5 v& I k2 D, S3 W1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
0 g' B; o J) e1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped
& u V) Y4 ?: U: N( K& p/ V1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical
, M1 C J$ ~+ l+ }* s, P1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
& z/ L( `; I2 X, I1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas
3 q# `6 W( o# q" a0 w' Z& c2 E1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
( `& s. I4 t2 X; B8 S# j1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast
9 U2 |! n! c, H! X i1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently, _# p; f" g1 E& K
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page2 _0 H5 S9 u% {5 G. _
1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI
X0 G; d" a9 Q$ V; v1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created
# K' n; T9 ^7 k9 T4 M2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
, O A8 o) X% w/ g0 T: H+ ~4 C1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
* Y# F- t; |# y; m5 a+ e6 q& o1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL1 U. S( u8 D7 Z
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture7 M! A2 n$ X9 S6 F) C& E# F2 P( l
1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message8 J4 o$ M9 p4 X; c8 z( M
1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor$ s, g* |. Z; X6 `# m8 f1 m
2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder$ Y4 t m8 h& p- {
1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
3 J9 @3 V) m1 v- N! C0 R2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component
" i, ~! b/ i5 I8 S% m, C( n1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES$ ? t; P4 C2 m3 F& n& F0 i% Y
1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option) _0 x( X/ V5 E: W! e
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor; k' x3 ~3 ?9 T! a4 ~
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发表于 2019-4-6 21:51
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