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装完还是显示052 ( Y* k2 F& Q5 Q- e
Fixed CCRs: SPB 17.2 HF053
; O A( E( ?1 F) T1 G' |03-01-2019
% b- n# m$ P' N========================================================================================================================================================' A# }# F6 _; d" p( l7 j
CCRID Product ProductLevel2 Title& O' Z; |* Q; u$ C' d
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2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right- Q* K- a& z2 Z0 y. c
2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag/ @* r% p$ e8 E; N. D0 t- U' O/ A
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name7 S; R" g1 ^/ y/ V; L( I
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design2 G3 e3 V4 [8 T) @
2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error' g, \! t# V. o0 B5 W6 \
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object! Q/ P) i+ S6 f6 T0 z+ S
2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer
' o/ l6 A0 W8 @* b5 ~6 ^+ n2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down
% ?- J6 D2 T2 a5 ~6 I& }/ J8 c) E2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
* m: W/ q9 r- A& f) X* N4 a2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
7 ] ~* @. O0 A% |/ m$ d, @4 f2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned; b, I( A1 B4 W, Y5 @
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded; y! z9 Z" ~* t
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
* _# w W0 y5 V1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.3 K! s' f& Y4 Q; J7 O+ s* s7 e! S! R
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization
3 Z4 L% ^4 L8 t- u; M2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack+ P2 V. K9 r( O" m- w
1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols$ S1 t# m/ s6 i' X# b3 R& P
1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines
5 g/ ~0 o% q5 S# X1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.
. ~, y9 [! G u1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types& P" `. z0 [% f2 j& g: y1 D' m
2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.8 @ T( x7 X$ x' v3 c
2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
* h0 @8 t) }0 D7 Q( V2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation& d h8 i; [; |7 L5 L/ Q5 x, a
2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
$ \6 [5 P3 [: T! f% J2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column/ Y8 T, a# q" h; u4 J8 W. |
2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.- Y* ~. `: _& h! C0 l% q* q
2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table2 Q& e. E( m: S5 Z) ?
2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data3 X6 N7 h' M, N% i
2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value: n- k6 _& W; \" N
2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added
7 U( z' W6 c' b8 ?2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created2 K8 c2 I# Q2 Z' C
2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev
1 V" O9 I" ~" U3 F9 B2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
. \: _* K& t2 s9 Q. s: K7 v% n2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding9 ?9 b( S! z4 ^' _4 M
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update" a5 A6 s, a S, Q2 ^* ]- t
2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.& W! u( D0 p$ `9 I, t% q3 _
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present4 _$ L% v) ?- j9 t" l: r- ?
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.
. @$ Q3 a. W9 W# X" M2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
3 |' C8 b+ p) q. f( H! T6 A, z1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint4 {5 P6 n& | O% K
2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
: z4 V3 \) R4 N X2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash6 j2 c# P9 t7 \1 U
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas
! \/ [3 ?9 O( c2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden: S- I' N' a) H9 m3 G
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash" |- S7 [( J( Q! G7 p
1699433 APD EDIT_ETCH Field solver runs when not expected& c( G5 Q% Q. O5 k
1937159 APD EDIT_ETCH Routing clines takes long time
3 A6 @8 s1 O) [1 ]2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region
! f* Q. t. h. d2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051. S9 d; H$ K8 h$ I
2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture1 U& Z" l. @! Z9 j; e$ b
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved H ^( `1 C6 L: A, g6 ~
2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project
- T+ t$ R3 g; u8 y- ]& t2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification0 [7 O$ x0 s* u, y, O
2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM& `5 H% U8 R/ q2 o j v: r3 p# p
2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source: @: T$ d$ p5 t5 f/ M: d
2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol
N8 a2 }! A2 y% b9 W1 i2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
! F, s& _+ n4 s; e* h2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
! e# D1 G0 p$ S/ t2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library7 D l: d! ], A; p( x
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty/ E2 q3 w/ G& M! I7 [7 ^9 T
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
2 f% T; }) a* C: O$ N1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled
4 [% g1 c/ Q% v# l1 e/ x- m1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components
; P9 Q4 _( n5 h! [+ z: g1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names
6 B9 H0 _7 T3 a$ A- m+ \2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character
0 f- n+ ?! F% `( W& M1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
- O t9 k! T4 g8 H: F" a1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
3 F" k+ N* C+ a0 o1 w( c# u1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped' Y0 a1 V3 Q) @) E
1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical
" S1 f1 K" h) v( a. h, ]1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
: W( [7 W* y4 q' d; C5 N* M1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas
: R/ |/ u. X# J+ C5 B* p1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
" X& c# U# A4 g7 O6 m1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast
$ `: B | t% b. T9 n1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently
9 z9 R) }$ o$ R6 q1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
) {9 B9 m+ [0 u4 v1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI7 D! q8 y" V5 b& V ]
1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created
% i# U$ _0 ^4 w w5 J! J) F- f& \2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library$ R& L' ^1 Y; d2 r. H) A
1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it$ ], {9 O4 Q3 L) t9 K. K# M
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL5 c, b; R* Z z) v; E$ h* q8 D/ T |
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture# L# N! T6 z6 f8 a$ j' X$ q2 O) {; r
1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message
0 i4 B1 G7 e2 V2 ]1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor
! ~6 _: [$ N! c7 Z, q2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder
8 B- l4 D. Z8 ^- }, o5 Y/ l( ?7 Q1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
$ G0 h7 Y- k9 k7 H7 ~ n2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component2 c0 k" `' L/ l! W* u/ u! m) E
1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES2 e6 B6 J3 l) J4 p9 j
1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option: j, f) Y m' h3 @( o6 z
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor$ \/ [0 \. e5 X- Y. a2 s7 `
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发表于 2019-4-6 21:51
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