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装完还是显示052
- q) v$ o8 X: H: e9 fFixed CCRs: SPB 17.2 HF0530 T1 H( J. |4 j5 U) V
03-01-20197 T* T" ?+ p$ d7 C4 e7 E6 @
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CCRID Product ProductLevel2 Title- U3 m' q# W# c5 X% r# x3 d5 K/ i
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* e8 r- y _) O4 Q; {- V! n. v2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right
- U# e5 m% y8 E# w5 n2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag) Y; V- ^' `" ~9 Y" w! O A
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name! t0 g9 S/ }6 E6 E4 _, K) Z! Z
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
6 \; B# I: J' U( J. r2 z8 x4 @2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error
3 [. z6 g$ l6 v6 {2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object4 |# E. q3 W- g3 @
2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer
! ?! V) `0 }1 J/ y. Q2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down4 I* I) n; M$ H3 y6 @# a0 t) g z
2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
0 K9 x6 I) K& F8 p# U2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
- b3 m) H# `# h6 J. U2 `0 v2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned8 L1 z. L# p9 Q0 s( C
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded0 D" h/ z8 i( f( N" p/ U
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
. j5 O1 \9 ?7 H J' f( z0 `$ ~1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.% p3 X. W$ c0 G7 n
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization# u% t2 w# Q# ?8 o. y) v; q
2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack
$ [3 m X: }1 s1 `- b1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols" l M1 ?5 g* ~
1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines
5 `- k* U, @. q" Z) @1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.6 B; w, P+ _" U; S7 n$ w
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types+ u0 n* D5 |" n5 i/ j
2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.
: A! _8 r6 Z1 ]0 H+ d: a2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
! _- |$ F) R. T4 C4 G& ?" \2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation% s" [( N: j( }
2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design. A. u% D; \. o. X# h! S3 \
2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column2 Y2 |4 f7 `0 Q7 {3 m
2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table." z# W/ w M ?" r% H4 y0 Q, c P3 o
2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table
3 F5 O+ {6 l3 R* e* H5 U" S) e) k2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
, b, M- ~" L! A2 D3 n2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value, t% R4 S# O0 E9 O$ t
2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added' ]9 B8 t M7 R! A* P' y6 s
2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
) e0 \2 h* d$ A! x( `2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev
2 p( U6 Y& {$ F" U# ?0 S0 k1 O6 B2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
- d4 {: Y1 y D5 G$ _' r2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding# ^* `, o( _$ G1 q8 ^9 U
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
( y7 `2 g( |* _5 N* a9 F2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol. d( ?- L9 N1 F* M2 @5 R
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present2 j, r7 R; C, p
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.
& M- y8 S5 ^2 Q' \2 O2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
# b3 y( D% V9 E1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
- f ?& i& ]9 Y2 ?/ m2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
5 ~. Y( V% e8 [8 i2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash( w! `) N8 R) n* Q( E& d9 u0 c" C
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas; r- z# U, R8 U( G5 D& @! r9 S
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden8 b1 {7 g) O& \- O4 S h
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash
! A( W) w: L3 p6 d3 H1699433 APD EDIT_ETCH Field solver runs when not expected
0 R& Q* h4 n1 Q# c1937159 APD EDIT_ETCH Routing clines takes long time6 h# V8 Z N" x ^4 a! r8 r7 m
2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region! Q" c$ g4 f2 W% u
2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051' {5 i. m4 R& \3 M. `3 }, j
2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture$ \ Y4 G* y2 I8 k- K
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved6 E8 P" R5 L2 ]! ]
2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project
1 m. b; ~: b5 W2 t6 v) a2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification
1 J6 o% V) p8 U- T# M2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM) M/ @5 Z6 t0 R/ g; X+ O ]) s
2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source( b9 }! }, T4 G& l* }" `$ F
2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol, V$ E/ w! l3 a, K. A+ f- W* n
2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
1 b5 m; u+ G8 a! g# T2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
' B6 q" W* s: n4 ~7 P5 r' S2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library
" c% t$ U- b1 E' I' G! o8 O; ~2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
1 X7 }3 `0 H. T0 @- Z; Q" V1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
* U3 B8 E J# e7 y1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled
( {& N7 L% a# t& A' H1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components5 U) U; W/ V9 t% l# i
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names& J1 A8 S/ D; r* }6 N, o" Y
2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character
! k6 q" r7 |) D* @8 o1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas! ^1 q& e# {2 ^ J
1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
5 L6 ~$ H Q8 G* U5 S: w1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped
$ z: v t# Z- r. w# w: u$ d1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical
% k' k- a' q8 u- `8 O0 W! j" Q1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
. F* f" b u8 [% @8 G1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas6 Y2 K+ F# j. ~4 f8 Q
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
. E3 v* |+ m) w1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast# `& U* x3 Z" _- ^
1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently4 T7 q' W. x+ }
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page9 C" W' Q( g5 e5 [! R, k
1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI
- s; g9 p: f) ?* A' W9 v1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created4 [) ~) ~) O0 U
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library) X5 {9 }5 n' R E
1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
( s* `, j9 |# F+ c ~1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL
1 z. R) p1 E) y) v1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
, T4 y/ |3 u$ J1 s1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message+ J! k# \6 ?; V. H
1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor
+ P, D; a' D; s' C+ n2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder
+ T! W* {7 P i$ I1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message; U9 {4 {3 i- s( w
2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component6 G$ m7 x+ x' }7 V1 @# L" [7 N
1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES/ E6 L* z7 @3 J: g
1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option& I0 o# H [, L
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor
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发表于 2019-4-6 21:51
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