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如何通过综合工具综合后给出的一个报告修改优化自己的设计?
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- x8 T: G0 r. G$ J; x# G, ~! c, h" O以下面我写的为例子
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# ~8 o, J5 t v1 b; B5 f6 O) y还请高手指点拉
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原代码:
" T5 U- D+ c+ m s========================================================================================================================== # P+ s. S+ M+ N) c, b7 i
assign Transmite_Task_Sign =~(|NUM_SIGN_r);+ K) O& |* C% E; e. S/ w
& q+ Y5 Z3 I' ~ D" |5 y
# K S* Q9 g; d( R. l9 n1 O7 \( b5 D, s( ~7 s% d! I, t$ ?
always @(posedge i_Clock or negedge i_Reset_n)
7 N8 ~$ p% s" e3 w if(~i_Reset_n)
) S" s8 D( o; a% s# Q NUM_SIGN_r<=0;
; V# Z* U! `6 e& P: t! P O5 ~ else begin/ D7 W3 e4 }7 [1 F' d y
case ({UART_WR_SWITCH,Transmite_OK_reg})- n& C$ w1 |2 _, t0 H
2'b10:NUM_SIGN_r<=NUM_SIGN;
1 T! d- {, y. W' U* C 2'b01:if(NUM_SIGN_r!==0)NUM_SIGN_r<=NUM_SIGN_r-1;) g' S% d! ~. n3 ]: Q/ F
default:NUM_SIGN_r<=NUM_SIGN_r;
& L# z" K# y! t, N- Y3 p: L endcase. v$ X, Q- j# G' O1 u
end* c/ z4 V: z( Q; T3 o- `- a& X5 ^
==========================================================================================================================- v1 ~4 H% z* y+ X
0 e7 B5 g% k+ }
! F9 W2 x& L [$ ^8 d- |报告:( e/ B$ v8 o" c4 y9 E- c. H
Worst slack in design: -0.836
7 g) p6 v u& i# R# Q7 }! z7 S6 e5 B) [3 X! i1 ^1 g, k
Requested Estimated Requested Estimated Clock Clock
' @4 P2 i' T" T pStarting Clock Frequency Frequency Period Period Slack Type Group
# q2 ^3 l4 K" R$ R% s+ n) o--------------------------------------------------------------------------------------------------------------------------
/ [. I: N6 T+ Q" S: P3 e8 v9 |, {I2C_TEST|i_Clock 263.4 MHz 215.9 MHz 3.796 4.632 -0.836 inferred Autoconstr_clkgroup_0
) C V5 F q7 h6 x==========================================================================================================================, P8 u$ \ ^- b& X2 o
4 i) ` C# R' L k6 EStarting Points with Worst Slack
' ~& b, e1 N; s" O********************************
( h. `- u9 W/ f4 A
' x" q2 V. C: V Starting Arrival + K8 O4 @4 x R1 l' @: a a5 S X
Instance Reference Type Pin Net Time Slack
7 A. j# `/ {9 g% j0 }& S+ X* O Clock
9 w6 a1 H5 f* }. P/ @3 h- i7 j9 k------------------------------------------------------------------------------------------------------------------------------------------------------------------3 C, ?' Q7 z) P
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[0] I2C_TEST|i_Clock cycloneii_lcell_ff regout NUM_SIGN_r[0] 0.255 -0.836
2 r) b* f2 j3 ^- \UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[1] I2C_TEST|i_Clock cycloneii_lcell_ff regout NUM_SIGN_r[1] 0.255 -0.817- ^7 a. a" H" q, a: m
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[4] I2C_TEST|i_Clock cycloneii_lcell_ff regout NUM_SIGN_r[4] 0.255 -0.688! z' c. H7 D+ o7 k: h& j
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[5] I2C_TEST|i_Clock cycloneii_lcell_ff regout NUM_SIGN_r[5] 0.255 -0.669
; r) D N9 q# @. g3 p8 FUART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[16] I2C_TEST|i_Clock cycloneii_lcell_ff regout NUM_SIGN_r[16] 0.255 -0.669
; ?& x% ^1 F. pUART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[8] I2C_TEST|i_Clock cycloneii_lcell_ff regout NUM_SIGN_r[8] 0.255 -0.5616 o- s, k9 y. Z5 j2 w% v, x
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[9] I2C_TEST|i_Clock cycloneii_lcell_ff regout NUM_SIGN_r[9] 0.255 -0.542$ K$ }* g0 S1 n
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[17] I2C_TEST|i_Clock cycloneii_lcell_ff regout NUM_SIGN_r[17] 0.255 -0.542
n$ ^' c! ]2 {& S$ E3 y: lUART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[2] I2C_TEST|i_Clock cycloneii_lcell_ff regout NUM_SIGN_r[2] 0.255 -0.521
& J I5 j5 \5 Q' s( eUART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[3] I2C_TEST|i_Clock cycloneii_lcell_ff regout NUM_SIGN_r[3] 0.255 -0.394
4 S" X. P: q* x; F0 |==================================================================================================================================================================3 R3 G6 R6 b0 m1 f) s
6 |# V, i5 A/ B) ?) W/ O. ]5 J0 V z
Ending Points with Worst Slack$ }! _' b- \& [ D( C' X# i
******************************
, r; [5 L" |/ [0 o4 j4 q8 Z$ |. |/ Y$ q) y( }; @
Starting Required : Q7 D* C7 p5 W* g7 J
Instance Reference Type Pin Net Time Slack * e8 b: p' ~: J3 ]$ a5 G% a z
Clock / B/ }4 M0 H& Z5 s5 f* U7 S# O
----------------------------------------------------------------------------------------------------------------------------------------------------------------
% G, x: y# }. j; nUART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[0] I2C_TEST|i_Clock cycloneii_lcell_ff ena NUM_SIGN_rlde_0 3.133 -0.836" q( h+ m( m. X$ @
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[1] I2C_TEST|i_Clock cycloneii_lcell_ff ena NUM_SIGN_rlde_0 3.133 -0.8366 F6 D2 Q, C7 N1 s' ~8 s( h
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[2] I2C_TEST|i_Clock cycloneii_lcell_ff ena NUM_SIGN_rlde_0 3.133 -0.836
$ u" D( X5 w% F8 c0 I2 u' i" T: LUART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[3] I2C_TEST|i_Clock cycloneii_lcell_ff ena NUM_SIGN_rlde_0 3.133 -0.836
7 c* P: }2 s6 {5 q9 _0 w% n* SUART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[4] I2C_TEST|i_Clock cycloneii_lcell_ff ena NUM_SIGN_rlde_0 3.133 -0.836
7 p" [7 [' ^/ y3 r. @UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[5] I2C_TEST|i_Clock cycloneii_lcell_ff ena NUM_SIGN_rlde_0 3.133 -0.836( H& _& J; O8 J9 b0 I% @: g, [
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[6] I2C_TEST|i_Clock cycloneii_lcell_ff ena NUM_SIGN_rlde_0 3.133 -0.836
" }3 d* v r e. N) @( A% s0 Q, {! bUART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[7] I2C_TEST|i_Clock cycloneii_lcell_ff ena NUM_SIGN_rlde_0 3.133 -0.8369 b( d" e/ p( O( o! z) _
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[8] I2C_TEST|i_Clock cycloneii_lcell_ff ena NUM_SIGN_rlde_0 3.133 -0.836# e: q6 i1 g4 b: c, _
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[9] I2C_TEST|i_Clock cycloneii_lcell_ff ena NUM_SIGN_rlde_0 3.133 -0.8366 T7 J7 [1 O' ~3 Y" F
================================================================================================================================================================
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. z7 a# L# R2 g修改后的代码:. T! a, X" t5 g! a* \4 ?
==========================================================================================================================. t/ ?6 _- z5 y- W) u
assign TX_Baudrate_Clock_Stop=Transmite_Task_Finish & StopCHECK_Ack;% u1 [) { P1 v
reg d1;( L8 }/ F' K; ~2 n' I) F0 j0 s
reg d2;0 J. D: b; u; c$ w8 o% D0 b
reg d3,d4,d5,d6,d7,d8,d9,d10;6 l9 v2 Y5 C' }' b. V3 A. J a
reg Transmite_Task_Sign;, W3 l6 o/ Z# ?2 n
always @(posedge i_Clock or negedge i_Reset_n)
' w3 g, V8 L3 V6 L, r" Dif(~i_Reset_n)begin5 ~' H% i1 i2 G: S
d1<=0;9 R% g H& q* e+ g$ Y
d2<=0;7 R. F5 @# i5 p4 Y- J7 Q- J0 ?
d3<=0;
9 Z6 j0 j* W' [d4<=0;; v5 [9 v7 _6 |
d5<=0;# O. R7 q# z' w8 B) G7 k* I0 U, F
d6<=0; : H$ M- p+ O$ D, g! Y! J7 q
d7<=0;
g' C, H; Y4 ^. ^d8<=0;
/ W; ?# ?' q# Z sd9<=0;
6 u; U9 {% Z3 Md10<=0;
& R% t5 ?' c' \; ^Transmite_Task_Sign<=0;% O# N& M; t2 F0 ~- g7 w
end( {% s/ m, P5 n0 M5 T
else begin
" W! j o4 i. ad1<=|NUM_SIGN_r[1:0];6 ^ R# Y! ], \3 N/ n
d2<=|NUM_SIGN_r[5:3];3 d' ~. x/ ^5 {+ W$ r
d3<=|NUM_SIGN_r[8:6];9 y/ w* y5 x% o) R& {0 `! I9 z# I
d4<=|NUM_SIGN_r[11:9];0 W( i; k* g7 |: P* H( p
d5<=|NUM_SIGN_r[14:12];
0 c3 |8 \$ R5 Q4 t2 U4 S. rd6<=|NUM_SIGN_r[17:15];& V4 @; {& M8 O( F; r
d7<=d1 | d2; ; n) ?6 U. {$ r# }: {) C
d8<=d3 | d4;
0 Z1 n9 ~# {% T3 ]! l5 Y; K0 Gd9<=d5 | d6; 2 g) k0 C9 r e! S8 o F: k
d10<=d7 | d8 | d9;( g5 X2 o4 w* ?7 g8 j
Transmite_Task_Sign<=~d10;
; I( ^2 S) D8 O. n3 B# J( wend( R" q! V3 d- P! ?) y3 B7 Z7 H
==========================================================================================================================5 h3 v1 D8 S$ J' G$ o/ P
) p$ i7 ~9 W1 C& w- l
报告:8 s2 x7 c) N! L! p; `* S
" T$ z7 o: w) ^# T. I- c
Worst slack in design: -0.601( v1 ? K2 d6 \* Q
2 `1 L% [' T) T' P
Requested Estimated Requested Estimated Clock Clock
- W6 B n: k' ]% w5 L# K5 N: oStarting Clock Frequency Frequency Period Period Slack Type Group , J0 @+ j$ W8 U) x a! A
--------------------------------------------------------------------------------------------------------------------------
; S. k# t- Z3 U+ UI2C_TEST|i_Clock 293.8 MHz 249.7 MHz 3.404 4.005 -0.601 inferred Autoconstr_clkgroup_0
, d1 N* F. s( l==========================================================================================================================7 ^+ s/ v4 w6 r6 n, t) r5 u$ c
+ o6 s2 q# u9 Y: N
! M% e- W+ n' Z
Starting Points with Worst Slack9 c0 A# U+ Z% q" D
********************************0 |# C, i0 v- [9 P( y& B
2 ^( Z2 n& T" h# W7 y; O Starting Arrival 8 T+ O) z3 U: P0 W* F
Instance Reference Type Pin Net Time Slack " f8 W4 r# U* w8 u9 x% f7 E
Clock
1 `- h$ k) @+ j& f# }------------------------------------------------------------------------------------------------------------------------------------------------------------------------
% C, U: M! T/ I! _. ~UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[8] I2C_TEST|i_Clock cycloneii_lcell_ff regout NUM_SIGN_r[8] 0.255 -0.6015 [5 _1 D; I* p7 j9 V
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[11] I2C_TEST|i_Clock cycloneii_lcell_ff regout NUM_SIGN_r[11] 0.255 -0.582& I9 p- O/ o; L1 r/ a
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[1] I2C_TEST|i_Clock cycloneii_lcell_ff regout NUM_SIGN_r[1] 0.255 -0.500
: Y. m0 @+ p( yUART_Controller.Baudrate_Clock_Generator.RX_Clock_Div_Cnt[14] I2C_TEST|i_Clock cycloneii_lcell_ff regout RX_Clock_Div_Cnt[14] 0.255 -0.462, f( J& |+ A, M8 \% v/ e- p
UART_Controller.Baudrate_Clock_Generator.TX_Clock_Div_Cnt[14] I2C_TEST|i_Clock cycloneii_lcell_ff regout TX_Clock_Div_Cnt[14] 0.255 -0.462
! ]9 m: r# F" L7 c0 \0 K. j9 lUART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[6] I2C_TEST|i_Clock cycloneii_lcell_ff regout NUM_SIGN_r[6] 0.255 -0.453! a! `" K/ ?3 v0 [3 R6 p4 T) n: ~
UART_Controller.Baudrate_Clock_Generator.RX_Clock_Div_Cnt[15] I2C_TEST|i_Clock cycloneii_lcell_ff regout RX_Clock_Div_Cnt[15] 0.255 -0.4438 a- [3 k" Y% E" h W- v
UART_Controller.Baudrate_Clock_Generator.RX_Clock_Div_Cnt_i[6] I2C_TEST|i_Clock cycloneii_lcell_ff regout RX_Clock_Div_Cnt_i_6 0.255 -0.443- F( O' U; \: S9 i( f6 B: {
UART_Controller.Baudrate_Clock_Generator.TX_Clock_Div_Cnt[15] I2C_TEST|i_Clock cycloneii_lcell_ff regout TX_Clock_Div_Cnt[15] 0.255 -0.443
9 Y% S0 N$ i% C+ o) e- j$ kUART_Controller.Baudrate_Clock_Generator.TX_Clock_Div_Cnt_i[6] I2C_TEST|i_Clock cycloneii_lcell_ff regout TX_Clock_Div_Cnt_i_6 0.255 -0.443
. r k9 `1 `& t- A: @========================================================================================================================================================================: @' m9 @* H! i0 ]
! L: {! T" Z. H# F# x j+ T/ j( [1 H; }6 \' B2 V
Ending Points with Worst Slack
0 ?$ @; J4 O" |; Y6 P7 _******************************
1 H: C/ Z; V+ q( C
6 j9 n$ |7 ~2 a9 n' c% _3 O5 v Starting Required
$ p# K% R! q1 g2 ]' ]: oInstance Reference Type Pin Net Time Slack 1 a- ], T" G: B, T0 z
Clock ) ~! T7 q$ n9 M4 C {
---------------------------------------------------------------------------------------------------------------------------------------------------------
' n) v+ K+ h8 r! xUART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[0] I2C_TEST|i_Clock cycloneii_lcell_ff ena N_1768_i 2.741 -0.6017 c" m7 B* c4 l! {, j* y
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[1] I2C_TEST|i_Clock cycloneii_lcell_ff ena N_1768_i 2.741 -0.601
4 K# B7 D: J6 h. g8 ]UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[2] I2C_TEST|i_Clock cycloneii_lcell_ff ena N_1768_i 2.741 -0.601+ }( O; Z l- U6 s3 Z9 Z) g' Z2 K- v2 C
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[3] I2C_TEST|i_Clock cycloneii_lcell_ff ena N_1768_i 2.741 -0.601
5 H) M+ p0 X# z/ D$ G) E: WUART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[4] I2C_TEST|i_Clock cycloneii_lcell_ff ena N_1768_i 2.741 -0.601
" ?: @( ] m8 _; i0 q! X( H' oUART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[5] I2C_TEST|i_Clock cycloneii_lcell_ff ena N_1768_i 2.741 -0.601" t5 M" X& R7 n' t' {8 B
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[6] I2C_TEST|i_Clock cycloneii_lcell_ff ena N_1768_i 2.741 -0.601
- I, N- v- k% w4 zUART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[7] I2C_TEST|i_Clock cycloneii_lcell_ff ena N_1768_i 2.741 -0.601, g o2 V4 B$ M2 Q% B
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[8] I2C_TEST|i_Clock cycloneii_lcell_ff ena N_1768_i 2.741 -0.6016 y6 N2 ~4 G4 y1 Z# p+ ]; M
UART_Controller.UART_Transmiter.Transmite_Data_CTR.NUM_SIGN_r[9] I2C_TEST|i_Clock cycloneii_lcell_ff ena N_1768_i 2.741 -0.601
9 C6 B% ^, ~1 [" L=========================================================================================================================================================
3 B T$ s0 t* h4 t' [' F) Y* U( t2 L7 B9 E
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