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Fixed CCRs: SPB 17.2 HF021! R3 W3 y: c1 O/ D) u. G; Z' U
06-3-2017
' Y* \; f7 u( a: K========================================================================================================================================================4 L& }% y. `& Z1 G
CCRID Product ProductLevel2 Title9 _% F7 ]# s9 m4 z5 W' x
========================================================================================================================================================0 p/ k7 f1 g0 h8 p& P( R
1401318 ADW DBEDITOR Bulk Edit - Previously modified cells do not turn blue when selected
# n! X* J' [6 u* |; Q( G) f1621446 ADW DBEDITOR Bulk Edit - sorting highlights incorrect cells to mark them as changed
& D( k$ L4 @# }4 s1743997 ADW LIB_FLOW Match file for standard models is incorrect
1 |3 `0 a+ G* J! R1746052 ALLEGRO_EDITOR DATABASE PCB Editor crashes when applying no drc property
- z1 b. N' I( s9 R- X1736067 ALLEGRO_EDITOR DRC_CONSTR Interlayer checks not reporting DRCs between cline and mask layer
2 b- r0 `$ w$ b5 g* F6 f& K1738587 ALLEGRO_EDITOR EDIT_ETCH Line width changing on slide for ETCH - Conductor (Not on a NET)
1 A+ [7 j( e% g+ A" r: o% o, v6 \! ^4 P1745277 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using the slide command- N F3 P! Q: N% E
1747942 ALLEGRO_EDITOR EXTRACT Fabmaster Out does not export arc in pad_shape
/ E0 F1 X, |3 ~1737202 ALLEGRO_EDITOR GRAPHICS Setting the variable display_raster_ops
0 ]0 e$ Y* s/ n( D/ r1 j& J1744042 ALLEGRO_EDITOR GRAPHICS Unused pad suppression is not working on few nets& \/ q8 z. l- W. [ e" J; b
1703848 ALLEGRO_EDITOR INTERFACES IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty0 p) I! |2 i# c. l$ R: i1 c9 u* h
1743899 ALLEGRO_EDITOR MANUFACT Glossing dangling vias crashes PCB Editor5 j# d* Q2 S% Z' l5 ~. O
1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor
@7 j3 W" A) _/ \, N0 K% M1748520 ALLEGRO_EDITOR OTHER TDP fails to load on an empty database
n# S# f3 f% _7 _& C/ K7 V1748581 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when changing default pad geometry- [4 z4 a4 G: d: O: m3 {) V
1751469 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes/freezes when browsing for a shape symbol
' b2 v2 X7 l. G1 ~1725948 ALLEGRO_EDITOR SHAPE Shape differences after conversion from release 16.6 to release 17.2-2016
3 a' s4 S( G# [6 R, _* [+ ]& Y9 s1729306 ALLEGRO_EDITOR SHAPE Seting shape_rki_autoclip variable causes no void to be generated9 G( o) m. D0 d7 U) r" ]6 u
1698876 ALLEGRO_EDITOR UI_GENERAL Tabs are large and text is compressed in release 17.2-2016
3 K9 z9 G+ X @4 {1698883 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors
' E) [, h4 Q3 B8 g1707933 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not locating menu as per x_location
( I9 h @% ]7 x' m5 O1741460 ALLEGRO_EDITOR UI_GENERAL Right-click, context menu options grayed in some cases after choosing Edit - Copy; H& b+ G; a( f
1747588 ALLEGRO_EDITOR UI_GENERAL Interacting with PCB Editor by sending messages is not working# M" H+ E# R& W: _" a
1747488 APD EDIT_ETCH Route connect is improperly affecting existing routes in locked high speed via structures! A8 B' O1 E! A1 `7 S/ i
1750182 APD STREAM_IF The stream out settings are not saved: a Y* g& Q) @' B& }
1752067 ASI_SI GUI Links to differential waveforms do not work in Sigrity SI report- j* s" C* r+ ^* y/ t
1752131 CONCEPT_HDL COMP_BROWSER Symbol view in part manager doesn't match the symbol version% g( |2 R" k: a' Q2 j
1754116 CONCEPT_HDL COMP_BROWSER Default Symbol selected is n°2 instead of n°1 in component Browser
' z" Y7 q6 h8 B! A$ H" a- j2 u0 b1754949 CONCEPT_HDL COMP_BROWSER Part Information Manager displays preview window with the wrong symbol and missing footprint5 a0 L+ d+ m" J
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic; I, I$ Q, p. b& c1 n$ u) Y
1750916 CONCEPT_HDL CORE DE-HDL crashes when trying to uprev a project in release 17.2-2016
+ W' e) a$ H! ]% t8 \" ^3 Z- E& M1711487 CONCEPT_HDL INFRA Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design" v2 t9 ~( N+ b7 I( r2 T
1746915 CONSTRAINT_MGR CONCEPT_HDL Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow
5 B) d7 S+ m/ [% p3 D1743523 CONSTRAINT_MGR DATABASE Suppress warning pop-ups from the constraint automation script3 w/ f4 g6 e; a
1746941 CONSTRAINT_MGR UI_FORMS 'Go to Source' from DRC tab is not working in release 17.2-2016
% i9 l- O- R7 R: d+ `6 h* S1753010 ECW METRICS Metrics not getting collected due to old license in use0 `% `, }. c* H% w
1713052 FSP GUI Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance
2 A5 d/ Y6 M' |% u2 T1719099 FSP GUI Net naming wrong after building block
: }! w7 N, b8 h1 d- C4 ~/ u% g" `1719105 FSP GUI Tabular sorting not working in FPGA System Planner
; h) {- Q+ N: ]# }# m' M1720479 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems* J7 m2 t; u9 c8 x) N1 C4 |' ~. a" D
1723411 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems
1 b. z2 }$ t/ r# Q& L' M1746628 PSPICE ENVIRONMENT PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016' J2 e& s+ p) S$ x* Q% y
1745976 SIG_INTEGRITY GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing) p) E1 g9 @/ o' N$ y) z! ^
1690820 SIP_LAYOUT PLATING_BAR Cannot add fillets to pads with plating bars in release 17.2-2016
- ?. G+ R% @% j+ P3 T3 d: O6 Q" m1725042 SIP_LAYOUT PLATING_BAR Creating a plating bar removes dynamic fillets
/ u8 j* g; _' W$ `0 I) z# e, E t8 k1747534 SIP_LAYOUT SHAPE Moving fiducial crashes SiP Layout' H( T$ t2 ^2 V
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发表于 2017-7-2 18:37
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发表于 2019-2-27 16:42