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Fixed CCRs: SPB 17.2 HF021( T0 Q- C- {2 E0 F
06-3-2017
; F& {$ C5 n7 Z1 _! h========================================================================================================================================================- e6 {' Y- O! N5 K& Y# {
CCRID Product ProductLevel2 Title
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. M+ Q9 l4 C( c+ D8 M5 ^1401318 ADW DBEDITOR Bulk Edit - Previously modified cells do not turn blue when selected3 M4 E) J3 r- ]/ \) S& l
1621446 ADW DBEDITOR Bulk Edit - sorting highlights incorrect cells to mark them as changed" v, q+ F1 d% j. e7 Z: p
1743997 ADW LIB_FLOW Match file for standard models is incorrect
# ]6 R$ j/ u- J- ^1746052 ALLEGRO_EDITOR DATABASE PCB Editor crashes when applying no drc property
" U. `9 I$ Z9 b" D4 z- E1736067 ALLEGRO_EDITOR DRC_CONSTR Interlayer checks not reporting DRCs between cline and mask layer5 q/ U/ I% m! S
1738587 ALLEGRO_EDITOR EDIT_ETCH Line width changing on slide for ETCH - Conductor (Not on a NET)% c" ?. l- A8 F m
1745277 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using the slide command
: y& D8 q+ z, m+ w5 {6 i4 ^2 U6 M6 b1747942 ALLEGRO_EDITOR EXTRACT Fabmaster Out does not export arc in pad_shape
' V* @2 D0 B0 r* M. D, V z0 t1737202 ALLEGRO_EDITOR GRAPHICS Setting the variable display_raster_ops
7 O4 F$ _; @4 }' g G; q) }- k1744042 ALLEGRO_EDITOR GRAPHICS Unused pad suppression is not working on few nets& l2 o5 c, _# U2 v! L& m
1703848 ALLEGRO_EDITOR INTERFACES IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty4 E6 P- V2 I8 x
1743899 ALLEGRO_EDITOR MANUFACT Glossing dangling vias crashes PCB Editor
, x0 [6 F; H( V1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor5 d# `* M, q2 V. Q% p; ^) D$ ~
1748520 ALLEGRO_EDITOR OTHER TDP fails to load on an empty database5 A7 K1 E% }; k* R6 ?; d, z2 d+ d, P
1748581 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when changing default pad geometry
+ k8 k! }5 k! c. B1751469 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes/freezes when browsing for a shape symbol8 Q/ H- Q0 K$ [1 j- v
1725948 ALLEGRO_EDITOR SHAPE Shape differences after conversion from release 16.6 to release 17.2-2016
6 s v$ [* K3 ^+ t1729306 ALLEGRO_EDITOR SHAPE Seting shape_rki_autoclip variable causes no void to be generated" r: @# m/ ?, y, U6 ^! |
1698876 ALLEGRO_EDITOR UI_GENERAL Tabs are large and text is compressed in release 17.2-2016
0 d3 w0 T. m8 w1698883 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors7 \6 g5 h9 a; \5 U$ e; }
1707933 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not locating menu as per x_location' E* J8 c+ ^- G% b
1741460 ALLEGRO_EDITOR UI_GENERAL Right-click, context menu options grayed in some cases after choosing Edit - Copy$ m) l& E9 s2 P) x3 N; a9 E! l
1747588 ALLEGRO_EDITOR UI_GENERAL Interacting with PCB Editor by sending messages is not working2 [1 `0 H; l7 o
1747488 APD EDIT_ETCH Route connect is improperly affecting existing routes in locked high speed via structures8 ?2 ]- U" K. B+ |% Z. Z
1750182 APD STREAM_IF The stream out settings are not saved1 u" `1 S9 B6 l* [" b/ y+ {& Q! G
1752067 ASI_SI GUI Links to differential waveforms do not work in Sigrity SI report
) T0 ^5 b/ x2 A$ o3 i1752131 CONCEPT_HDL COMP_BROWSER Symbol view in part manager doesn't match the symbol version
# q' R6 E( r, I1754116 CONCEPT_HDL COMP_BROWSER Default Symbol selected is n°2 instead of n°1 in component Browser8 y8 p) x' J' G" E6 r w2 ?2 x
1754949 CONCEPT_HDL COMP_BROWSER Part Information Manager displays preview window with the wrong symbol and missing footprint
; H* ?8 S) p2 \+ G) o! H# p2 }1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic
/ t1 a, e9 K& G# G- |1 ^; |2 C1750916 CONCEPT_HDL CORE DE-HDL crashes when trying to uprev a project in release 17.2-2016
" I1 \+ ]8 r, b, h- ]4 T1 j, _+ o1711487 CONCEPT_HDL INFRA Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design
# k. \8 |: v& h1746915 CONSTRAINT_MGR CONCEPT_HDL Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow5 h) X: |. N5 e7 E9 t5 ]
1743523 CONSTRAINT_MGR DATABASE Suppress warning pop-ups from the constraint automation script3 c7 V E" ^# Y- X, G" R5 z
1746941 CONSTRAINT_MGR UI_FORMS 'Go to Source' from DRC tab is not working in release 17.2-2016 g) T8 q0 L9 V2 J: K; _# b
1753010 ECW METRICS Metrics not getting collected due to old license in use
) @8 E O0 X9 r J; a4 F0 P1713052 FSP GUI Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance! O7 u' R4 y2 |& ]7 V
1719099 FSP GUI Net naming wrong after building block) O% u. b) a( Z$ z' Q( C$ t5 w
1719105 FSP GUI Tabular sorting not working in FPGA System Planner
* p" j' r7 Z. ]4 ~+ [1720479 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems
5 u2 Q; t! @# K% W/ y1723411 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems/ G" Q5 m4 p$ _
1746628 PSPICE ENVIRONMENT PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016
8 D6 f9 Y4 t- w% U1745976 SIG_INTEGRITY GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing% j4 |/ A3 T! u! o& q3 t9 M
1690820 SIP_LAYOUT PLATING_BAR Cannot add fillets to pads with plating bars in release 17.2-2016
( F. Q9 d! t- q7 |5 a/ O% Q1725042 SIP_LAYOUT PLATING_BAR Creating a plating bar removes dynamic fillets
/ T& ^7 }9 A3 K; |1747534 SIP_LAYOUT SHAPE Moving fiducial crashes SiP Layout
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发表于 2017-7-2 18:37
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发表于 2019-2-27 16:42