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Fixed CCRs: SPB 17.2 HF022) R- o. y4 e" F0 F; n/ s
06-16-20170 L8 P0 ~; \4 R+ I2 u- i! P/ ]3 Y( @
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CCRID Product ProductLevel2 Title/ p, u) M7 Y+ v
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1755789 ADW DBEDITOR Checking in HSS Block returns 'Failed to create archive'# j; T- j, R0 e q
1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager
. @; k/ }- M8 Y q4 I1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager
6 T* b4 I* u/ E/ v L1744081 ADW FLOW_MGR Error regarding configuration file when trying to open Workflow Manager! F' Z) e& L5 g! W/ Y
1756727 ADW LIBIMPORT EDM Library Import fails with java exceptions when merging classifications
9 x( p1 I7 r$ M$ J2 s, \" r1743763 ADW SRM Find filter is grayed out when Allegro PCB Editor is opened from EDM Flow Manager Y) }$ e7 w4 ?* l3 J8 Y z
1748399 ALLEGRO_EDITOR DATABASE In release 17.2-2016, end caps not visible for certain clines in PCB Editor
% A( ~3 j8 T5 V1 d6 z9 w1748522 ALLEGRO_EDITOR INTERACTIV A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it
0 r' Y' G( o+ q7 b1734983 ALLEGRO_EDITOR INTERFACES Secondary step model does not stay mapped after drawing is reopened8 e' z' Q8 X6 A. Y' @
1753704 ALLEGRO_EDITOR REFRESH Refreshing symbols crashes PCB Editor( O4 M# L1 w5 N7 p
1493721 ALLEGRO_EDITOR SHAPE Voids on negative planes are not adhering to constraints
- p: k. h/ \6 ?. K* o( z A3 o; Q1711242 ALLEGRO_EDITOR SHAPE Route keep out leads to partly unfilled shapes with gaps
/ t5 G/ B# h9 [; h1726865 ALLEGRO_EDITOR UI_GENERAL Pop-up Mirror command does not mirror at cursor position
8 {! ^0 {6 H- X1752987 ALLEGRO_EDITOR UI_GENERAL axlUIViewFileCreate zoom to xy location not working while in user created form.8 N# Z" W. e; F/ j/ \$ \8 e
1755638 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run7 g3 ^* u q8 b% E [1 F8 }
1719792 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC hangs or crashes PCB Editor# J$ x% R- ]( X5 x. A+ G! p! c/ J
1624869 ALTM_TRANSLATOR CAPTURE A structure file is required to translate a third-party schematic to OrCAD Capture5 V( P6 K: _- K# S
1707416 ALTM_TRANSLATOR CAPTURE Missing components and pins in the OrCAD Capture schematic translated from a third-party tool
% L0 m8 |/ Q: L5 ?1708825 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate the schematic
3 B0 a+ _/ |2 G8 O) ~. K6 ?1719200 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate all the pages of a schematic# g6 d% Y: H1 x5 g4 ]6 g" f8 }
1546070 ALTM_TRANSLATOR CORE Third-party to DE-HDL schematic translation fails7 E' m7 ?2 F1 l, g; Z+ ]: {
1700508 ALTM_TRANSLATOR CORE Third-party PCB translator does not work in release 17.2-2016: k7 p* R# p. K( u
1699340 ALTM_TRANSLATOR DE_HDL Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor6 J1 }4 _( g' g. B
1630379 ALTM_TRANSLATOR PCB_EDITOR Third-party translator is not importing clines and vias$ c3 w* Z/ n5 l; z4 O1 R
1708615 ALTM_TRANSLATOR PCB_EDITOR All items of third-party PCB not imported in release 17.2-2016
. T* y# I- ^& [1758296 APD DXF_IF DXF OUT: Rounded rectangle pads mirrored incorrectly
E9 T& p) A, m5 P; E3 _5 Q# r1756040 APD IMPORT_DATA The 'die text in' command ignores values after the decimal point% m5 _9 k7 M5 ]3 j3 c( u2 a2 u
1727206 APD SHAPE Merging two shapes results in an incorrect shape) @9 J: T* y: y# z/ m
1753682 CONCEPT_HDL CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL
7 V. i/ p6 z+ G1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic
, z0 @+ Y, q: R2 T& C8 s6 P1747559 CONCEPT_HDL CORE Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)6 D% I: h* F$ S. h+ I
1749644 CONCEPT_HDL CORE In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes
" I, Y2 l' A- \) [: A, z1746910 CONCEPT_HDL GLOBALCHANGE Global Component Change unable to identify part data when using schematic pick option7 J6 x2 A5 s! l) e
1743572 FLOWS PROJMGR Project Manager displays incorrect values in Project Setting! g2 g$ ?+ [) r; Y5 r" j0 L& u& w7 V
1724124 FSP DESIGN_EXPLOR Provide TCL command to filter design connectivity window
8 ?5 c) S& ~$ B% q1719105 FSP GUI Tabular sorting not working in FPGA System Planner/ U$ `9 M. F( x8 j
1755750 PCB_LIBRARIAN GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor
# X6 P G8 D6 s+ y1 e6 O1722993 PCB_LIBRARIAN IMPORT_CSV Part Developer crashes while importing part information stored in a .csv file
6 V' r- ]- d& c1758856 SIP_LAYOUT 3D_VIEWER Correct the spelling error in the 3D Viewer Design Configuration window
# \6 _, a; Q% {4 f' k/ U, ?1755179 SIP_LAYOUT ARTWORK PCB Editor crashes when creating Gerber files9 m' R8 }) G7 _7 k% Z/ Q
1743511 SIP_LAYOUT MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check |
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