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Fixed CCRs: SPB 17.2 HF022
( ~5 ]% Q8 }* q06-16-2017( W5 b! m. a8 X
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6 V9 p5 N9 e2 A% i- G- HCCRID Product ProductLevel2 Title; v9 c9 ^4 q0 w6 n' P' `% |
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; Q7 A8 F4 f: U; H8 Q. @6 m& t* p* A1755789 ADW DBEDITOR Checking in HSS Block returns 'Failed to create archive': V' k$ }5 i' a
1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager% r( d) c7 M6 M4 G# \- G' O0 ~3 x
1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager
3 K$ M& q3 U4 h1 K! J, l1744081 ADW FLOW_MGR Error regarding configuration file when trying to open Workflow Manager) N, F1 | S$ |" d
1756727 ADW LIBIMPORT EDM Library Import fails with java exceptions when merging classifications
; U7 T* Z `! D3 i2 i9 a9 X: [% @) J1743763 ADW SRM Find filter is grayed out when Allegro PCB Editor is opened from EDM Flow Manager7 I+ j7 d+ w. a d" x o# I
1748399 ALLEGRO_EDITOR DATABASE In release 17.2-2016, end caps not visible for certain clines in PCB Editor- I `2 r" z" h& _
1748522 ALLEGRO_EDITOR INTERACTIV A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it1 I& L) A! }" K; l" Z1 t0 d( I
1734983 ALLEGRO_EDITOR INTERFACES Secondary step model does not stay mapped after drawing is reopened
% j# v s) y2 j2 h4 u1 ?1753704 ALLEGRO_EDITOR REFRESH Refreshing symbols crashes PCB Editor; ]5 e2 A* y4 N3 z6 z: q2 |" c2 P
1493721 ALLEGRO_EDITOR SHAPE Voids on negative planes are not adhering to constraints$ X: K: O# o5 p3 _
1711242 ALLEGRO_EDITOR SHAPE Route keep out leads to partly unfilled shapes with gaps5 `/ Z) ^- W0 B& G# U2 o( p% m
1726865 ALLEGRO_EDITOR UI_GENERAL Pop-up Mirror command does not mirror at cursor position: ?$ |+ z C5 d: Y. l4 U
1752987 ALLEGRO_EDITOR UI_GENERAL axlUIViewFileCreate zoom to xy location not working while in user created form.( i; X0 e- U1 i
1755638 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run
$ h" |1 V$ ~6 Z& o; v4 g- `1719792 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC hangs or crashes PCB Editor
$ W; q2 t) x, g R$ E2 u6 |1624869 ALTM_TRANSLATOR CAPTURE A structure file is required to translate a third-party schematic to OrCAD Capture
+ v& D( _. i' L8 D g I$ @9 \1707416 ALTM_TRANSLATOR CAPTURE Missing components and pins in the OrCAD Capture schematic translated from a third-party tool
& P0 W! P0 k: K$ f0 [ S9 l/ _* z1708825 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate the schematic: J) B" E, k- Y' x9 ^6 |, E0 `
1719200 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate all the pages of a schematic
' r# \4 i- P$ }/ i( M5 {1546070 ALTM_TRANSLATOR CORE Third-party to DE-HDL schematic translation fails2 w/ V% D& g3 {
1700508 ALTM_TRANSLATOR CORE Third-party PCB translator does not work in release 17.2-2016
9 Y( I' \) Q: ?& Z! X& y, q/ H1699340 ALTM_TRANSLATOR DE_HDL Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor/ l7 z+ v+ ~" F: c
1630379 ALTM_TRANSLATOR PCB_EDITOR Third-party translator is not importing clines and vias, ?- g# a: H# m" J$ ?( y: |
1708615 ALTM_TRANSLATOR PCB_EDITOR All items of third-party PCB not imported in release 17.2-2016! | m, ?1 ^/ a" @4 l
1758296 APD DXF_IF DXF OUT: Rounded rectangle pads mirrored incorrectly
8 P+ ?4 s5 w( j1756040 APD IMPORT_DATA The 'die text in' command ignores values after the decimal point
! y. G6 I" K% }1727206 APD SHAPE Merging two shapes results in an incorrect shape" r3 c9 [7 @# Z, M7 f
1753682 CONCEPT_HDL CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL
0 C5 }" k7 I7 N7 l9 C `1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic) I2 q+ ?3 G2 b! c! a$ q
1747559 CONCEPT_HDL CORE Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)
" f5 |2 R0 `: E' J4 `1749644 CONCEPT_HDL CORE In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes8 y. n1 w# x p# Z; w! h% o3 J
1746910 CONCEPT_HDL GLOBALCHANGE Global Component Change unable to identify part data when using schematic pick option
& z. S2 ^! p4 {1743572 FLOWS PROJMGR Project Manager displays incorrect values in Project Setting' k; Z5 E2 |7 R: W
1724124 FSP DESIGN_EXPLOR Provide TCL command to filter design connectivity window
9 j# c" R" O" [, r3 {1719105 FSP GUI Tabular sorting not working in FPGA System Planner
1 G" s( Y# l: L# T1755750 PCB_LIBRARIAN GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor2 \' ~! O, b# P: ]
1722993 PCB_LIBRARIAN IMPORT_CSV Part Developer crashes while importing part information stored in a .csv file/ c& j% Z0 r7 W! N8 e; O, W
1758856 SIP_LAYOUT 3D_VIEWER Correct the spelling error in the 3D Viewer Design Configuration window" O* f+ e# O: V3 x4 ^0 J' z
1755179 SIP_LAYOUT ARTWORK PCB Editor crashes when creating Gerber files
7 A' m) ?5 _: c& a( ^1 R1743511 SIP_LAYOUT MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check |
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发表于 2017-7-2 18:36
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发表于 2017-7-2 19:07
