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本帖最后由 紫菁 于 2017-9-14 16:05 编辑 . G4 R7 k: ?1 Z- i) p
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转 Hotfix_SPB17.20.015_wint_1of1
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& X, Q5 y) g8 n; E8 vFixed CCRs: SPB 17.2 HF015
# t* B1 m6 g5 }; [. c: }03-16-2017
0 b( {6 q6 ]9 U8 y3 u) U% K; n1 l========================================================================================================================================================
* {3 }' r$ B/ g# n0 ICCRID Product ProductLevel2 Title
1 @8 h. r; S/ `& a7 x# f! c========================================================================================================================================================
. R* ^0 F% [6 T% D( W3 S1653366 allegro_EDITOR INTERFACES Unable to attach step model to symbol R/ B" k: G+ m/ r2 \/ E$ l9 V
1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model
7 ~7 p- r5 Q& C6 d5 ] ?& [1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function2 {1 A% n& J$ c& v
1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file' v+ j/ @4 ~! T! S" T
1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting padstack Editor results in incorrectly scaled forms
* h* E* V- K% P0 z7 n5 u/ m4 K) J1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design& v) N/ R- C* D/ M
1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees
. @; i' W: L. X4 X1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.
& i5 |# {% h6 L9 q; l+ O1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously1 s9 y" F' }( g# U' f1 t
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
1 D8 P. M/ F J( @/ ]. g! I! a! T1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
3 @ j) P& Z! Z8 x O$ z1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used
1 D! l6 l- Q; A$ E1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places9 ]0 O# B ^! w5 b. a \3 ^
1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value5 t( G1 d c- L' A6 g
1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
0 _! y& {; f+ {, D7 I+ o# K1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad
: `' G; E5 a# D( X$ U; X1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout
6 t3 D; k7 t* A1698697 concept_HDL COPY_PROJECT Copy project corrupts the .dcf file& ?( l7 Z" J. B' |3 ^4 v2 y
1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 0844 `+ q, E- f) N
1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position
% y2 n4 |7 c' z* S% l" Q3 O' a1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net
. {0 U% G0 D( e5 }2 y' v1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer
) E" w- N' p r- X/ d1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation0 p$ K4 V9 l+ \% j3 w
1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates3 D7 } m2 {- G
1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode
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* r0 w9 R7 L- ]0 R. _8 c转：Hotfix_SPB17.20.014_wint_1of1.exe 链接：http://pan.baidu.com/s/1jHFB2Pg 密码：mxnk2 F4 i4 c6 r" g7 O
Fixed CCRs: SPB 17.2 HF014
& |" K" D) H$ [ B/ |2 j========================================================================================================================================================$ B, n% S- R5 \- J6 h# r
CCRID Product ProductLevel2 Title
: ]% r# H* P( D3 c, W========================================================================================================================================================
" }5 }& s$ y8 k/ c! g1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships
" y4 w& C" t* W1 K1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity" \! o( P! O9 N+ w/ z2 Z" A% }
1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-2689 ~4 v* i0 W% R; O1 ?/ }( b( {
1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data u1 m: A* v7 n1 J U4 z9 \, Y1 d; u
1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data, ^$ G" q- @% }: Z5 W
1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors
, y% {0 q7 d5 {5 ?( C' n1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.
4 ]7 m7 G( X& u& w1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted
& ]$ ~( ~% [6 {3 z* f4 m1 V1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location- A6 u) A" i6 U- t4 p
1685995 ALLEGRO_EDITOR skill All film sequence numbers are returned as 0 when using the SKILL function axlGetParam
7 g* A: O* k/ `1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately
4 ?- }. [$ e1 e# H# c1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6
# Q2 v1 M0 g. ]4 p1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one! G8 @. r! N! x0 v3 C& w4 f) l
1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled
6 w! i u2 r$ a2 |9 W7 g1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved
% ]$ I+ L" p2 y# J) [1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components2 {" E t! L2 P7 s
1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers5 v" n0 t* S m9 W9 `
1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase1 ]$ u# [5 Y" \1 h ^8 N3 Z, |
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement* D9 v, K7 Q$ a, L
1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message8 C) i0 t# w) m) @- i/ m$ [
1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011
# x. l3 ]5 C" v) A, b1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2
' F0 o( L J% f7 m$ J1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers
- j5 F9 y# S, \1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016 t0 s/ v- ~0 } O/ P
1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design
2 P1 O: ]6 q- p3 ]/ s9 R3 |6 O1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors5 M# R4 C1 ]) [7 j( V) {
1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters
3 l1 x9 K: e8 j! A5 G( N* O& X _# h1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP! c; J4 e/ j9 j' C
1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'
8 T7 z! I) A5 t( R2 y1705265 INSTALLATION DOWNLOAD_MGR Problem installing orcad Library Builder from Download Manager6 y# b$ c; p C) @
1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script+ n: ], C) k, O M! K4 |" F. n
4 H( ]- s6 S) k" [0 Xcadence OrCAD and Allegro 17.20.013 Hotfix链接：http://pan.baidu.com/s/1kVmHGZ9 密码：smsv' f: U ~$ Z; T/ ^
Fixed CCRs in SPB 17.2 HF013
: O. }) A. h+ r1 ^3 ?, a========================================================================================================================================================
* |, F+ L7 A Z4 ?6 @CCRID Product ProductLevel2 Title, c7 b) J3 q) ], v) W
========================================================================================================================================================
% h3 H+ H" Z; ^/ g3 `- P1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm* C1 _4 O2 I# V9 M" ]7 G2 c6 H1 H
1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer. q8 q% H% j; @8 G; }( H* k
1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
* G! J! G1 a0 c# _1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated1 W& ]7 R, m; s
1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated+ _( k% U' J+ F5 H _% l" d, U- v" Z
1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board
, `# b! d( d4 }* x1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor# d4 C1 Z! e" U- ]: P7 E
1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol
. t" L3 k' Q, m% V3 ~+ M% L1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not: R( p5 k. `- V* t, B6 E
1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components
- Q$ T ^6 m$ G) f# X6 z: m1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components
* B9 G* O1 v6 _7 h% e0 {/ b' z1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets
- t, r3 M2 r4 N1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets
% V+ m' ?# ~- |* R& [- d1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF
" S# G+ T+ M" s' A1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement
/ n# S0 V/ ?, J% _3 s* U$ p1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.) q ]* u% n+ ?0 Z5 k
1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file" q) j0 F8 q4 x3 D1 d, ?, K
1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.
8 a5 u7 {, P4 l1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker
; U' h! s% E9 z: ^6 T" B _1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates
: w+ I* q; o, Q8 v1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes, _5 U' q6 N( G) D, b$ Q+ t! b
1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.
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发表于 2017-2-26 17:05
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发表于 2017-2-26 20:26
