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本帖最后由 紫菁 于 2017-9-14 16:05 编辑
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, @& t6 _% U2 K( T, u9 c转 Hotfix_SPB17.20.015_wint_1of1- \. I. J9 ?- I) G1 E
! S* I* I, _ R4 T* oFixed CCRs: SPB 17.2 HF015
) E, `3 v/ \6 X" K$ C0 \7 \03-16-2017- K; \! j; a+ m
========================================================================================================================================================! x. |1 I9 a/ j
CCRID Product ProductLevel2 Title" Q+ M0 @% ? O$ W4 y
========================================================================================================================================================
9 f! L, m0 p2 Q" x; R8 b1653366 allegro_EDITOR INTERFACES Unable to attach step model to symbol8 X! Y( M8 C' n$ b
1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model! R) J8 V, X$ Q; _! ]. }
1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function$ [ m8 T/ k" `1 F4 _2 V+ Q+ N
1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file
% [, i1 ^/ U/ O" `1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting padstack Editor results in incorrectly scaled forms
1 E7 g7 i" w) }; [' r- H3 ?; z1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design; o$ R& H6 ~; L
1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees* S+ ~% Y: _0 Z8 @- a5 f
1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.5 h! E/ O9 y' g" i, C, k2 }+ i
1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
8 R, n3 o& ?2 m& k9 F1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
" L- O( m, O O7 O1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not: p. @6 C3 U9 C# p+ z3 m3 v' ^
1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used
+ ` e# f0 P$ p# A! o/ e8 h1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places) S# Q( t% M: ?/ p
1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value6 q) u5 D- X+ f% H3 c6 d# \
1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
- J3 \2 a9 \% v9 l1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad) L' Z+ ^) q5 l0 W3 S
1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout
. }& q. Z6 m5 p! W/ u) o1698697 concept_HDL COPY_PROJECT Copy project corrupts the .dcf file- M6 ^7 _* v/ U3 y4 _9 g
1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084, P9 \& `( \& G
1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position" E. A$ V% Y8 `6 x
1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net3 H; `0 y% z# ^' p2 Y
1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer
3 c7 C2 G, a' a+ D m. J* b: Q1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation+ z2 H& M6 |( c* ? ^. C' o
1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates0 k2 S9 i$ t- h% R& F
1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode
) R8 c# H3 I% ]
3 h- W4 S4 Z, D# g8 p9 ~转：Hotfix_SPB17.20.014_wint_1of1.exe 链接：http://pan.baidu.com/s/1jHFB2Pg 密码：mxnk
1 B& W9 M. \9 m u2 L4 E8 Y, ]Fixed CCRs: SPB 17.2 HF014
' E1 u1 S& `; e6 C/ p========================================================================================================================================================
3 V1 F! W B9 n, H8 p8 q4 G! qCCRID Product ProductLevel2 Title
7 Y6 L- t: a/ y% y- j- U! \========================================================================================================================================================2 e& n' |0 _! N
1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships$ s# U$ u/ ~0 @4 g9 \, y6 L! l3 p2 p! p- h
1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity2 V. ^9 s; n6 w( w
1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-268! T( B: R5 z- q7 _1 Q: S3 }
1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data t( p3 W: c+ b/ g( K6 n! V4 w/ Z9 ^
1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data
1 w/ J* t0 e; {9 _, M) C1 m1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors
+ a# s. b! N1 S# H1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.
0 m. e! e% O7 ]: k% B( R; a6 g1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted5 p6 e- v1 N) h/ s" A; q% F* z
1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location
+ l( {% y7 L4 t1685995 ALLEGRO_EDITOR skill All film sequence numbers are returned as 0 when using the SKILL function axlGetParam
; s# C4 Y& T7 s y$ I! [1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately; ?- P% @; ^2 Y3 D9 s5 H
1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.62 X+ G7 ]% n8 ^5 S; h
1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one% U! x! m, E5 x, ]/ T% a& q" J3 `0 o
1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled
, P4 k# J* C) J- }7 t1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved
) S7 H/ P5 O o" d1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components* f; O) A4 m+ s. r" v- W. y
1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers" f* N% |) o6 n" @
1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase" Q; x# Z/ u9 L% D; o& |
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement
' s; i; f3 ^4 W' T1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message" K h) d4 L6 B" H" m; q2 G
1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011
+ i u( m3 o' I. D! e) ~ ]1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2
& t! I7 o" P, \1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers! m1 O) C6 v0 M6 ]' s: d3 s
1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016
# Q( ^2 A3 F i! x. K1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design5 d/ }8 B$ ~2 ?3 N+ m
1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors
/ l% A) V. }" W! m7 t1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters
* W7 A3 y& i- e" O) g- g6 M2 }1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP0 D1 K8 w6 j- i3 m
1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'0 D5 T7 w. Z% X# _4 U4 k
1705265 INSTALLATION DOWNLOAD_MGR Problem installing orcad Library Builder from Download Manager
7 ]8 C3 T( o& G/ f! r' w) `1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script. h9 Q6 e7 d# [# ?. j
; g( S) F1 }4 ?7 Jcadence OrCAD and Allegro 17.20.013 Hotfix链接：http://pan.baidu.com/s/1kVmHGZ9 密码：smsv V9 ]; ~1 O2 q1 k7 d9 A
Fixed CCRs in SPB 17.2 HF013
9 S6 W) G& M- I3 C; v- {========================================================================================================================================================; M) Q" N |! D" E' J! A X- E. V
CCRID Product ProductLevel2 Title& L( B. p9 i' J
========================================================================================================================================================0 h9 `& q! a& h+ ^ t( \! @1 ~
1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm
5 y. r& q2 ?. G, X1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer. h) c7 |: ^, P; _
1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version3 |2 i) N; ~' g
1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated5 n$ H ? N; |0 t. r
1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated9 k' L+ ?* d! Q2 m* P& ?0 i
1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board0 [0 p$ Q0 F& u
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor* D3 V2 Q" G5 Q, W0 k: H/ g
1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol2 B! Q7 v" A# h0 P: m; N2 S; J
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
9 t8 c$ a3 b7 b; m2 J1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components
$ ?5 v6 C6 U7 Y1 C4 M* `1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components) X2 n: W: _, R& x
1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets' I5 M( p) @/ ~4 N" v) x
1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets/ l4 b9 f; z. c
1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF
5 h7 }% V/ V n" _; b$ a1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement- |5 Q! \& e6 ^. h# M
1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.
+ D" {0 X- ~6 j" U1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file2 ?9 V8 O8 O% I4 a: q5 g, u' a
1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.
8 G4 R( T: [$ h8 ? I1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker4 a" p/ o3 u+ n& z9 a9 E& y
1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates$ P$ v" I; Z8 K9 ?2 k
1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes
0 l2 t/ {3 Z; k9 o0 _( X6 T0 C1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.( C) {. f" @* e" `9 `' r3 N0 ]
; a7 m. v, u ~ p1 |$ r6 ~9 q% Q$ ~: y7 T/ L* i! t' j* j$ K1 M
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发表于 2017-2-26 17:05
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发表于 2017-2-26 20:26
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