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LBSALE[10]LBSALEMIXED-SIGNAL AND DSP DESIGN TECHNIQUES$ z& t. ?$ W7 X9 r/ }- V$ q
SECTION 1
7 v) K. i2 A. J$ v# E4 ^INTRODUCTION
0 R( |. U* l" _* ^" Q- wSECTION 2" G' q% R( S, B5 y$ P2 i V
SAMPLED DATA SYSTEMS2 m* I D3 I0 [5 P
Discrete Time Sampling of Analog Signals
4 H2 p* p6 K" {+ y4 L ADC and DAC Static Transfer Functions and DC Errors
* v# Z3 J& ]& Q$ Y8 F$ j+ Q! R, F* \) S- L AC Errors in Data Converters
* q8 B: i' ?0 @( d! T DAC Dynamic PeRFormance8 a1 N1 O! b" |# S: T- a6 Y0 h
SECTION 3
' a9 I0 z, A1 o5 g: W& _ADCs FOR DSP APPLICATIONS
1 l& R* {+ Q0 Z Successive Approximation ADCs) x: d# |& r& [% t3 l3 m. D+ [
Sigma-Delta ADCs: o3 U/ F/ S, [: l
Flash Converters( J9 d9 N4 b0 }2 K6 Q
Subranging (Pipelined) ADCs
- p5 j" R+ ~9 { Bit-Per-Stage (Serial, or Ripple) ADCs2 ?8 D i! \% I8 H& o! C) z2 r* T$ T
SECTION 4) h9 B1 w& Q- a% X
DACs FOR DSP APPLICATIONS3 ?, T4 ?2 C' I2 D
DAC Structures* p% ^. L6 l! H& {& B' `
Low Distortion DAC Architectures
+ H0 ~5 [% p6 g1 @' M" F7 l DAC Logic
, r1 O" V2 j3 `) C! A Sigma-Delta DACs
! n$ H( Y+ _1 V4 S6 P9 P& d Direct Digital Synthesis (DDS)0 I& R" Q8 e/ p+ `+ @, j8 w u
SECTION 5
( H1 q" `" a! E' Q/ S; w" mFAST FOURIER TRANSFORMS
! n( a3 k/ B3 y# s0 J7 e3 h; G The Discrete Fourier Transform
, ~& Q/ h) S; S6 v The Fast Fourier Transform! ]6 I7 k* U! e4 U T7 \3 g" Z
FFT Hardware Implementation and Benchmarks4 E3 B; _ u2 M+ J, Z9 r9 Q
DSP Requirements for Real Time FFT Applications
$ @/ U1 c6 ` [4 w2 m Spectral Leakage and Windowing
+ B; Y, K! o) p9 @) T+ U/ N7 X9 PSECTION 6
7 s$ H6 X" I4 v' B0 NDIGITAL FILTERS
' q" {7 ]: u" W: C0 O7 x Finite Impulse Response (FIR) Filters" O0 a- e/ L/ f+ B4 d F7 ^
Infinite Impulse Response (IIR) Filters) P3 f3 A6 o: L: p
Multirate Filters9 u( R: @. ?* A
Adaptive Filters
8 R! C7 z8 a1 q- {SECTION 7
! _% u0 ^% J. v" ^DSP HARDWARE& x* }5 T V( j2 `$ O
Microcontrollers, Microprocessors, and Digital Signal
; I8 J8 X$ t! U( X& Q8 ?Processors (DSPs)8 I9 q+ J0 P+ j' m
DSP Requirements
+ _( c" u/ k/ ]) d% X ADSP-21xx 16-Bit Fixed-Point DSP Core
( O6 t8 O7 M/ l0 V$ C Fixed-Point Versus Floating Point
7 c: {% s% D$ C7 D8 E2 P ADI SHARC® Floating Point DSPs
$ N- M8 f2 u1 D5 W. S# k9 z/ i# B ADSP-2116x Single-Instruction, Multiple Data (SIMD)# G1 Z1 }' @* Q7 ^2 L8 p( E& q& q" H
Core Architecture. N$ l7 b$ g/ S* ]# m
TigerSHARC™: The ADSP-TS001 Static Superscalar$ Q2 l& ]8 U) `
DSP9 \* Q$ J4 N9 T
DSP Benchmarks b' A! |; _7 J
DSP Evaluation and Development Tools
! D# ^0 E ~; D+ }1 W, Q LSECTION 8
: ~& }9 J0 U5 Y3 r0 f7 VINTERFACING TO DSPs' Z5 r, C. Q) _$ w. ^3 h2 K
Parallel Interfacing to DSP Processors: Reading Data5 c" I4 j6 ~0 h5 f; z
From Memory-Mapped Peripheral ADCs9 Q# N0 L- D, n& A) f9 ~
Parallel Interfacing to DSP Processors: Writing Data to
; n8 s( R3 X$ ~& f2 aMemory-Mapped DACs' s8 `4 R$ M1 U
Serial Interfacing to DSP Processors
% G( }% c# R5 [( U$ } Interfacing I/O Ports, Analog Front Ends, and Codecs to
2 e8 B( h" w; dDSPs5 `. N/ T5 x4 U8 H2 E! C3 o
DSP System Interface
# h, W$ v1 x4 K: K7 \6 m( ~SECTION 9
# q% U' v, ~3 Z* kDSP APPLICATIONS) ~) w m, D& K! }* Q; z
High Performance Modems for Plain Old Telephone
$ F! _6 u3 ^0 ~7 A9 \8 Y! B: K: |, @Service (POTS)
8 {. O0 `" |4 P) T& ~1 D+ d0 B Remote Access Server (RAS) Modems2 [9 G7 i( w& k2 B* @( x8 R
ADSL (Assymetric Digital Subscriber Line)& I; c* i8 T9 V- [8 _7 b
Digital Cellular Telephones) f# t1 L- T+ u& W3 @4 J' P$ H
GSM Handset Using SoftFone™ Baseband Processor
* n6 d6 `! p% j) S6 Fand Othello™ Radio3 K" i" X+ V$ B
Analog Cellular Basestations
9 M6 E2 v# f2 ^0 U; Q6 E Digital Cellular Basestations0 v* |3 K; N3 R
Motor Control
) u! O$ \: g: y& }2 H+ F5 K- R Codecs and DSPs in Voiceband and Audio Applications! g ^9 j; R4 d6 k) I
A Sigma-Delta ADC with Programmable Digital Filter
5 U9 t4 o. K- a+ TSECTION 10
( C4 }2 l# f2 {8 g3 R5 }6 k1 [ U$ uHARDWARE DESIGN TECHNIQUES* Y8 {1 p: Y% r; L4 a @3 k
Low Voltage Interfaces1 L1 e3 j' Z( o9 B1 t* R6 f+ D
Grounding in Mixed Signal Systems+ N& @; o5 [+ A8 U7 k# y9 e
Digital Isolation Techniques
- |% A$ T2 n7 D1 z3 g; N4 K0 S! K Power Supply Noise Reduction and Filtering4 n9 D7 g* J9 i7 s) X; S& J
Dealing with High Speed Logic' _0 Q% Z C; G2 j8 |& f- R: ] f3 m; @+ U
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