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Since the earliest days of microprocessors, system designers have been plagued by a problem in which the
6 p j9 `& M$ v/ T: ^# T: Dspeed of the CPU's operation exceeded the bandwidth of the memory subsystem to which it was connected.' Y! c$ \0 m4 o0 @
To avoid wasting CPU cycles while waiting for the memory to fetch the requested data, the universally# s) n. N o) d' E
adopted solution was to use an area of faster (and thus more expensive) memory to cache main memory data.
' q: Y: ^; r" P" q3 ZThis solution allowed the CPU to operate at its natural speed as long as the data it required was available in
5 J6 f/ x1 J& Z5 e8 \the cache. |
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