我用cadence16.5 conceptHDL设计原理图，完成后道pCB，我使用的Top-down式原理图设计方式! {! E0 C* x! V) s) X! n
导PCB时提示“Connectitivity server is unable to load design. The .xcon file might be missing or incorrect. Your design needs to be netlisted in 16.4 or later version of Design Entry HDL"9 o+ \' Z1 g, I
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发表于 2016-8-4 20:08
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支持！
反对！