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PCB图进行DRC检测, i: f' M$ k' f( S5 ^2 [2 @
选择其中Clearance Constraints Max/Min Width Constraints Short Circuit Constraints 和Un-Routed Nets Constraints 这几项(请大家帮忙看看是什么问题,我是自学的protel,尚不熟练,请指教!谢谢!)' G1 _/ v/ l5 ?* n* I6 v
结果如下:3 j. J" J; h! r9 b' I1 I, k
Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Prefered=10mil) (On the board )
\, E2 S4 s+ X* N Violation Polygon Arc (6033.874mil,6670.183mil) TopLayer Actual Width = 8mil
) O2 }$ F2 c+ X; ^+ c$ P ] Violation Polygon Arc (6019.943mil,6665.654mil) TopLayer Actual Width = 8mil- y( s7 G% i! a2 r/ M
Violation Polygon Arc (6006.011mil,6661.126mil) TopLayer Actual Width = 8mil% D0 Z: ?, Y1 x4 K: t
Violation Polygon Arc (5992.08mil,6656.597mil) TopLayer Actual Width = 8mil' W6 j3 G* i* N3 T1 I2 j' T
……
+ ~& n( E8 p4 U `More than 120 violations detected. DRC stopped!
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