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PCB图进行DRC检测
! g: [% H0 R& D选择其中Clearance Constraints Max/Min Width Constraints Short Circuit Constraints 和Un-Routed Nets Constraints 这几项(请大家帮忙看看是什么问题,我是自学的protel,尚不熟练,请指教!谢谢!)) P9 T+ b2 M' m7 c' u5 T
结果如下:
4 X2 y( ~% m9 E' r+ qProcessing Rule : Width Constraint (Min=10mil) (Max=10mil) (Prefered=10mil) (On the board )) s. @1 R7 y+ @+ g
Violation Polygon Arc (6033.874mil,6670.183mil) TopLayer Actual Width = 8mil$ Q h1 {, Z) e
Violation Polygon Arc (6019.943mil,6665.654mil) TopLayer Actual Width = 8mil3 O7 I" I6 A! L e. I
Violation Polygon Arc (6006.011mil,6661.126mil) TopLayer Actual Width = 8mil
# [4 l& i& P" B) K7 Y$ U. @- x+ K Violation Polygon Arc (5992.08mil,6656.597mil) TopLayer Actual Width = 8mil
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More than 120 violations detected. DRC stopped!
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