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我的设计已经没有错误，session log也没有报错，但是就是把生成网表的过程给终止掉了，太诡异了 b) X7 X5 }- H% _- F
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********************************************************************************
. ^9 j$ f6 d; S( b9 a; L** Netlisting the design " Z3 v0 J3 L! O2 f* u* B) U
********************************************************************************
5 m: X4 z8 g, h+ fDesign Name:
, F# S7 e- W' I0 lE:\cadence\RF7021\rf7021.dsn
( p5 z/ }8 \% r1 r4 DNetlist Directory:; |% `' d. O, C' ?2 T0 G
E:\CADENCE\RF7021
! _- Q& ~7 w& M6 l5 pConfiguration File:7 I' O1 e8 `% P8 C
C:\Cadence\PSD_15.1\tools\capture\allegro.cfg4 G% S1 B* _( ]4 f3 b
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Spawning... "C:\Cadence\PSD_15.1\tools\capture\pstswp.exe" -pst -d "E:\cadence\RF7021\rf7021.dsn" -n "E:\CADENCE\RF7021" -c "C:\Cadence\PSD_15.1\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"0 M/ G; T2 R \' x& Y- w; _7 I
#1 Aborting Netlisting... Please correct the above errors and retry.
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& Z& u+ _+ t" Q' I/ b* _Exiting... "C:\Cadence\PSD_15.1\tools\capture\pstswp.exe" -pst -d "E:\cadence\RF7021\rf7021.dsn" -n "E:\CADENCE\RF7021" -c "C:\Cadence\PSD_15.1\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint": Z1 b% x& ~& e1 S* W
. c8 K2 H$ G1 ?+ O*** Done *** ^0 Z( @' V/ } ~; y
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# o: C# D! l3 G/ m9 B没有错误为什么还要终止啊，哪位牛人指点一下，help |
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发表于 2008-10-17 11:24
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淘帖
支持！
反对！
发表于 2008-10-21 13:25